1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Assembly Matcher Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_ASSEMBLER_HEADER 11#undef GET_ASSEMBLER_HEADER 12 // This should be included into the middle of the declaration of 13 // your subclasses implementation of MCTargetAsmParser. 14 FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const; 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 16 const OperandVector &Operands); 17 void convertToMapAndConstraints(unsigned Kind, 18 const OperandVector &Operands) override; 19 unsigned MatchInstructionImpl(const OperandVector &Operands, 20 MCInst &Inst, 21 uint64_t &ErrorInfo, 22 FeatureBitset &MissingFeatures, 23 bool matchingInlineAsm, 24 unsigned VariantID = 0); 25 unsigned MatchInstructionImpl(const OperandVector &Operands, 26 MCInst &Inst, 27 uint64_t &ErrorInfo, 28 bool matchingInlineAsm, 29 unsigned VariantID = 0) { 30 FeatureBitset MissingFeatures; 31 return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, 32 matchingInlineAsm, VariantID); 33 } 34 35 OperandMatchResultTy MatchOperandParserImpl( 36 OperandVector &Operands, 37 StringRef Mnemonic, 38 bool ParseForAllFeatures = false); 39 OperandMatchResultTy tryCustomParseOperand( 40 OperandVector &Operands, 41 unsigned MCK); 42 43#endif // GET_ASSEMBLER_HEADER_INFO 44 45 46#ifdef GET_OPERAND_DIAGNOSTIC_TYPES 47#undef GET_OPERAND_DIAGNOSTIC_TYPES 48 49 Match_InvalidBareSymbol, 50 Match_InvalidCLUIImm, 51 Match_InvalidCSRSystemRegister, 52 Match_InvalidCallSymbol, 53 Match_InvalidFRMArg, 54 Match_InvalidFenceArg, 55 Match_InvalidImmXLenLI, 56 Match_InvalidImmZero, 57 Match_InvalidSImm10Lsb0000NonZero, 58 Match_InvalidSImm12, 59 Match_InvalidSImm12Lsb0, 60 Match_InvalidSImm13Lsb0, 61 Match_InvalidSImm21Lsb0JAL, 62 Match_InvalidSImm6, 63 Match_InvalidSImm6NonZero, 64 Match_InvalidSImm9Lsb0, 65 Match_InvalidTPRelAddSymbol, 66 Match_InvalidUImm10Lsb00NonZero, 67 Match_InvalidUImm20AUIPC, 68 Match_InvalidUImm20LUI, 69 Match_InvalidUImm5, 70 Match_InvalidUImm7Lsb00, 71 Match_InvalidUImm8Lsb00, 72 Match_InvalidUImm8Lsb000, 73 Match_InvalidUImm9Lsb000, 74 Match_InvalidUImmLog2XLen, 75 Match_InvalidUImmLog2XLenNonZero, 76 END_OPERAND_DIAGNOSTIC_TYPES 77#endif // GET_OPERAND_DIAGNOSTIC_TYPES 78 79 80#ifdef GET_REGISTER_MATCHER 81#undef GET_REGISTER_MATCHER 82 83// Bits for subtarget features that participate in instruction matching. 84enum SubtargetFeatureBits : uint8_t { 85 Feature_HasStdExtMBit = 5, 86 Feature_HasStdExtABit = 1, 87 Feature_HasStdExtFBit = 4, 88 Feature_HasStdExtDBit = 3, 89 Feature_HasStdExtCBit = 2, 90 Feature_HasRVCHintsBit = 0, 91 Feature_IsRV64Bit = 8, 92 Feature_IsRV32Bit = 6, 93 Feature_IsRV32EBit = 7, 94}; 95 96static unsigned MatchRegisterName(StringRef Name) { 97 switch (Name.size()) { 98 default: break; 99 case 2: // 30 strings to match. 100 switch (Name[0]) { 101 default: break; 102 case 'f': // 20 strings to match. 103 switch (Name[1]) { 104 default: break; 105 case '0': // 2 strings to match. 106 return 33; // "f0" 107 case '1': // 2 strings to match. 108 return 34; // "f1" 109 case '2': // 2 strings to match. 110 return 35; // "f2" 111 case '3': // 2 strings to match. 112 return 36; // "f3" 113 case '4': // 2 strings to match. 114 return 37; // "f4" 115 case '5': // 2 strings to match. 116 return 38; // "f5" 117 case '6': // 2 strings to match. 118 return 39; // "f6" 119 case '7': // 2 strings to match. 120 return 40; // "f7" 121 case '8': // 2 strings to match. 122 return 41; // "f8" 123 case '9': // 2 strings to match. 124 return 42; // "f9" 125 } 126 break; 127 case 'x': // 10 strings to match. 128 switch (Name[1]) { 129 default: break; 130 case '0': // 1 string to match. 131 return 1; // "x0" 132 case '1': // 1 string to match. 133 return 2; // "x1" 134 case '2': // 1 string to match. 135 return 3; // "x2" 136 case '3': // 1 string to match. 137 return 4; // "x3" 138 case '4': // 1 string to match. 139 return 5; // "x4" 140 case '5': // 1 string to match. 141 return 6; // "x5" 142 case '6': // 1 string to match. 143 return 7; // "x6" 144 case '7': // 1 string to match. 145 return 8; // "x7" 146 case '8': // 1 string to match. 147 return 9; // "x8" 148 case '9': // 1 string to match. 149 return 10; // "x9" 150 } 151 break; 152 } 153 break; 154 case 3: // 66 strings to match. 155 switch (Name[0]) { 156 default: break; 157 case 'f': // 44 strings to match. 158 switch (Name[1]) { 159 default: break; 160 case '1': // 20 strings to match. 161 switch (Name[2]) { 162 default: break; 163 case '0': // 2 strings to match. 164 return 43; // "f10" 165 case '1': // 2 strings to match. 166 return 44; // "f11" 167 case '2': // 2 strings to match. 168 return 45; // "f12" 169 case '3': // 2 strings to match. 170 return 46; // "f13" 171 case '4': // 2 strings to match. 172 return 47; // "f14" 173 case '5': // 2 strings to match. 174 return 48; // "f15" 175 case '6': // 2 strings to match. 176 return 49; // "f16" 177 case '7': // 2 strings to match. 178 return 50; // "f17" 179 case '8': // 2 strings to match. 180 return 51; // "f18" 181 case '9': // 2 strings to match. 182 return 52; // "f19" 183 } 184 break; 185 case '2': // 20 strings to match. 186 switch (Name[2]) { 187 default: break; 188 case '0': // 2 strings to match. 189 return 53; // "f20" 190 case '1': // 2 strings to match. 191 return 54; // "f21" 192 case '2': // 2 strings to match. 193 return 55; // "f22" 194 case '3': // 2 strings to match. 195 return 56; // "f23" 196 case '4': // 2 strings to match. 197 return 57; // "f24" 198 case '5': // 2 strings to match. 199 return 58; // "f25" 200 case '6': // 2 strings to match. 201 return 59; // "f26" 202 case '7': // 2 strings to match. 203 return 60; // "f27" 204 case '8': // 2 strings to match. 205 return 61; // "f28" 206 case '9': // 2 strings to match. 207 return 62; // "f29" 208 } 209 break; 210 case '3': // 4 strings to match. 211 switch (Name[2]) { 212 default: break; 213 case '0': // 2 strings to match. 214 return 63; // "f30" 215 case '1': // 2 strings to match. 216 return 64; // "f31" 217 } 218 break; 219 } 220 break; 221 case 'x': // 22 strings to match. 222 switch (Name[1]) { 223 default: break; 224 case '1': // 10 strings to match. 225 switch (Name[2]) { 226 default: break; 227 case '0': // 1 string to match. 228 return 11; // "x10" 229 case '1': // 1 string to match. 230 return 12; // "x11" 231 case '2': // 1 string to match. 232 return 13; // "x12" 233 case '3': // 1 string to match. 234 return 14; // "x13" 235 case '4': // 1 string to match. 236 return 15; // "x14" 237 case '5': // 1 string to match. 238 return 16; // "x15" 239 case '6': // 1 string to match. 240 return 17; // "x16" 241 case '7': // 1 string to match. 242 return 18; // "x17" 243 case '8': // 1 string to match. 244 return 19; // "x18" 245 case '9': // 1 string to match. 246 return 20; // "x19" 247 } 248 break; 249 case '2': // 10 strings to match. 250 switch (Name[2]) { 251 default: break; 252 case '0': // 1 string to match. 253 return 21; // "x20" 254 case '1': // 1 string to match. 255 return 22; // "x21" 256 case '2': // 1 string to match. 257 return 23; // "x22" 258 case '3': // 1 string to match. 259 return 24; // "x23" 260 case '4': // 1 string to match. 261 return 25; // "x24" 262 case '5': // 1 string to match. 263 return 26; // "x25" 264 case '6': // 1 string to match. 265 return 27; // "x26" 266 case '7': // 1 string to match. 267 return 28; // "x27" 268 case '8': // 1 string to match. 269 return 29; // "x28" 270 case '9': // 1 string to match. 271 return 30; // "x29" 272 } 273 break; 274 case '3': // 2 strings to match. 275 switch (Name[2]) { 276 default: break; 277 case '0': // 1 string to match. 278 return 31; // "x30" 279 case '1': // 1 string to match. 280 return 32; // "x31" 281 } 282 break; 283 } 284 break; 285 } 286 break; 287 } 288 return 0; 289} 290 291static unsigned MatchRegisterAltName(StringRef Name) { 292 switch (Name.size()) { 293 default: break; 294 case 2: // 30 strings to match. 295 switch (Name[0]) { 296 default: break; 297 case 'a': // 8 strings to match. 298 switch (Name[1]) { 299 default: break; 300 case '0': // 1 string to match. 301 return 11; // "a0" 302 case '1': // 1 string to match. 303 return 12; // "a1" 304 case '2': // 1 string to match. 305 return 13; // "a2" 306 case '3': // 1 string to match. 307 return 14; // "a3" 308 case '4': // 1 string to match. 309 return 15; // "a4" 310 case '5': // 1 string to match. 311 return 16; // "a5" 312 case '6': // 1 string to match. 313 return 17; // "a6" 314 case '7': // 1 string to match. 315 return 18; // "a7" 316 } 317 break; 318 case 'f': // 1 string to match. 319 if (Name[1] != 'p') 320 break; 321 return 9; // "fp" 322 case 'g': // 1 string to match. 323 if (Name[1] != 'p') 324 break; 325 return 4; // "gp" 326 case 'r': // 1 string to match. 327 if (Name[1] != 'a') 328 break; 329 return 2; // "ra" 330 case 's': // 11 strings to match. 331 switch (Name[1]) { 332 default: break; 333 case '0': // 1 string to match. 334 return 9; // "s0" 335 case '1': // 1 string to match. 336 return 10; // "s1" 337 case '2': // 1 string to match. 338 return 19; // "s2" 339 case '3': // 1 string to match. 340 return 20; // "s3" 341 case '4': // 1 string to match. 342 return 21; // "s4" 343 case '5': // 1 string to match. 344 return 22; // "s5" 345 case '6': // 1 string to match. 346 return 23; // "s6" 347 case '7': // 1 string to match. 348 return 24; // "s7" 349 case '8': // 1 string to match. 350 return 25; // "s8" 351 case '9': // 1 string to match. 352 return 26; // "s9" 353 case 'p': // 1 string to match. 354 return 3; // "sp" 355 } 356 break; 357 case 't': // 8 strings to match. 358 switch (Name[1]) { 359 default: break; 360 case '0': // 1 string to match. 361 return 6; // "t0" 362 case '1': // 1 string to match. 363 return 7; // "t1" 364 case '2': // 1 string to match. 365 return 8; // "t2" 366 case '3': // 1 string to match. 367 return 29; // "t3" 368 case '4': // 1 string to match. 369 return 30; // "t4" 370 case '5': // 1 string to match. 371 return 31; // "t5" 372 case '6': // 1 string to match. 373 return 32; // "t6" 374 case 'p': // 1 string to match. 375 return 5; // "tp" 376 } 377 break; 378 } 379 break; 380 case 3: // 58 strings to match. 381 switch (Name[0]) { 382 default: break; 383 case 'f': // 56 strings to match. 384 switch (Name[1]) { 385 default: break; 386 case 'a': // 16 strings to match. 387 switch (Name[2]) { 388 default: break; 389 case '0': // 2 strings to match. 390 return 43; // "fa0" 391 case '1': // 2 strings to match. 392 return 44; // "fa1" 393 case '2': // 2 strings to match. 394 return 45; // "fa2" 395 case '3': // 2 strings to match. 396 return 46; // "fa3" 397 case '4': // 2 strings to match. 398 return 47; // "fa4" 399 case '5': // 2 strings to match. 400 return 48; // "fa5" 401 case '6': // 2 strings to match. 402 return 49; // "fa6" 403 case '7': // 2 strings to match. 404 return 50; // "fa7" 405 } 406 break; 407 case 's': // 20 strings to match. 408 switch (Name[2]) { 409 default: break; 410 case '0': // 2 strings to match. 411 return 41; // "fs0" 412 case '1': // 2 strings to match. 413 return 42; // "fs1" 414 case '2': // 2 strings to match. 415 return 51; // "fs2" 416 case '3': // 2 strings to match. 417 return 52; // "fs3" 418 case '4': // 2 strings to match. 419 return 53; // "fs4" 420 case '5': // 2 strings to match. 421 return 54; // "fs5" 422 case '6': // 2 strings to match. 423 return 55; // "fs6" 424 case '7': // 2 strings to match. 425 return 56; // "fs7" 426 case '8': // 2 strings to match. 427 return 57; // "fs8" 428 case '9': // 2 strings to match. 429 return 58; // "fs9" 430 } 431 break; 432 case 't': // 20 strings to match. 433 switch (Name[2]) { 434 default: break; 435 case '0': // 2 strings to match. 436 return 33; // "ft0" 437 case '1': // 2 strings to match. 438 return 34; // "ft1" 439 case '2': // 2 strings to match. 440 return 35; // "ft2" 441 case '3': // 2 strings to match. 442 return 36; // "ft3" 443 case '4': // 2 strings to match. 444 return 37; // "ft4" 445 case '5': // 2 strings to match. 446 return 38; // "ft5" 447 case '6': // 2 strings to match. 448 return 39; // "ft6" 449 case '7': // 2 strings to match. 450 return 40; // "ft7" 451 case '8': // 2 strings to match. 452 return 61; // "ft8" 453 case '9': // 2 strings to match. 454 return 62; // "ft9" 455 } 456 break; 457 } 458 break; 459 case 's': // 2 strings to match. 460 if (Name[1] != '1') 461 break; 462 switch (Name[2]) { 463 default: break; 464 case '0': // 1 string to match. 465 return 27; // "s10" 466 case '1': // 1 string to match. 467 return 28; // "s11" 468 } 469 break; 470 } 471 break; 472 case 4: // 9 strings to match. 473 switch (Name[0]) { 474 default: break; 475 case 'f': // 8 strings to match. 476 switch (Name[1]) { 477 default: break; 478 case 's': // 4 strings to match. 479 if (Name[2] != '1') 480 break; 481 switch (Name[3]) { 482 default: break; 483 case '0': // 2 strings to match. 484 return 59; // "fs10" 485 case '1': // 2 strings to match. 486 return 60; // "fs11" 487 } 488 break; 489 case 't': // 4 strings to match. 490 if (Name[2] != '1') 491 break; 492 switch (Name[3]) { 493 default: break; 494 case '0': // 2 strings to match. 495 return 63; // "ft10" 496 case '1': // 2 strings to match. 497 return 64; // "ft11" 498 } 499 break; 500 } 501 break; 502 case 'z': // 1 string to match. 503 if (memcmp(Name.data()+1, "ero", 3) != 0) 504 break; 505 return 1; // "zero" 506 } 507 break; 508 } 509 return 0; 510} 511 512#endif // GET_REGISTER_MATCHER 513 514 515#ifdef GET_SUBTARGET_FEATURE_NAME 516#undef GET_SUBTARGET_FEATURE_NAME 517 518// User-level names for subtarget features that participate in 519// instruction matching. 520static const char *getSubtargetFeatureName(uint64_t Val) { 521 switch(Val) { 522 case Feature_HasStdExtMBit: return "'M' (Integer Multiplication and Division)"; 523 case Feature_HasStdExtABit: return "'A' (Atomic Instructions)"; 524 case Feature_HasStdExtFBit: return "'F' (Single-Precision Floating-Point)"; 525 case Feature_HasStdExtDBit: return "'D' (Double-Precision Floating-Point)"; 526 case Feature_HasStdExtCBit: return "'C' (Compressed Instructions)"; 527 case Feature_HasRVCHintsBit: return "RVC Hint Instructions"; 528 case Feature_IsRV64Bit: return "RV64I Base Instruction Set"; 529 case Feature_IsRV32Bit: return "RV32I Base Instruction Set"; 530 case Feature_IsRV32EBit: return ""; 531 default: return "(unknown)"; 532 } 533} 534 535#endif // GET_SUBTARGET_FEATURE_NAME 536 537 538#ifdef GET_MATCHER_IMPLEMENTATION 539#undef GET_MATCHER_IMPLEMENTATION 540 541static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { 542 switch (VariantID) { 543 case 0: 544 switch (Mnemonic.size()) { 545 default: break; 546 case 4: // 1 string to match. 547 if (memcmp(Mnemonic.data()+0, "move", 4) != 0) 548 break; 549 Mnemonic = "mv"; // "move" 550 return; 551 case 5: // 1 string to match. 552 if (memcmp(Mnemonic.data()+0, "scall", 5) != 0) 553 break; 554 Mnemonic = "ecall"; // "scall" 555 return; 556 case 6: // 1 string to match. 557 if (memcmp(Mnemonic.data()+0, "sbreak", 6) != 0) 558 break; 559 Mnemonic = "ebreak"; // "sbreak" 560 return; 561 case 7: // 2 strings to match. 562 if (memcmp(Mnemonic.data()+0, "fmv.", 4) != 0) 563 break; 564 switch (Mnemonic[4]) { 565 default: break; 566 case 's': // 1 string to match. 567 if (memcmp(Mnemonic.data()+5, ".x", 2) != 0) 568 break; 569 if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x" 570 Mnemonic = "fmv.w.x"; 571 return; 572 case 'x': // 1 string to match. 573 if (memcmp(Mnemonic.data()+5, ".s", 2) != 0) 574 break; 575 if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s" 576 Mnemonic = "fmv.x.w"; 577 return; 578 } 579 break; 580 } 581 break; 582 } 583 switch (Mnemonic.size()) { 584 default: break; 585 case 4: // 1 string to match. 586 if (memcmp(Mnemonic.data()+0, "move", 4) != 0) 587 break; 588 Mnemonic = "mv"; // "move" 589 return; 590 case 5: // 1 string to match. 591 if (memcmp(Mnemonic.data()+0, "scall", 5) != 0) 592 break; 593 Mnemonic = "ecall"; // "scall" 594 return; 595 case 6: // 1 string to match. 596 if (memcmp(Mnemonic.data()+0, "sbreak", 6) != 0) 597 break; 598 Mnemonic = "ebreak"; // "sbreak" 599 return; 600 case 7: // 2 strings to match. 601 if (memcmp(Mnemonic.data()+0, "fmv.", 4) != 0) 602 break; 603 switch (Mnemonic[4]) { 604 default: break; 605 case 's': // 1 string to match. 606 if (memcmp(Mnemonic.data()+5, ".x", 2) != 0) 607 break; 608 if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x" 609 Mnemonic = "fmv.w.x"; 610 return; 611 case 'x': // 1 string to match. 612 if (memcmp(Mnemonic.data()+5, ".s", 2) != 0) 613 break; 614 if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s" 615 Mnemonic = "fmv.x.w"; 616 return; 617 } 618 break; 619 } 620} 621 622enum { 623 Tie0_1_1, 624}; 625 626static const uint8_t TiedAsmOperandTable[][3] = { 627 /* Tie0_1_1 */ { 0, 1, 1 }, 628}; 629 630namespace { 631enum OperatorConversionKind { 632 CVT_Done, 633 CVT_Reg, 634 CVT_Tied, 635 CVT_95_Reg, 636 CVT_95_addImmOperands, 637 CVT_95_addRegOperands, 638 CVT_regX0, 639 CVT_imm_95_0, 640 CVT_95_addCSRSystemRegisterOperands, 641 CVT_imm_95_7, 642 CVT_95_addFRMArgOperands, 643 CVT_imm_95_15, 644 CVT_95_addFenceArgOperands, 645 CVT_imm_95_3, 646 CVT_imm_95_1, 647 CVT_imm_95_2, 648 CVT_regX1, 649 CVT_imm_95__MINUS_1, 650 CVT_imm_95_3072, 651 CVT_imm_95_3200, 652 CVT_imm_95_3074, 653 CVT_imm_95_3202, 654 CVT_imm_95_3073, 655 CVT_imm_95_3201, 656 CVT_NUM_CONVERTERS 657}; 658 659enum InstructionConversionKind { 660 Convert__Reg1_0__Reg1_1__Reg1_2, 661 Convert__Reg1_0__Reg1_1__SImm121_2, 662 Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, 663 Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, 664 Convert__Reg1_0__UImm20AUIPC1_1, 665 Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, 666 Convert__Reg1_0__regX0__SImm13Lsb01_1, 667 Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, 668 Convert__regX0__Reg1_0__SImm13Lsb01_1, 669 Convert__Reg1_0__Tie0_1_1__Reg1_1, 670 Convert__Reg1_0__Tie0_1_1__ImmZero1_1, 671 Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1, 672 Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, 673 Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, 674 Convert__Reg1_0__Tie0_1_1__SImm61_1, 675 Convert__Reg1_0__SImm9Lsb01_1, 676 Convert_NoOperands, 677 Convert__Reg1_0__Reg1_2__imm_95_0, 678 Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, 679 Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, 680 Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, 681 Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, 682 Convert__SImm12Lsb01_0, 683 Convert__Reg1_0, 684 Convert__Reg1_0__SImm61_1, 685 Convert__Reg1_0__CLUIImm1_1, 686 Convert__Reg1_0__Reg1_1, 687 Convert__SImm6NonZero1_0, 688 Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, 689 Convert__Reg1_0__Tie0_1_1, 690 Convert__CallSymbol1_0, 691 Convert__Reg1_0__CallSymbol1_1, 692 Convert__regX0__CSRSystemRegister1_0__Reg1_1, 693 Convert__regX0__CSRSystemRegister1_0__UImm51_1, 694 Convert__Reg1_0__CSRSystemRegister1_1__regX0, 695 Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, 696 Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, 697 Convert__Reg1_0__Reg1_1__Reg1_1, 698 Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, 699 Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, 700 Convert__Reg1_0__Reg1_1__imm_95_7, 701 Convert__Reg1_0__Reg1_1__FRMArg1_2, 702 Convert__imm_95_15__imm_95_15, 703 Convert__FenceArg1_0__FenceArg1_1, 704 Convert__Reg1_0__Reg1_2__Reg1_1, 705 Convert__Reg1_0__Reg1_2__BareSymbol1_1, 706 Convert__Reg1_0__Reg1_3__SImm121_1, 707 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, 708 Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, 709 Convert__Reg1_0__imm_95_3__regX0, 710 Convert__Reg1_0__imm_95_1__regX0, 711 Convert__Reg1_0__imm_95_2__regX0, 712 Convert__regX0__imm_95_3__Reg1_0, 713 Convert__Reg1_0__imm_95_3__Reg1_1, 714 Convert__regX0__imm_95_1__Reg1_0, 715 Convert__Reg1_0__imm_95_1__Reg1_1, 716 Convert__regX0__imm_95_1__UImm51_0, 717 Convert__Reg1_0__imm_95_1__UImm51_1, 718 Convert__regX0__imm_95_2__Reg1_0, 719 Convert__Reg1_0__imm_95_2__Reg1_1, 720 Convert__regX0__imm_95_2__UImm51_0, 721 Convert__Reg1_0__imm_95_2__UImm51_1, 722 Convert__regX0__SImm21Lsb0JAL1_0, 723 Convert__regX1__SImm21Lsb0JAL1_0, 724 Convert__Reg1_0__SImm21Lsb0JAL1_1, 725 Convert__regX1__Reg1_0__imm_95_0, 726 Convert__Reg1_0__Reg1_1__imm_95_0, 727 Convert__regX1__Reg1_0__SImm121_1, 728 Convert__regX1__Reg1_2__SImm121_0, 729 Convert__regX0__Reg1_0__imm_95_0, 730 Convert__regX0__Reg1_0__SImm121_1, 731 Convert__regX0__Reg1_2__SImm121_0, 732 Convert__Reg1_0__BareSymbol1_1, 733 Convert__Reg1_0__ImmXLenLI1_1, 734 Convert__Reg1_0__AtomicMemOpOperand1_1, 735 Convert__Reg1_0__UImm20LUI1_1, 736 Convert__imm_95_0__imm_95_0, 737 Convert__Reg1_0__regX0__Reg1_1, 738 Convert__regX0__regX0__imm_95_0, 739 Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, 740 Convert__Reg1_0__imm_95_3072__regX0, 741 Convert__Reg1_0__imm_95_3200__regX0, 742 Convert__Reg1_0__imm_95_3074__regX0, 743 Convert__Reg1_0__imm_95_3202__regX0, 744 Convert__Reg1_0__imm_95_3073__regX0, 745 Convert__Reg1_0__imm_95_3201__regX0, 746 Convert__regX0__regX1__imm_95_0, 747 Convert__Reg1_0__Reg1_1__imm_95_1, 748 Convert__regX0__regX0, 749 Convert__Reg1_0__regX0, 750 Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, 751 Convert__Reg1_0__Reg1_1__UImm51_2, 752 Convert__Reg1_0__Reg1_1__regX0, 753 CVT_NUM_SIGNATURES 754}; 755 756} // end anonymous namespace 757 758static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = { 759 // Convert__Reg1_0__Reg1_1__Reg1_2 760 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 761 // Convert__Reg1_0__Reg1_1__SImm121_2 762 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 763 // Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3 764 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done }, 765 // Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1 766 { CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_Reg, 2, CVT_Done }, 767 // Convert__Reg1_0__UImm20AUIPC1_1 768 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 769 // Convert__Reg1_0__Reg1_1__SImm13Lsb01_2 770 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 771 // Convert__Reg1_0__regX0__SImm13Lsb01_1 772 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done }, 773 // Convert__Reg1_1__Reg1_0__SImm13Lsb01_2 774 { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done }, 775 // Convert__regX0__Reg1_0__SImm13Lsb01_1 776 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 777 // Convert__Reg1_0__Tie0_1_1__Reg1_1 778 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done }, 779 // Convert__Reg1_0__Tie0_1_1__ImmZero1_1 780 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 781 // Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1 782 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 783 // Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1 784 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 785 // Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2 786 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 787 // Convert__Reg1_0__Tie0_1_1__SImm61_1 788 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 789 // Convert__Reg1_0__SImm9Lsb01_1 790 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 791 // Convert_NoOperands 792 { CVT_Done }, 793 // Convert__Reg1_0__Reg1_2__imm_95_0 794 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done }, 795 // Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1 796 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 797 // Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1 798 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 799 // Convert__Reg1_0__Reg1_3__UImm7Lsb001_1 800 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 801 // Convert__Reg1_0__Reg1_3__UImm8Lsb001_1 802 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 803 // Convert__SImm12Lsb01_0 804 { CVT_95_addImmOperands, 1, CVT_Done }, 805 // Convert__Reg1_0 806 { CVT_95_Reg, 1, CVT_Done }, 807 // Convert__Reg1_0__SImm61_1 808 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 809 // Convert__Reg1_0__CLUIImm1_1 810 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 811 // Convert__Reg1_0__Reg1_1 812 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, 813 // Convert__SImm6NonZero1_0 814 { CVT_95_addImmOperands, 1, CVT_Done }, 815 // Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1 816 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done }, 817 // Convert__Reg1_0__Tie0_1_1 818 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done }, 819 // Convert__CallSymbol1_0 820 { CVT_95_addImmOperands, 1, CVT_Done }, 821 // Convert__Reg1_0__CallSymbol1_1 822 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 823 // Convert__regX0__CSRSystemRegister1_0__Reg1_1 824 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done }, 825 // Convert__regX0__CSRSystemRegister1_0__UImm51_1 826 { CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 827 // Convert__Reg1_0__CSRSystemRegister1_1__regX0 828 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_regX0, 0, CVT_Done }, 829 // Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2 830 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_Reg, 3, CVT_Done }, 831 // Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2 832 { CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 833 // Convert__Reg1_0__Reg1_1__Reg1_1 834 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_Done }, 835 // Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7 836 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_7, 0, CVT_Done }, 837 // Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3 838 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addFRMArgOperands, 4, CVT_Done }, 839 // Convert__Reg1_0__Reg1_1__imm_95_7 840 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done }, 841 // Convert__Reg1_0__Reg1_1__FRMArg1_2 842 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done }, 843 // Convert__imm_95_15__imm_95_15 844 { CVT_imm_95_15, 0, CVT_imm_95_15, 0, CVT_Done }, 845 // Convert__FenceArg1_0__FenceArg1_1 846 { CVT_95_addFenceArgOperands, 1, CVT_95_addFenceArgOperands, 2, CVT_Done }, 847 // Convert__Reg1_0__Reg1_2__Reg1_1 848 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done }, 849 // Convert__Reg1_0__Reg1_2__BareSymbol1_1 850 { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Done }, 851 // Convert__Reg1_0__Reg1_3__SImm121_1 852 { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done }, 853 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7 854 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_7, 0, CVT_Done }, 855 // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4 856 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addFRMArgOperands, 5, CVT_Done }, 857 // Convert__Reg1_0__imm_95_3__regX0 858 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_regX0, 0, CVT_Done }, 859 // Convert__Reg1_0__imm_95_1__regX0 860 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_regX0, 0, CVT_Done }, 861 // Convert__Reg1_0__imm_95_2__regX0 862 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_regX0, 0, CVT_Done }, 863 // Convert__regX0__imm_95_3__Reg1_0 864 { CVT_regX0, 0, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done }, 865 // Convert__Reg1_0__imm_95_3__Reg1_1 866 { CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done }, 867 // Convert__regX0__imm_95_1__Reg1_0 868 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done }, 869 // Convert__Reg1_0__imm_95_1__Reg1_1 870 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done }, 871 // Convert__regX0__imm_95_1__UImm51_0 872 { CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_addImmOperands, 1, CVT_Done }, 873 // Convert__Reg1_0__imm_95_1__UImm51_1 874 { CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_addImmOperands, 2, CVT_Done }, 875 // Convert__regX0__imm_95_2__Reg1_0 876 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done }, 877 // Convert__Reg1_0__imm_95_2__Reg1_1 878 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done }, 879 // Convert__regX0__imm_95_2__UImm51_0 880 { CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_addImmOperands, 1, CVT_Done }, 881 // Convert__Reg1_0__imm_95_2__UImm51_1 882 { CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_addImmOperands, 2, CVT_Done }, 883 // Convert__regX0__SImm21Lsb0JAL1_0 884 { CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done }, 885 // Convert__regX1__SImm21Lsb0JAL1_0 886 { CVT_regX1, 0, CVT_95_addImmOperands, 1, CVT_Done }, 887 // Convert__Reg1_0__SImm21Lsb0JAL1_1 888 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 889 // Convert__regX1__Reg1_0__imm_95_0 890 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done }, 891 // Convert__Reg1_0__Reg1_1__imm_95_0 892 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done }, 893 // Convert__regX1__Reg1_0__SImm121_1 894 { CVT_regX1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 895 // Convert__regX1__Reg1_2__SImm121_0 896 { CVT_regX1, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done }, 897 // Convert__regX0__Reg1_0__imm_95_0 898 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done }, 899 // Convert__regX0__Reg1_0__SImm121_1 900 { CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 901 // Convert__regX0__Reg1_2__SImm121_0 902 { CVT_regX0, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done }, 903 // Convert__Reg1_0__BareSymbol1_1 904 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 905 // Convert__Reg1_0__ImmXLenLI1_1 906 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 907 // Convert__Reg1_0__AtomicMemOpOperand1_1 908 { CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done }, 909 // Convert__Reg1_0__UImm20LUI1_1 910 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 911 // Convert__imm_95_0__imm_95_0 912 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done }, 913 // Convert__Reg1_0__regX0__Reg1_1 914 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done }, 915 // Convert__regX0__regX0__imm_95_0 916 { CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done }, 917 // Convert__Reg1_0__Reg1_1__imm_95__MINUS_1 918 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_Done }, 919 // Convert__Reg1_0__imm_95_3072__regX0 920 { CVT_95_Reg, 1, CVT_imm_95_3072, 0, CVT_regX0, 0, CVT_Done }, 921 // Convert__Reg1_0__imm_95_3200__regX0 922 { CVT_95_Reg, 1, CVT_imm_95_3200, 0, CVT_regX0, 0, CVT_Done }, 923 // Convert__Reg1_0__imm_95_3074__regX0 924 { CVT_95_Reg, 1, CVT_imm_95_3074, 0, CVT_regX0, 0, CVT_Done }, 925 // Convert__Reg1_0__imm_95_3202__regX0 926 { CVT_95_Reg, 1, CVT_imm_95_3202, 0, CVT_regX0, 0, CVT_Done }, 927 // Convert__Reg1_0__imm_95_3073__regX0 928 { CVT_95_Reg, 1, CVT_imm_95_3073, 0, CVT_regX0, 0, CVT_Done }, 929 // Convert__Reg1_0__imm_95_3201__regX0 930 { CVT_95_Reg, 1, CVT_imm_95_3201, 0, CVT_regX0, 0, CVT_Done }, 931 // Convert__regX0__regX1__imm_95_0 932 { CVT_regX0, 0, CVT_regX1, 0, CVT_imm_95_0, 0, CVT_Done }, 933 // Convert__Reg1_0__Reg1_1__imm_95_1 934 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done }, 935 // Convert__regX0__regX0 936 { CVT_regX0, 0, CVT_regX0, 0, CVT_Done }, 937 // Convert__Reg1_0__regX0 938 { CVT_95_Reg, 1, CVT_regX0, 0, CVT_Done }, 939 // Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2 940 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 941 // Convert__Reg1_0__Reg1_1__UImm51_2 942 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done }, 943 // Convert__Reg1_0__Reg1_1__regX0 944 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done }, 945}; 946 947void RISCVAsmParser:: 948convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 949 const OperandVector &Operands) { 950 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 951 const uint8_t *Converter = ConversionTable[Kind]; 952 unsigned OpIdx; 953 Inst.setOpcode(Opcode); 954 for (const uint8_t *p = Converter; *p; p+= 2) { 955 OpIdx = *(p + 1); 956 switch (*p) { 957 default: llvm_unreachable("invalid conversion entry!"); 958 case CVT_Reg: 959 static_cast<RISCVOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 960 break; 961 case CVT_Tied: { 962 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 963 std::begin(TiedAsmOperandTable)) && 964 "Tied operand not found"); 965 unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; 966 if (TiedResOpnd != (uint8_t) -1) 967 Inst.addOperand(Inst.getOperand(TiedResOpnd)); 968 break; 969 } 970 case CVT_95_Reg: 971 static_cast<RISCVOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 972 break; 973 case CVT_95_addImmOperands: 974 static_cast<RISCVOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1); 975 break; 976 case CVT_95_addRegOperands: 977 static_cast<RISCVOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 978 break; 979 case CVT_regX0: 980 Inst.addOperand(MCOperand::createReg(RISCV::X0)); 981 break; 982 case CVT_imm_95_0: 983 Inst.addOperand(MCOperand::createImm(0)); 984 break; 985 case CVT_95_addCSRSystemRegisterOperands: 986 static_cast<RISCVOperand&>(*Operands[OpIdx]).addCSRSystemRegisterOperands(Inst, 1); 987 break; 988 case CVT_imm_95_7: 989 Inst.addOperand(MCOperand::createImm(7)); 990 break; 991 case CVT_95_addFRMArgOperands: 992 static_cast<RISCVOperand&>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1); 993 break; 994 case CVT_imm_95_15: 995 Inst.addOperand(MCOperand::createImm(15)); 996 break; 997 case CVT_95_addFenceArgOperands: 998 static_cast<RISCVOperand&>(*Operands[OpIdx]).addFenceArgOperands(Inst, 1); 999 break; 1000 case CVT_imm_95_3: 1001 Inst.addOperand(MCOperand::createImm(3)); 1002 break; 1003 case CVT_imm_95_1: 1004 Inst.addOperand(MCOperand::createImm(1)); 1005 break; 1006 case CVT_imm_95_2: 1007 Inst.addOperand(MCOperand::createImm(2)); 1008 break; 1009 case CVT_regX1: 1010 Inst.addOperand(MCOperand::createReg(RISCV::X1)); 1011 break; 1012 case CVT_imm_95__MINUS_1: 1013 Inst.addOperand(MCOperand::createImm(-1)); 1014 break; 1015 case CVT_imm_95_3072: 1016 Inst.addOperand(MCOperand::createImm(3072)); 1017 break; 1018 case CVT_imm_95_3200: 1019 Inst.addOperand(MCOperand::createImm(3200)); 1020 break; 1021 case CVT_imm_95_3074: 1022 Inst.addOperand(MCOperand::createImm(3074)); 1023 break; 1024 case CVT_imm_95_3202: 1025 Inst.addOperand(MCOperand::createImm(3202)); 1026 break; 1027 case CVT_imm_95_3073: 1028 Inst.addOperand(MCOperand::createImm(3073)); 1029 break; 1030 case CVT_imm_95_3201: 1031 Inst.addOperand(MCOperand::createImm(3201)); 1032 break; 1033 } 1034 } 1035} 1036 1037void RISCVAsmParser:: 1038convertToMapAndConstraints(unsigned Kind, 1039 const OperandVector &Operands) { 1040 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 1041 unsigned NumMCOperands = 0; 1042 const uint8_t *Converter = ConversionTable[Kind]; 1043 for (const uint8_t *p = Converter; *p; p+= 2) { 1044 switch (*p) { 1045 default: llvm_unreachable("invalid conversion entry!"); 1046 case CVT_Reg: 1047 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1048 Operands[*(p + 1)]->setConstraint("r"); 1049 ++NumMCOperands; 1050 break; 1051 case CVT_Tied: 1052 ++NumMCOperands; 1053 break; 1054 case CVT_95_Reg: 1055 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1056 Operands[*(p + 1)]->setConstraint("r"); 1057 NumMCOperands += 1; 1058 break; 1059 case CVT_95_addImmOperands: 1060 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1061 Operands[*(p + 1)]->setConstraint("m"); 1062 NumMCOperands += 1; 1063 break; 1064 case CVT_95_addRegOperands: 1065 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1066 Operands[*(p + 1)]->setConstraint("m"); 1067 NumMCOperands += 1; 1068 break; 1069 case CVT_regX0: 1070 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1071 Operands[*(p + 1)]->setConstraint("m"); 1072 ++NumMCOperands; 1073 break; 1074 case CVT_imm_95_0: 1075 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1076 Operands[*(p + 1)]->setConstraint(""); 1077 ++NumMCOperands; 1078 break; 1079 case CVT_95_addCSRSystemRegisterOperands: 1080 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1081 Operands[*(p + 1)]->setConstraint("m"); 1082 NumMCOperands += 1; 1083 break; 1084 case CVT_imm_95_7: 1085 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1086 Operands[*(p + 1)]->setConstraint(""); 1087 ++NumMCOperands; 1088 break; 1089 case CVT_95_addFRMArgOperands: 1090 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1091 Operands[*(p + 1)]->setConstraint("m"); 1092 NumMCOperands += 1; 1093 break; 1094 case CVT_imm_95_15: 1095 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1096 Operands[*(p + 1)]->setConstraint(""); 1097 ++NumMCOperands; 1098 break; 1099 case CVT_95_addFenceArgOperands: 1100 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1101 Operands[*(p + 1)]->setConstraint("m"); 1102 NumMCOperands += 1; 1103 break; 1104 case CVT_imm_95_3: 1105 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1106 Operands[*(p + 1)]->setConstraint(""); 1107 ++NumMCOperands; 1108 break; 1109 case CVT_imm_95_1: 1110 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1111 Operands[*(p + 1)]->setConstraint(""); 1112 ++NumMCOperands; 1113 break; 1114 case CVT_imm_95_2: 1115 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1116 Operands[*(p + 1)]->setConstraint(""); 1117 ++NumMCOperands; 1118 break; 1119 case CVT_regX1: 1120 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1121 Operands[*(p + 1)]->setConstraint("m"); 1122 ++NumMCOperands; 1123 break; 1124 case CVT_imm_95__MINUS_1: 1125 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1126 Operands[*(p + 1)]->setConstraint(""); 1127 ++NumMCOperands; 1128 break; 1129 case CVT_imm_95_3072: 1130 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1131 Operands[*(p + 1)]->setConstraint(""); 1132 ++NumMCOperands; 1133 break; 1134 case CVT_imm_95_3200: 1135 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1136 Operands[*(p + 1)]->setConstraint(""); 1137 ++NumMCOperands; 1138 break; 1139 case CVT_imm_95_3074: 1140 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1141 Operands[*(p + 1)]->setConstraint(""); 1142 ++NumMCOperands; 1143 break; 1144 case CVT_imm_95_3202: 1145 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1146 Operands[*(p + 1)]->setConstraint(""); 1147 ++NumMCOperands; 1148 break; 1149 case CVT_imm_95_3073: 1150 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1151 Operands[*(p + 1)]->setConstraint(""); 1152 ++NumMCOperands; 1153 break; 1154 case CVT_imm_95_3201: 1155 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1156 Operands[*(p + 1)]->setConstraint(""); 1157 ++NumMCOperands; 1158 break; 1159 } 1160 } 1161} 1162 1163namespace { 1164 1165/// MatchClassKind - The kinds of classes which participate in 1166/// instruction matching. 1167enum MatchClassKind { 1168 InvalidMatchClass = 0, 1169 OptionalMatchClass = 1, 1170 MCK__40_, // '(' 1171 MCK__41_, // ')' 1172 MCK_LAST_TOKEN = MCK__41_, 1173 MCK_GPRX0, // register class 'GPRX0' 1174 MCK_SP, // register class 'SP' 1175 MCK_Reg7, // derived register class 1176 MCK_FPR32C, // register class 'FPR32C' 1177 MCK_FPR64C, // register class 'FPR64C' 1178 MCK_GPRC, // register class 'GPRC' 1179 MCK_GPRTC, // register class 'GPRTC' 1180 MCK_GPRNoX0X2, // register class 'GPRNoX0X2' 1181 MCK_GPRNoX0, // register class 'GPRNoX0' 1182 MCK_FPR32, // register class 'FPR32' 1183 MCK_FPR64, // register class 'FPR64' 1184 MCK_GPR, // register class 'GPR' 1185 MCK_LAST_REGISTER = MCK_GPR, 1186 MCK_AtomicMemOpOperand, // user defined class 'AtomicMemOpOperand' 1187 MCK_BareSymbol, // user defined class 'BareSymbol' 1188 MCK_CLUIImm, // user defined class 'CLUIImmAsmOperand' 1189 MCK_CSRSystemRegister, // user defined class 'CSRSystemRegister' 1190 MCK_CallSymbol, // user defined class 'CallSymbol' 1191 MCK_FRMArg, // user defined class 'FRMArg' 1192 MCK_FenceArg, // user defined class 'FenceArg' 1193 MCK_Imm, // user defined class 'ImmAsmOperand' 1194 MCK_ImmZero, // user defined class 'ImmZeroAsmOperand' 1195 MCK_SImm21Lsb0JAL, // user defined class 'Simm21Lsb0JALAsmOperand' 1196 MCK_TPRelAddSymbol, // user defined class 'TPRelAddSymbol' 1197 MCK_UImmLog2XLen, // user defined class 'UImmLog2XLenAsmOperand' 1198 MCK_UImmLog2XLenNonZero, // user defined class 'UImmLog2XLenNonZeroAsmOperand' 1199 MCK_UImm5, // user defined class 'anonymous_2450' 1200 MCK_SImm12, // user defined class 'anonymous_2451' 1201 MCK_SImm13Lsb0, // user defined class 'anonymous_2452' 1202 MCK_UImm20LUI, // user defined class 'anonymous_2453' 1203 MCK_UImm20AUIPC, // user defined class 'anonymous_2454' 1204 MCK_ImmXLenLI, // user defined class 'anonymous_2455' 1205 MCK_SImm6, // user defined class 'anonymous_3109' 1206 MCK_SImm6NonZero, // user defined class 'anonymous_3110' 1207 MCK_UImm7Lsb00, // user defined class 'anonymous_3111' 1208 MCK_UImm8Lsb00, // user defined class 'anonymous_3112' 1209 MCK_UImm8Lsb000, // user defined class 'anonymous_3113' 1210 MCK_SImm9Lsb0, // user defined class 'anonymous_3114' 1211 MCK_UImm9Lsb000, // user defined class 'anonymous_3115' 1212 MCK_UImm10Lsb00NonZero, // user defined class 'anonymous_3116' 1213 MCK_SImm10Lsb0000NonZero, // user defined class 'anonymous_3117' 1214 MCK_SImm12Lsb0, // user defined class 'anonymous_3118' 1215 NumMatchClassKinds 1216}; 1217 1218} // end anonymous namespace 1219 1220static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { 1221 return MCTargetAsmParser::Match_InvalidOperand; 1222} 1223 1224static MatchClassKind matchTokenString(StringRef Name) { 1225 switch (Name.size()) { 1226 default: break; 1227 case 1: // 2 strings to match. 1228 switch (Name[0]) { 1229 default: break; 1230 case '(': // 1 string to match. 1231 return MCK__40_; // "(" 1232 case ')': // 1 string to match. 1233 return MCK__41_; // ")" 1234 } 1235 break; 1236 } 1237 return InvalidMatchClass; 1238} 1239 1240/// isSubclass - Compute whether \p A is a subclass of \p B. 1241static bool isSubclass(MatchClassKind A, MatchClassKind B) { 1242 if (A == B) 1243 return true; 1244 1245 switch (A) { 1246 default: 1247 return false; 1248 1249 case MCK_GPRX0: 1250 return B == MCK_GPR; 1251 1252 case MCK_SP: 1253 switch (B) { 1254 default: return false; 1255 case MCK_GPRNoX0: return true; 1256 case MCK_GPR: return true; 1257 } 1258 1259 case MCK_Reg7: 1260 switch (B) { 1261 default: return false; 1262 case MCK_GPRC: return true; 1263 case MCK_GPRTC: return true; 1264 case MCK_GPRNoX0X2: return true; 1265 case MCK_GPRNoX0: return true; 1266 case MCK_GPR: return true; 1267 } 1268 1269 case MCK_FPR32C: 1270 return B == MCK_FPR32; 1271 1272 case MCK_FPR64C: 1273 return B == MCK_FPR64; 1274 1275 case MCK_GPRC: 1276 switch (B) { 1277 default: return false; 1278 case MCK_GPRNoX0X2: return true; 1279 case MCK_GPRNoX0: return true; 1280 case MCK_GPR: return true; 1281 } 1282 1283 case MCK_GPRTC: 1284 switch (B) { 1285 default: return false; 1286 case MCK_GPRNoX0X2: return true; 1287 case MCK_GPRNoX0: return true; 1288 case MCK_GPR: return true; 1289 } 1290 1291 case MCK_GPRNoX0X2: 1292 switch (B) { 1293 default: return false; 1294 case MCK_GPRNoX0: return true; 1295 case MCK_GPR: return true; 1296 } 1297 1298 case MCK_GPRNoX0: 1299 return B == MCK_GPR; 1300 } 1301} 1302 1303static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { 1304 RISCVOperand &Operand = (RISCVOperand&)GOp; 1305 if (Kind == InvalidMatchClass) 1306 return MCTargetAsmParser::Match_InvalidOperand; 1307 1308 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN) 1309 return isSubclass(matchTokenString(Operand.getToken()), Kind) ? 1310 MCTargetAsmParser::Match_Success : 1311 MCTargetAsmParser::Match_InvalidOperand; 1312 1313 switch (Kind) { 1314 default: break; 1315 // 'AtomicMemOpOperand' class 1316 case MCK_AtomicMemOpOperand: { 1317 DiagnosticPredicate DP(Operand.isGPR()); 1318 if (DP.isMatch()) 1319 return MCTargetAsmParser::Match_Success; 1320 break; 1321 } 1322 // 'BareSymbol' class 1323 case MCK_BareSymbol: { 1324 DiagnosticPredicate DP(Operand.isBareSymbol()); 1325 if (DP.isMatch()) 1326 return MCTargetAsmParser::Match_Success; 1327 if (DP.isNearMatch()) 1328 return RISCVAsmParser::Match_InvalidBareSymbol; 1329 break; 1330 } 1331 // 'CLUIImm' class 1332 case MCK_CLUIImm: { 1333 DiagnosticPredicate DP(Operand.isCLUIImm()); 1334 if (DP.isMatch()) 1335 return MCTargetAsmParser::Match_Success; 1336 if (DP.isNearMatch()) 1337 return RISCVAsmParser::Match_InvalidCLUIImm; 1338 break; 1339 } 1340 // 'CSRSystemRegister' class 1341 case MCK_CSRSystemRegister: { 1342 DiagnosticPredicate DP(Operand.isCSRSystemRegister()); 1343 if (DP.isMatch()) 1344 return MCTargetAsmParser::Match_Success; 1345 if (DP.isNearMatch()) 1346 return RISCVAsmParser::Match_InvalidCSRSystemRegister; 1347 break; 1348 } 1349 // 'CallSymbol' class 1350 case MCK_CallSymbol: { 1351 DiagnosticPredicate DP(Operand.isCallSymbol()); 1352 if (DP.isMatch()) 1353 return MCTargetAsmParser::Match_Success; 1354 if (DP.isNearMatch()) 1355 return RISCVAsmParser::Match_InvalidCallSymbol; 1356 break; 1357 } 1358 // 'FRMArg' class 1359 case MCK_FRMArg: { 1360 DiagnosticPredicate DP(Operand.isFRMArg()); 1361 if (DP.isMatch()) 1362 return MCTargetAsmParser::Match_Success; 1363 if (DP.isNearMatch()) 1364 return RISCVAsmParser::Match_InvalidFRMArg; 1365 break; 1366 } 1367 // 'FenceArg' class 1368 case MCK_FenceArg: { 1369 DiagnosticPredicate DP(Operand.isFenceArg()); 1370 if (DP.isMatch()) 1371 return MCTargetAsmParser::Match_Success; 1372 if (DP.isNearMatch()) 1373 return RISCVAsmParser::Match_InvalidFenceArg; 1374 break; 1375 } 1376 // 'Imm' class 1377 case MCK_Imm: { 1378 DiagnosticPredicate DP(Operand.isImm()); 1379 if (DP.isMatch()) 1380 return MCTargetAsmParser::Match_Success; 1381 break; 1382 } 1383 // 'ImmZero' class 1384 case MCK_ImmZero: { 1385 DiagnosticPredicate DP(Operand.isImmZero()); 1386 if (DP.isMatch()) 1387 return MCTargetAsmParser::Match_Success; 1388 if (DP.isNearMatch()) 1389 return RISCVAsmParser::Match_InvalidImmZero; 1390 break; 1391 } 1392 // 'SImm21Lsb0JAL' class 1393 case MCK_SImm21Lsb0JAL: { 1394 DiagnosticPredicate DP(Operand.isSImm21Lsb0JAL()); 1395 if (DP.isMatch()) 1396 return MCTargetAsmParser::Match_Success; 1397 if (DP.isNearMatch()) 1398 return RISCVAsmParser::Match_InvalidSImm21Lsb0JAL; 1399 break; 1400 } 1401 // 'TPRelAddSymbol' class 1402 case MCK_TPRelAddSymbol: { 1403 DiagnosticPredicate DP(Operand.isTPRelAddSymbol()); 1404 if (DP.isMatch()) 1405 return MCTargetAsmParser::Match_Success; 1406 if (DP.isNearMatch()) 1407 return RISCVAsmParser::Match_InvalidTPRelAddSymbol; 1408 break; 1409 } 1410 // 'UImmLog2XLen' class 1411 case MCK_UImmLog2XLen: { 1412 DiagnosticPredicate DP(Operand.isUImmLog2XLen()); 1413 if (DP.isMatch()) 1414 return MCTargetAsmParser::Match_Success; 1415 if (DP.isNearMatch()) 1416 return RISCVAsmParser::Match_InvalidUImmLog2XLen; 1417 break; 1418 } 1419 // 'UImmLog2XLenNonZero' class 1420 case MCK_UImmLog2XLenNonZero: { 1421 DiagnosticPredicate DP(Operand.isUImmLog2XLenNonZero()); 1422 if (DP.isMatch()) 1423 return MCTargetAsmParser::Match_Success; 1424 if (DP.isNearMatch()) 1425 return RISCVAsmParser::Match_InvalidUImmLog2XLenNonZero; 1426 break; 1427 } 1428 // 'UImm5' class 1429 case MCK_UImm5: { 1430 DiagnosticPredicate DP(Operand.isUImm5()); 1431 if (DP.isMatch()) 1432 return MCTargetAsmParser::Match_Success; 1433 if (DP.isNearMatch()) 1434 return RISCVAsmParser::Match_InvalidUImm5; 1435 break; 1436 } 1437 // 'SImm12' class 1438 case MCK_SImm12: { 1439 DiagnosticPredicate DP(Operand.isSImm12()); 1440 if (DP.isMatch()) 1441 return MCTargetAsmParser::Match_Success; 1442 if (DP.isNearMatch()) 1443 return RISCVAsmParser::Match_InvalidSImm12; 1444 break; 1445 } 1446 // 'SImm13Lsb0' class 1447 case MCK_SImm13Lsb0: { 1448 DiagnosticPredicate DP(Operand.isSImm13Lsb0()); 1449 if (DP.isMatch()) 1450 return MCTargetAsmParser::Match_Success; 1451 if (DP.isNearMatch()) 1452 return RISCVAsmParser::Match_InvalidSImm13Lsb0; 1453 break; 1454 } 1455 // 'UImm20LUI' class 1456 case MCK_UImm20LUI: { 1457 DiagnosticPredicate DP(Operand.isUImm20LUI()); 1458 if (DP.isMatch()) 1459 return MCTargetAsmParser::Match_Success; 1460 if (DP.isNearMatch()) 1461 return RISCVAsmParser::Match_InvalidUImm20LUI; 1462 break; 1463 } 1464 // 'UImm20AUIPC' class 1465 case MCK_UImm20AUIPC: { 1466 DiagnosticPredicate DP(Operand.isUImm20AUIPC()); 1467 if (DP.isMatch()) 1468 return MCTargetAsmParser::Match_Success; 1469 if (DP.isNearMatch()) 1470 return RISCVAsmParser::Match_InvalidUImm20AUIPC; 1471 break; 1472 } 1473 // 'ImmXLenLI' class 1474 case MCK_ImmXLenLI: { 1475 DiagnosticPredicate DP(Operand.isImmXLenLI()); 1476 if (DP.isMatch()) 1477 return MCTargetAsmParser::Match_Success; 1478 if (DP.isNearMatch()) 1479 return RISCVAsmParser::Match_InvalidImmXLenLI; 1480 break; 1481 } 1482 // 'SImm6' class 1483 case MCK_SImm6: { 1484 DiagnosticPredicate DP(Operand.isSImm6()); 1485 if (DP.isMatch()) 1486 return MCTargetAsmParser::Match_Success; 1487 if (DP.isNearMatch()) 1488 return RISCVAsmParser::Match_InvalidSImm6; 1489 break; 1490 } 1491 // 'SImm6NonZero' class 1492 case MCK_SImm6NonZero: { 1493 DiagnosticPredicate DP(Operand.isSImm6NonZero()); 1494 if (DP.isMatch()) 1495 return MCTargetAsmParser::Match_Success; 1496 if (DP.isNearMatch()) 1497 return RISCVAsmParser::Match_InvalidSImm6NonZero; 1498 break; 1499 } 1500 // 'UImm7Lsb00' class 1501 case MCK_UImm7Lsb00: { 1502 DiagnosticPredicate DP(Operand.isUImm7Lsb00()); 1503 if (DP.isMatch()) 1504 return MCTargetAsmParser::Match_Success; 1505 if (DP.isNearMatch()) 1506 return RISCVAsmParser::Match_InvalidUImm7Lsb00; 1507 break; 1508 } 1509 // 'UImm8Lsb00' class 1510 case MCK_UImm8Lsb00: { 1511 DiagnosticPredicate DP(Operand.isUImm8Lsb00()); 1512 if (DP.isMatch()) 1513 return MCTargetAsmParser::Match_Success; 1514 if (DP.isNearMatch()) 1515 return RISCVAsmParser::Match_InvalidUImm8Lsb00; 1516 break; 1517 } 1518 // 'UImm8Lsb000' class 1519 case MCK_UImm8Lsb000: { 1520 DiagnosticPredicate DP(Operand.isUImm8Lsb000()); 1521 if (DP.isMatch()) 1522 return MCTargetAsmParser::Match_Success; 1523 if (DP.isNearMatch()) 1524 return RISCVAsmParser::Match_InvalidUImm8Lsb000; 1525 break; 1526 } 1527 // 'SImm9Lsb0' class 1528 case MCK_SImm9Lsb0: { 1529 DiagnosticPredicate DP(Operand.isSImm9Lsb0()); 1530 if (DP.isMatch()) 1531 return MCTargetAsmParser::Match_Success; 1532 if (DP.isNearMatch()) 1533 return RISCVAsmParser::Match_InvalidSImm9Lsb0; 1534 break; 1535 } 1536 // 'UImm9Lsb000' class 1537 case MCK_UImm9Lsb000: { 1538 DiagnosticPredicate DP(Operand.isUImm9Lsb000()); 1539 if (DP.isMatch()) 1540 return MCTargetAsmParser::Match_Success; 1541 if (DP.isNearMatch()) 1542 return RISCVAsmParser::Match_InvalidUImm9Lsb000; 1543 break; 1544 } 1545 // 'UImm10Lsb00NonZero' class 1546 case MCK_UImm10Lsb00NonZero: { 1547 DiagnosticPredicate DP(Operand.isUImm10Lsb00NonZero()); 1548 if (DP.isMatch()) 1549 return MCTargetAsmParser::Match_Success; 1550 if (DP.isNearMatch()) 1551 return RISCVAsmParser::Match_InvalidUImm10Lsb00NonZero; 1552 break; 1553 } 1554 // 'SImm10Lsb0000NonZero' class 1555 case MCK_SImm10Lsb0000NonZero: { 1556 DiagnosticPredicate DP(Operand.isSImm10Lsb0000NonZero()); 1557 if (DP.isMatch()) 1558 return MCTargetAsmParser::Match_Success; 1559 if (DP.isNearMatch()) 1560 return RISCVAsmParser::Match_InvalidSImm10Lsb0000NonZero; 1561 break; 1562 } 1563 // 'SImm12Lsb0' class 1564 case MCK_SImm12Lsb0: { 1565 DiagnosticPredicate DP(Operand.isSImm12Lsb0()); 1566 if (DP.isMatch()) 1567 return MCTargetAsmParser::Match_Success; 1568 if (DP.isNearMatch()) 1569 return RISCVAsmParser::Match_InvalidSImm12Lsb0; 1570 break; 1571 } 1572 } // end switch (Kind) 1573 1574 if (Operand.isReg()) { 1575 MatchClassKind OpKind; 1576 switch (Operand.getReg()) { 1577 default: OpKind = InvalidMatchClass; break; 1578 case RISCV::X0: OpKind = MCK_GPRX0; break; 1579 case RISCV::X1: OpKind = MCK_GPRNoX0X2; break; 1580 case RISCV::X2: OpKind = MCK_SP; break; 1581 case RISCV::X3: OpKind = MCK_GPRNoX0X2; break; 1582 case RISCV::X4: OpKind = MCK_GPRNoX0X2; break; 1583 case RISCV::X5: OpKind = MCK_GPRTC; break; 1584 case RISCV::X6: OpKind = MCK_GPRTC; break; 1585 case RISCV::X7: OpKind = MCK_GPRTC; break; 1586 case RISCV::X8: OpKind = MCK_GPRC; break; 1587 case RISCV::X9: OpKind = MCK_GPRC; break; 1588 case RISCV::X10: OpKind = MCK_Reg7; break; 1589 case RISCV::X11: OpKind = MCK_Reg7; break; 1590 case RISCV::X12: OpKind = MCK_Reg7; break; 1591 case RISCV::X13: OpKind = MCK_Reg7; break; 1592 case RISCV::X14: OpKind = MCK_Reg7; break; 1593 case RISCV::X15: OpKind = MCK_Reg7; break; 1594 case RISCV::X16: OpKind = MCK_GPRTC; break; 1595 case RISCV::X17: OpKind = MCK_GPRTC; break; 1596 case RISCV::X18: OpKind = MCK_GPRNoX0X2; break; 1597 case RISCV::X19: OpKind = MCK_GPRNoX0X2; break; 1598 case RISCV::X20: OpKind = MCK_GPRNoX0X2; break; 1599 case RISCV::X21: OpKind = MCK_GPRNoX0X2; break; 1600 case RISCV::X22: OpKind = MCK_GPRNoX0X2; break; 1601 case RISCV::X23: OpKind = MCK_GPRNoX0X2; break; 1602 case RISCV::X24: OpKind = MCK_GPRNoX0X2; break; 1603 case RISCV::X25: OpKind = MCK_GPRNoX0X2; break; 1604 case RISCV::X26: OpKind = MCK_GPRNoX0X2; break; 1605 case RISCV::X27: OpKind = MCK_GPRNoX0X2; break; 1606 case RISCV::X28: OpKind = MCK_GPRTC; break; 1607 case RISCV::X29: OpKind = MCK_GPRTC; break; 1608 case RISCV::X30: OpKind = MCK_GPRTC; break; 1609 case RISCV::X31: OpKind = MCK_GPRTC; break; 1610 case RISCV::F0_F: OpKind = MCK_FPR32; break; 1611 case RISCV::F1_F: OpKind = MCK_FPR32; break; 1612 case RISCV::F2_F: OpKind = MCK_FPR32; break; 1613 case RISCV::F3_F: OpKind = MCK_FPR32; break; 1614 case RISCV::F4_F: OpKind = MCK_FPR32; break; 1615 case RISCV::F5_F: OpKind = MCK_FPR32; break; 1616 case RISCV::F6_F: OpKind = MCK_FPR32; break; 1617 case RISCV::F7_F: OpKind = MCK_FPR32; break; 1618 case RISCV::F8_F: OpKind = MCK_FPR32C; break; 1619 case RISCV::F9_F: OpKind = MCK_FPR32C; break; 1620 case RISCV::F10_F: OpKind = MCK_FPR32C; break; 1621 case RISCV::F11_F: OpKind = MCK_FPR32C; break; 1622 case RISCV::F12_F: OpKind = MCK_FPR32C; break; 1623 case RISCV::F13_F: OpKind = MCK_FPR32C; break; 1624 case RISCV::F14_F: OpKind = MCK_FPR32C; break; 1625 case RISCV::F15_F: OpKind = MCK_FPR32C; break; 1626 case RISCV::F16_F: OpKind = MCK_FPR32; break; 1627 case RISCV::F17_F: OpKind = MCK_FPR32; break; 1628 case RISCV::F18_F: OpKind = MCK_FPR32; break; 1629 case RISCV::F19_F: OpKind = MCK_FPR32; break; 1630 case RISCV::F20_F: OpKind = MCK_FPR32; break; 1631 case RISCV::F21_F: OpKind = MCK_FPR32; break; 1632 case RISCV::F22_F: OpKind = MCK_FPR32; break; 1633 case RISCV::F23_F: OpKind = MCK_FPR32; break; 1634 case RISCV::F24_F: OpKind = MCK_FPR32; break; 1635 case RISCV::F25_F: OpKind = MCK_FPR32; break; 1636 case RISCV::F26_F: OpKind = MCK_FPR32; break; 1637 case RISCV::F27_F: OpKind = MCK_FPR32; break; 1638 case RISCV::F28_F: OpKind = MCK_FPR32; break; 1639 case RISCV::F29_F: OpKind = MCK_FPR32; break; 1640 case RISCV::F30_F: OpKind = MCK_FPR32; break; 1641 case RISCV::F31_F: OpKind = MCK_FPR32; break; 1642 case RISCV::F0_D: OpKind = MCK_FPR64; break; 1643 case RISCV::F1_D: OpKind = MCK_FPR64; break; 1644 case RISCV::F2_D: OpKind = MCK_FPR64; break; 1645 case RISCV::F3_D: OpKind = MCK_FPR64; break; 1646 case RISCV::F4_D: OpKind = MCK_FPR64; break; 1647 case RISCV::F5_D: OpKind = MCK_FPR64; break; 1648 case RISCV::F6_D: OpKind = MCK_FPR64; break; 1649 case RISCV::F7_D: OpKind = MCK_FPR64; break; 1650 case RISCV::F8_D: OpKind = MCK_FPR64C; break; 1651 case RISCV::F9_D: OpKind = MCK_FPR64C; break; 1652 case RISCV::F10_D: OpKind = MCK_FPR64C; break; 1653 case RISCV::F11_D: OpKind = MCK_FPR64C; break; 1654 case RISCV::F12_D: OpKind = MCK_FPR64C; break; 1655 case RISCV::F13_D: OpKind = MCK_FPR64C; break; 1656 case RISCV::F14_D: OpKind = MCK_FPR64C; break; 1657 case RISCV::F15_D: OpKind = MCK_FPR64C; break; 1658 case RISCV::F16_D: OpKind = MCK_FPR64; break; 1659 case RISCV::F17_D: OpKind = MCK_FPR64; break; 1660 case RISCV::F18_D: OpKind = MCK_FPR64; break; 1661 case RISCV::F19_D: OpKind = MCK_FPR64; break; 1662 case RISCV::F20_D: OpKind = MCK_FPR64; break; 1663 case RISCV::F21_D: OpKind = MCK_FPR64; break; 1664 case RISCV::F22_D: OpKind = MCK_FPR64; break; 1665 case RISCV::F23_D: OpKind = MCK_FPR64; break; 1666 case RISCV::F24_D: OpKind = MCK_FPR64; break; 1667 case RISCV::F25_D: OpKind = MCK_FPR64; break; 1668 case RISCV::F26_D: OpKind = MCK_FPR64; break; 1669 case RISCV::F27_D: OpKind = MCK_FPR64; break; 1670 case RISCV::F28_D: OpKind = MCK_FPR64; break; 1671 case RISCV::F29_D: OpKind = MCK_FPR64; break; 1672 case RISCV::F30_D: OpKind = MCK_FPR64; break; 1673 case RISCV::F31_D: OpKind = MCK_FPR64; break; 1674 } 1675 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success : 1676 getDiagKindFromRegisterClass(Kind); 1677 } 1678 1679 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER) 1680 return getDiagKindFromRegisterClass(Kind); 1681 1682 return MCTargetAsmParser::Match_InvalidOperand; 1683} 1684 1685#ifndef NDEBUG 1686const char *getMatchClassName(MatchClassKind Kind) { 1687 switch (Kind) { 1688 case InvalidMatchClass: return "InvalidMatchClass"; 1689 case OptionalMatchClass: return "OptionalMatchClass"; 1690 case MCK__40_: return "MCK__40_"; 1691 case MCK__41_: return "MCK__41_"; 1692 case MCK_GPRX0: return "MCK_GPRX0"; 1693 case MCK_SP: return "MCK_SP"; 1694 case MCK_Reg7: return "MCK_Reg7"; 1695 case MCK_FPR32C: return "MCK_FPR32C"; 1696 case MCK_FPR64C: return "MCK_FPR64C"; 1697 case MCK_GPRC: return "MCK_GPRC"; 1698 case MCK_GPRTC: return "MCK_GPRTC"; 1699 case MCK_GPRNoX0X2: return "MCK_GPRNoX0X2"; 1700 case MCK_GPRNoX0: return "MCK_GPRNoX0"; 1701 case MCK_FPR32: return "MCK_FPR32"; 1702 case MCK_FPR64: return "MCK_FPR64"; 1703 case MCK_GPR: return "MCK_GPR"; 1704 case MCK_AtomicMemOpOperand: return "MCK_AtomicMemOpOperand"; 1705 case MCK_BareSymbol: return "MCK_BareSymbol"; 1706 case MCK_CLUIImm: return "MCK_CLUIImm"; 1707 case MCK_CSRSystemRegister: return "MCK_CSRSystemRegister"; 1708 case MCK_CallSymbol: return "MCK_CallSymbol"; 1709 case MCK_FRMArg: return "MCK_FRMArg"; 1710 case MCK_FenceArg: return "MCK_FenceArg"; 1711 case MCK_Imm: return "MCK_Imm"; 1712 case MCK_ImmZero: return "MCK_ImmZero"; 1713 case MCK_SImm21Lsb0JAL: return "MCK_SImm21Lsb0JAL"; 1714 case MCK_TPRelAddSymbol: return "MCK_TPRelAddSymbol"; 1715 case MCK_UImmLog2XLen: return "MCK_UImmLog2XLen"; 1716 case MCK_UImmLog2XLenNonZero: return "MCK_UImmLog2XLenNonZero"; 1717 case MCK_UImm5: return "MCK_UImm5"; 1718 case MCK_SImm12: return "MCK_SImm12"; 1719 case MCK_SImm13Lsb0: return "MCK_SImm13Lsb0"; 1720 case MCK_UImm20LUI: return "MCK_UImm20LUI"; 1721 case MCK_UImm20AUIPC: return "MCK_UImm20AUIPC"; 1722 case MCK_ImmXLenLI: return "MCK_ImmXLenLI"; 1723 case MCK_SImm6: return "MCK_SImm6"; 1724 case MCK_SImm6NonZero: return "MCK_SImm6NonZero"; 1725 case MCK_UImm7Lsb00: return "MCK_UImm7Lsb00"; 1726 case MCK_UImm8Lsb00: return "MCK_UImm8Lsb00"; 1727 case MCK_UImm8Lsb000: return "MCK_UImm8Lsb000"; 1728 case MCK_SImm9Lsb0: return "MCK_SImm9Lsb0"; 1729 case MCK_UImm9Lsb000: return "MCK_UImm9Lsb000"; 1730 case MCK_UImm10Lsb00NonZero: return "MCK_UImm10Lsb00NonZero"; 1731 case MCK_SImm10Lsb0000NonZero: return "MCK_SImm10Lsb0000NonZero"; 1732 case MCK_SImm12Lsb0: return "MCK_SImm12Lsb0"; 1733 case NumMatchClassKinds: return "NumMatchClassKinds"; 1734 } 1735 llvm_unreachable("unhandled MatchClassKind!"); 1736} 1737 1738#endif // NDEBUG 1739FeatureBitset RISCVAsmParser:: 1740ComputeAvailableFeatures(const FeatureBitset& FB) const { 1741 FeatureBitset Features; 1742 if ((FB[RISCV::FeatureStdExtM])) 1743 Features.set(Feature_HasStdExtMBit); 1744 if ((FB[RISCV::FeatureStdExtA])) 1745 Features.set(Feature_HasStdExtABit); 1746 if ((FB[RISCV::FeatureStdExtF])) 1747 Features.set(Feature_HasStdExtFBit); 1748 if ((FB[RISCV::FeatureStdExtD])) 1749 Features.set(Feature_HasStdExtDBit); 1750 if ((FB[RISCV::FeatureStdExtC])) 1751 Features.set(Feature_HasStdExtCBit); 1752 if ((FB[RISCV::FeatureRVCHints])) 1753 Features.set(Feature_HasRVCHintsBit); 1754 if ((FB[RISCV::Feature64Bit])) 1755 Features.set(Feature_IsRV64Bit); 1756 if ((!FB[RISCV::Feature64Bit])) 1757 Features.set(Feature_IsRV32Bit); 1758 if ((FB[RISCV::FeatureRV32E])) 1759 Features.set(Feature_IsRV32EBit); 1760 return Features; 1761} 1762 1763static bool checkAsmTiedOperandConstraints(const RISCVAsmParser&AsmParser, 1764 unsigned Kind, 1765 const OperandVector &Operands, 1766 uint64_t &ErrorInfo) { 1767 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 1768 const uint8_t *Converter = ConversionTable[Kind]; 1769 for (const uint8_t *p = Converter; *p; p+= 2) { 1770 switch (*p) { 1771 case CVT_Tied: { 1772 unsigned OpIdx = *(p+1); 1773 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 1774 std::begin(TiedAsmOperandTable)) && 1775 "Tied operand not found"); 1776 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1]; 1777 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2]; 1778 if (OpndNum1 != OpndNum2) { 1779 auto &SrcOp1 = Operands[OpndNum1]; 1780 auto &SrcOp2 = Operands[OpndNum2]; 1781 if (SrcOp1->isReg() && SrcOp2->isReg()) { 1782 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) { 1783 ErrorInfo = OpndNum2; 1784 return false; 1785 } 1786 } 1787 } 1788 break; 1789 } 1790 default: 1791 break; 1792 } 1793 } 1794 return true; 1795} 1796 1797static const char *const MnemonicTable = 1798 "\003add\004addi\005addiw\004addw\010amoadd.d\013amoadd.d.aq\015amoadd.d" 1799 ".aqrl\013amoadd.d.rl\010amoadd.w\013amoadd.w.aq\015amoadd.w.aqrl\013amo" 1800 "add.w.rl\010amoand.d\013amoand.d.aq\015amoand.d.aqrl\013amoand.d.rl\010" 1801 "amoand.w\013amoand.w.aq\015amoand.w.aqrl\013amoand.w.rl\010amomax.d\013" 1802 "amomax.d.aq\015amomax.d.aqrl\013amomax.d.rl\010amomax.w\013amomax.w.aq\015" 1803 "amomax.w.aqrl\013amomax.w.rl\tamomaxu.d\014amomaxu.d.aq\016amomaxu.d.aq" 1804 "rl\014amomaxu.d.rl\tamomaxu.w\014amomaxu.w.aq\016amomaxu.w.aqrl\014amom" 1805 "axu.w.rl\010amomin.d\013amomin.d.aq\015amomin.d.aqrl\013amomin.d.rl\010" 1806 "amomin.w\013amomin.w.aq\015amomin.w.aqrl\013amomin.w.rl\tamominu.d\014a" 1807 "mominu.d.aq\016amominu.d.aqrl\014amominu.d.rl\tamominu.w\014amominu.w.a" 1808 "q\016amominu.w.aqrl\014amominu.w.rl\007amoor.d\namoor.d.aq\014amoor.d.a" 1809 "qrl\namoor.d.rl\007amoor.w\namoor.w.aq\014amoor.w.aqrl\namoor.w.rl\tamo" 1810 "swap.d\014amoswap.d.aq\016amoswap.d.aqrl\014amoswap.d.rl\tamoswap.w\014" 1811 "amoswap.w.aq\016amoswap.w.aqrl\014amoswap.w.rl\010amoxor.d\013amoxor.d." 1812 "aq\015amoxor.d.aqrl\013amoxor.d.rl\010amoxor.w\013amoxor.w.aq\015amoxor" 1813 ".w.aqrl\013amoxor.w.rl\003and\004andi\005auipc\003beq\004beqz\003bge\004" 1814 "bgeu\004bgez\003bgt\004bgtu\004bgtz\003ble\004bleu\004blez\003blt\004bl" 1815 "tu\004bltz\003bne\004bnez\005c.add\006c.addi\nc.addi16sp\nc.addi4spn\007" 1816 "c.addiw\006c.addw\005c.and\006c.andi\006c.beqz\006c.bnez\010c.ebreak\005" 1817 "c.fld\007c.fldsp\005c.flw\007c.flwsp\005c.fsd\007c.fsdsp\005c.fsw\007c." 1818 "fswsp\003c.j\005c.jal\006c.jalr\004c.jr\004c.ld\006c.ldsp\004c.li\005c." 1819 "lui\004c.lw\006c.lwsp\004c.mv\005c.nop\004c.or\004c.sd\006c.sdsp\006c.s" 1820 "lli\010c.slli64\006c.srai\010c.srai64\006c.srli\010c.srli64\005c.sub\006" 1821 "c.subw\004c.sw\006c.swsp\007c.unimp\005c.xor\004call\004csrc\005csrci\004" 1822 "csrr\005csrrc\006csrrci\005csrrs\006csrrsi\005csrrw\006csrrwi\004csrs\005" 1823 "csrsi\004csrw\005csrwi\003div\004divu\005divuw\004divw\006ebreak\005eca" 1824 "ll\006fabs.d\006fabs.s\006fadd.d\006fadd.s\010fclass.d\010fclass.s\010f" 1825 "cvt.d.l\tfcvt.d.lu\010fcvt.d.s\010fcvt.d.w\tfcvt.d.wu\010fcvt.l.d\010fc" 1826 "vt.l.s\tfcvt.lu.d\tfcvt.lu.s\010fcvt.s.d\010fcvt.s.l\tfcvt.s.lu\010fcvt" 1827 ".s.w\tfcvt.s.wu\010fcvt.w.d\010fcvt.w.s\tfcvt.wu.d\tfcvt.wu.s\006fdiv.d" 1828 "\006fdiv.s\005fence\007fence.i\tfence.tso\005feq.d\005feq.s\005fge.d\005" 1829 "fge.s\005fgt.d\005fgt.s\003fld\005fle.d\005fle.s\005flt.d\005flt.s\003f" 1830 "lw\007fmadd.d\007fmadd.s\006fmax.d\006fmax.s\006fmin.d\006fmin.s\007fms" 1831 "ub.d\007fmsub.s\006fmul.d\006fmul.s\005fmv.d\007fmv.d.x\005fmv.s\007fmv" 1832 ".w.x\007fmv.x.d\007fmv.x.w\006fneg.d\006fneg.s\010fnmadd.d\010fnmadd.s\010" 1833 "fnmsub.d\010fnmsub.s\005frcsr\007frflags\004frrm\004frsr\005fscsr\003fs" 1834 "d\007fsflags\010fsflagsi\007fsgnj.d\007fsgnj.s\010fsgnjn.d\010fsgnjn.s\010" 1835 "fsgnjx.d\010fsgnjx.s\007fsqrt.d\007fsqrt.s\004fsrm\005fsrmi\004fssr\006" 1836 "fsub.d\006fsub.s\003fsw\001j\003jal\004jalr\002jr\002la\tla.tls.gd\tla." 1837 "tls.ie\002lb\003lbu\002ld\002lh\003lhu\002li\003lla\004lr.d\007lr.d.aq\t" 1838 "lr.d.aqrl\007lr.d.rl\004lr.w\007lr.w.aq\tlr.w.aqrl\007lr.w.rl\003lui\002" 1839 "lw\003lwu\004mret\003mul\004mulh\006mulhsu\005mulhu\004mulw\002mv\003ne" 1840 "g\004negw\003nop\003not\002or\003ori\007rdcycle\010rdcycleh\trdinstret\n" 1841 "rdinstreth\006rdtime\007rdtimeh\003rem\004remu\005remuw\004remw\003ret\002" 1842 "sb\004sc.d\007sc.d.aq\tsc.d.aqrl\007sc.d.rl\004sc.w\007sc.w.aq\tsc.w.aq" 1843 "rl\007sc.w.rl\002sd\004seqz\006sext.w\nsfence.vma\003sgt\004sgtu\004sgt" 1844 "z\002sh\003sll\004slli\005slliw\004sllw\003slt\004slti\005sltiu\004sltu" 1845 "\004sltz\004snez\003sra\004srai\005sraiw\004sraw\004sret\003srl\004srli" 1846 "\005srliw\004srlw\003sub\004subw\002sw\004tail\005unimp\004uret\003wfi\003" 1847 "xor\004xori"; 1848 1849// Feature bitsets. 1850enum : uint8_t { 1851 AMFBS_None, 1852 AMFBS_HasStdExtA, 1853 AMFBS_HasStdExtC, 1854 AMFBS_HasStdExtD, 1855 AMFBS_HasStdExtF, 1856 AMFBS_HasStdExtM, 1857 AMFBS_IsRV32, 1858 AMFBS_IsRV64, 1859 AMFBS_HasStdExtA_IsRV64, 1860 AMFBS_HasStdExtC_HasRVCHints, 1861 AMFBS_HasStdExtC_HasStdExtD, 1862 AMFBS_HasStdExtC_IsRV32, 1863 AMFBS_HasStdExtC_IsRV64, 1864 AMFBS_HasStdExtD_IsRV64, 1865 AMFBS_HasStdExtF_IsRV64, 1866 AMFBS_HasStdExtM_IsRV64, 1867 AMFBS_HasStdExtC_HasStdExtF_IsRV32, 1868}; 1869 1870static constexpr FeatureBitset FeatureBitsets[] = { 1871 {}, // AMFBS_None 1872 {Feature_HasStdExtABit, }, 1873 {Feature_HasStdExtCBit, }, 1874 {Feature_HasStdExtDBit, }, 1875 {Feature_HasStdExtFBit, }, 1876 {Feature_HasStdExtMBit, }, 1877 {Feature_IsRV32Bit, }, 1878 {Feature_IsRV64Bit, }, 1879 {Feature_HasStdExtABit, Feature_IsRV64Bit, }, 1880 {Feature_HasStdExtCBit, Feature_HasRVCHintsBit, }, 1881 {Feature_HasStdExtCBit, Feature_HasStdExtDBit, }, 1882 {Feature_HasStdExtCBit, Feature_IsRV32Bit, }, 1883 {Feature_HasStdExtCBit, Feature_IsRV64Bit, }, 1884 {Feature_HasStdExtDBit, Feature_IsRV64Bit, }, 1885 {Feature_HasStdExtFBit, Feature_IsRV64Bit, }, 1886 {Feature_HasStdExtMBit, Feature_IsRV64Bit, }, 1887 {Feature_HasStdExtCBit, Feature_HasStdExtFBit, Feature_IsRV32Bit, }, 1888}; 1889 1890namespace { 1891 struct MatchEntry { 1892 uint16_t Mnemonic; 1893 uint16_t Opcode; 1894 uint8_t ConvertFn; 1895 uint8_t RequiredFeaturesIdx; 1896 uint8_t Classes[5]; 1897 StringRef getMnemonic() const { 1898 return StringRef(MnemonicTable + Mnemonic + 1, 1899 MnemonicTable[Mnemonic]); 1900 } 1901 }; 1902 1903 // Predicate for searching for an opcode. 1904 struct LessOpcode { 1905 bool operator()(const MatchEntry &LHS, StringRef RHS) { 1906 return LHS.getMnemonic() < RHS; 1907 } 1908 bool operator()(StringRef LHS, const MatchEntry &RHS) { 1909 return LHS < RHS.getMnemonic(); 1910 } 1911 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { 1912 return LHS.getMnemonic() < RHS.getMnemonic(); 1913 } 1914 }; 1915} // end anonymous namespace 1916 1917static const MatchEntry MatchTable0[] = { 1918 { 0 /* add */, RISCV::ADD, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 1919 { 0 /* add */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 1920 { 0 /* add */, RISCV::PseudoAddTPRel, Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR, MCK_TPRelAddSymbol }, }, 1921 { 4 /* addi */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 1922 { 9 /* addiw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 1923 { 15 /* addw */, RISCV::ADDW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 1924 { 15 /* addw */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 1925 { 20 /* amoadd.d */, RISCV::AMOADD_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1926 { 29 /* amoadd.d.aq */, RISCV::AMOADD_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1927 { 41 /* amoadd.d.aqrl */, RISCV::AMOADD_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1928 { 55 /* amoadd.d.rl */, RISCV::AMOADD_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1929 { 67 /* amoadd.w */, RISCV::AMOADD_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1930 { 76 /* amoadd.w.aq */, RISCV::AMOADD_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1931 { 88 /* amoadd.w.aqrl */, RISCV::AMOADD_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1932 { 102 /* amoadd.w.rl */, RISCV::AMOADD_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1933 { 114 /* amoand.d */, RISCV::AMOAND_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1934 { 123 /* amoand.d.aq */, RISCV::AMOAND_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1935 { 135 /* amoand.d.aqrl */, RISCV::AMOAND_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1936 { 149 /* amoand.d.rl */, RISCV::AMOAND_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1937 { 161 /* amoand.w */, RISCV::AMOAND_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1938 { 170 /* amoand.w.aq */, RISCV::AMOAND_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1939 { 182 /* amoand.w.aqrl */, RISCV::AMOAND_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1940 { 196 /* amoand.w.rl */, RISCV::AMOAND_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1941 { 208 /* amomax.d */, RISCV::AMOMAX_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1942 { 217 /* amomax.d.aq */, RISCV::AMOMAX_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1943 { 229 /* amomax.d.aqrl */, RISCV::AMOMAX_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1944 { 243 /* amomax.d.rl */, RISCV::AMOMAX_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1945 { 255 /* amomax.w */, RISCV::AMOMAX_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1946 { 264 /* amomax.w.aq */, RISCV::AMOMAX_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1947 { 276 /* amomax.w.aqrl */, RISCV::AMOMAX_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1948 { 290 /* amomax.w.rl */, RISCV::AMOMAX_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1949 { 302 /* amomaxu.d */, RISCV::AMOMAXU_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1950 { 312 /* amomaxu.d.aq */, RISCV::AMOMAXU_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1951 { 325 /* amomaxu.d.aqrl */, RISCV::AMOMAXU_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1952 { 340 /* amomaxu.d.rl */, RISCV::AMOMAXU_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1953 { 353 /* amomaxu.w */, RISCV::AMOMAXU_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1954 { 363 /* amomaxu.w.aq */, RISCV::AMOMAXU_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1955 { 376 /* amomaxu.w.aqrl */, RISCV::AMOMAXU_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1956 { 391 /* amomaxu.w.rl */, RISCV::AMOMAXU_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1957 { 404 /* amomin.d */, RISCV::AMOMIN_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1958 { 413 /* amomin.d.aq */, RISCV::AMOMIN_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1959 { 425 /* amomin.d.aqrl */, RISCV::AMOMIN_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1960 { 439 /* amomin.d.rl */, RISCV::AMOMIN_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1961 { 451 /* amomin.w */, RISCV::AMOMIN_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1962 { 460 /* amomin.w.aq */, RISCV::AMOMIN_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1963 { 472 /* amomin.w.aqrl */, RISCV::AMOMIN_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1964 { 486 /* amomin.w.rl */, RISCV::AMOMIN_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1965 { 498 /* amominu.d */, RISCV::AMOMINU_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1966 { 508 /* amominu.d.aq */, RISCV::AMOMINU_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1967 { 521 /* amominu.d.aqrl */, RISCV::AMOMINU_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1968 { 536 /* amominu.d.rl */, RISCV::AMOMINU_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1969 { 549 /* amominu.w */, RISCV::AMOMINU_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1970 { 559 /* amominu.w.aq */, RISCV::AMOMINU_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1971 { 572 /* amominu.w.aqrl */, RISCV::AMOMINU_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1972 { 587 /* amominu.w.rl */, RISCV::AMOMINU_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1973 { 600 /* amoor.d */, RISCV::AMOOR_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1974 { 608 /* amoor.d.aq */, RISCV::AMOOR_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1975 { 619 /* amoor.d.aqrl */, RISCV::AMOOR_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1976 { 632 /* amoor.d.rl */, RISCV::AMOOR_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1977 { 643 /* amoor.w */, RISCV::AMOOR_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1978 { 651 /* amoor.w.aq */, RISCV::AMOOR_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1979 { 662 /* amoor.w.aqrl */, RISCV::AMOOR_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1980 { 675 /* amoor.w.rl */, RISCV::AMOOR_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1981 { 686 /* amoswap.d */, RISCV::AMOSWAP_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1982 { 696 /* amoswap.d.aq */, RISCV::AMOSWAP_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1983 { 709 /* amoswap.d.aqrl */, RISCV::AMOSWAP_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1984 { 724 /* amoswap.d.rl */, RISCV::AMOSWAP_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1985 { 737 /* amoswap.w */, RISCV::AMOSWAP_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1986 { 747 /* amoswap.w.aq */, RISCV::AMOSWAP_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1987 { 760 /* amoswap.w.aqrl */, RISCV::AMOSWAP_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1988 { 775 /* amoswap.w.rl */, RISCV::AMOSWAP_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1989 { 788 /* amoxor.d */, RISCV::AMOXOR_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1990 { 797 /* amoxor.d.aq */, RISCV::AMOXOR_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1991 { 809 /* amoxor.d.aqrl */, RISCV::AMOXOR_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1992 { 823 /* amoxor.d.rl */, RISCV::AMOXOR_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1993 { 835 /* amoxor.w */, RISCV::AMOXOR_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1994 { 844 /* amoxor.w.aq */, RISCV::AMOXOR_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1995 { 856 /* amoxor.w.aqrl */, RISCV::AMOXOR_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1996 { 870 /* amoxor.w.rl */, RISCV::AMOXOR_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 1997 { 882 /* and */, RISCV::AND, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 1998 { 882 /* and */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 1999 { 886 /* andi */, RISCV::ANDI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2000 { 891 /* auipc */, RISCV::AUIPC, Convert__Reg1_0__UImm20AUIPC1_1, AMFBS_None, { MCK_GPR, MCK_UImm20AUIPC }, }, 2001 { 897 /* beq */, RISCV::BEQ, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2002 { 901 /* beqz */, RISCV::BEQ, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 2003 { 906 /* bge */, RISCV::BGE, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2004 { 910 /* bgeu */, RISCV::BGEU, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2005 { 915 /* bgez */, RISCV::BGE, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 2006 { 920 /* bgt */, RISCV::BLT, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2007 { 924 /* bgtu */, RISCV::BLTU, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2008 { 929 /* bgtz */, RISCV::BLT, Convert__regX0__Reg1_0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 2009 { 934 /* ble */, RISCV::BGE, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2010 { 938 /* bleu */, RISCV::BGEU, Convert__Reg1_1__Reg1_0__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2011 { 943 /* blez */, RISCV::BGE, Convert__regX0__Reg1_0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 2012 { 948 /* blt */, RISCV::BLT, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2013 { 952 /* bltu */, RISCV::BLTU, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2014 { 957 /* bltz */, RISCV::BLT, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 2015 { 962 /* bne */, RISCV::BNE, Convert__Reg1_0__Reg1_1__SImm13Lsb01_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm13Lsb0 }, }, 2016 { 966 /* bnez */, RISCV::BNE, Convert__Reg1_0__regX0__SImm13Lsb01_1, AMFBS_None, { MCK_GPR, MCK_SImm13Lsb0 }, }, 2017 { 971 /* c.add */, RISCV::C_ADD_HINT, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_GPRNoX0 }, }, 2018 { 971 /* c.add */, RISCV::C_ADD, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_GPRNoX0 }, }, 2019 { 977 /* c.addi */, RISCV::C_ADDI_NOP, Convert__Reg1_0__Tie0_1_1__ImmZero1_1, AMFBS_HasStdExtC, { MCK_GPRX0, MCK_ImmZero }, }, 2020 { 977 /* c.addi */, RISCV::C_ADDI_HINT_X0, Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_SImm6NonZero }, }, 2021 { 977 /* c.addi */, RISCV::C_ADDI_HINT_IMM_ZERO, Convert__Reg1_0__Tie0_1_1__ImmZero1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRNoX0, MCK_ImmZero }, }, 2022 { 977 /* c.addi */, RISCV::C_ADDI, Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_SImm6NonZero }, }, 2023 { 984 /* c.addi16sp */, RISCV::C_ADDI16SP, Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1, AMFBS_HasStdExtC, { MCK_SP, MCK_SImm10Lsb0000NonZero }, }, 2024 { 995 /* c.addi4spn */, RISCV::C_ADDI4SPN, Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2, AMFBS_HasStdExtC, { MCK_GPRC, MCK_SP, MCK_UImm10Lsb00NonZero }, }, 2025 { 1006 /* c.addiw */, RISCV::C_ADDIW, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRNoX0, MCK_SImm6 }, }, 2026 { 1014 /* c.addw */, RISCV::C_ADDW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK_GPRC }, }, 2027 { 1021 /* c.and */, RISCV::C_AND, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_GPRC }, }, 2028 { 1027 /* c.andi */, RISCV::C_ANDI, Convert__Reg1_0__Tie0_1_1__SImm61_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_SImm6 }, }, 2029 { 1034 /* c.beqz */, RISCV::C_BEQZ, Convert__Reg1_0__SImm9Lsb01_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_SImm9Lsb0 }, }, 2030 { 1041 /* c.bnez */, RISCV::C_BNEZ, Convert__Reg1_0__SImm9Lsb01_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_SImm9Lsb0 }, }, 2031 { 1048 /* c.ebreak */, RISCV::C_EBREAK, Convert_NoOperands, AMFBS_HasStdExtC, { }, }, 2032 { 1057 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2033 { 1057 /* c.fld */, RISCV::C_FLD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2034 { 1063 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_SP, MCK__41_ }, }, 2035 { 1063 /* c.fldsp */, RISCV::C_FLDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, }, 2036 { 1071 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2037 { 1071 /* c.flw */, RISCV::C_FLW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2038 { 1077 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_SP, MCK__41_ }, }, 2039 { 1077 /* c.flwsp */, RISCV::C_FLWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, }, 2040 { 1085 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2041 { 1085 /* c.fsd */, RISCV::C_FSD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2042 { 1091 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64C, MCK__40_, MCK_SP, MCK__41_ }, }, 2043 { 1091 /* c.fsdsp */, RISCV::C_FSDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtC_HasStdExtD, { MCK_FPR64, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, }, 2044 { 1099 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2045 { 1099 /* c.fsw */, RISCV::C_FSW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2046 { 1105 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32C, MCK__40_, MCK_SP, MCK__41_ }, }, 2047 { 1105 /* c.fswsp */, RISCV::C_FSWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtC_HasStdExtF_IsRV32, { MCK_FPR32, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, }, 2048 { 1113 /* c.j */, RISCV::C_J, Convert__SImm12Lsb01_0, AMFBS_HasStdExtC, { MCK_SImm12Lsb0 }, }, 2049 { 1117 /* c.jal */, RISCV::C_JAL, Convert__SImm12Lsb01_0, AMFBS_HasStdExtC_IsRV32, { MCK_SImm12Lsb0 }, }, 2050 { 1123 /* c.jalr */, RISCV::C_JALR, Convert__Reg1_0, AMFBS_HasStdExtC, { MCK_GPRNoX0 }, }, 2051 { 1130 /* c.jr */, RISCV::C_JR, Convert__Reg1_0, AMFBS_HasStdExtC, { MCK_GPRNoX0 }, }, 2052 { 1135 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2053 { 1135 /* c.ld */, RISCV::C_LD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2054 { 1140 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, }, 2055 { 1140 /* c.ldsp */, RISCV::C_LDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRNoX0, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, }, 2056 { 1147 /* c.li */, RISCV::C_LI_HINT, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_SImm6 }, }, 2057 { 1147 /* c.li */, RISCV::C_LI, Convert__Reg1_0__SImm61_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_SImm6 }, }, 2058 { 1152 /* c.lui */, RISCV::C_LUI_HINT, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_CLUIImm }, }, 2059 { 1152 /* c.lui */, RISCV::C_LUI, Convert__Reg1_0__CLUIImm1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0X2, MCK_CLUIImm }, }, 2060 { 1158 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2061 { 1158 /* c.lw */, RISCV::C_LW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2062 { 1163 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, }, 2063 { 1163 /* c.lwsp */, RISCV::C_LWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, }, 2064 { 1170 /* c.mv */, RISCV::C_MV_HINT, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_GPRNoX0 }, }, 2065 { 1170 /* c.mv */, RISCV::C_MV, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_GPRNoX0 }, }, 2066 { 1175 /* c.nop */, RISCV::C_NOP, Convert_NoOperands, AMFBS_HasStdExtC, { }, }, 2067 { 1175 /* c.nop */, RISCV::C_NOP_HINT, Convert__SImm6NonZero1_0, AMFBS_HasStdExtC_HasRVCHints, { MCK_SImm6NonZero }, }, 2068 { 1181 /* c.or */, RISCV::C_OR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_GPRC }, }, 2069 { 1186 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2070 { 1186 /* c.sd */, RISCV::C_SD, Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK_UImm8Lsb000, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2071 { 1191 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, }, 2072 { 1191 /* c.sdsp */, RISCV::C_SDSP, Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPR, MCK_UImm9Lsb000, MCK__40_, MCK_SP, MCK__41_ }, }, 2073 { 1198 /* c.slli */, RISCV::C_SLLI_HINT, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRX0, MCK_UImmLog2XLenNonZero }, }, 2074 { 1198 /* c.slli */, RISCV::C_SLLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtC, { MCK_GPRNoX0, MCK_UImmLog2XLenNonZero }, }, 2075 { 1205 /* c.slli64 */, RISCV::C_SLLI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPR }, }, 2076 { 1214 /* c.srai */, RISCV::C_SRAI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, }, 2077 { 1221 /* c.srai64 */, RISCV::C_SRAI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRC }, }, 2078 { 1230 /* c.srli */, RISCV::C_SRLI, Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_UImmLog2XLenNonZero }, }, 2079 { 1237 /* c.srli64 */, RISCV::C_SRLI64_HINT, Convert__Reg1_0__Tie0_1_1, AMFBS_HasStdExtC_HasRVCHints, { MCK_GPRC }, }, 2080 { 1246 /* c.sub */, RISCV::C_SUB, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_GPRC }, }, 2081 { 1252 /* c.subw */, RISCV::C_SUBW, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC_IsRV64, { MCK_GPRC, MCK_GPRC }, }, 2082 { 1259 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPRC, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2083 { 1259 /* c.sw */, RISCV::C_SW, Convert__Reg1_0__Reg1_3__UImm7Lsb001_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_UImm7Lsb00, MCK__40_, MCK_GPRC, MCK__41_ }, }, 2084 { 1264 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPRC, MCK__40_, MCK_SP, MCK__41_ }, }, 2085 { 1264 /* c.swsp */, RISCV::C_SWSP, Convert__Reg1_0__Reg1_3__UImm8Lsb001_1, AMFBS_HasStdExtC, { MCK_GPR, MCK_UImm8Lsb00, MCK__40_, MCK_SP, MCK__41_ }, }, 2086 { 1271 /* c.unimp */, RISCV::C_UNIMP, Convert_NoOperands, AMFBS_HasStdExtC, { }, }, 2087 { 1279 /* c.xor */, RISCV::C_XOR, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_HasStdExtC, { MCK_GPRC, MCK_GPRC }, }, 2088 { 1285 /* call */, RISCV::PseudoCALL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, }, 2089 { 1285 /* call */, RISCV::PseudoCALLReg, Convert__Reg1_0__CallSymbol1_1, AMFBS_None, { MCK_GPR, MCK_CallSymbol }, }, 2090 { 1290 /* csrc */, RISCV::CSRRC, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, }, 2091 { 1290 /* csrc */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 2092 { 1295 /* csrci */, RISCV::CSRRCI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 2093 { 1301 /* csrr */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__regX0, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister }, }, 2094 { 1306 /* csrrc */, RISCV::CSRRC, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, }, 2095 { 1306 /* csrrc */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 2096 { 1312 /* csrrci */, RISCV::CSRRCI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 2097 { 1319 /* csrrs */, RISCV::CSRRS, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, }, 2098 { 1319 /* csrrs */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 2099 { 1325 /* csrrsi */, RISCV::CSRRSI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 2100 { 1332 /* csrrw */, RISCV::CSRRW, Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_GPR }, }, 2101 { 1332 /* csrrw */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 2102 { 1338 /* csrrwi */, RISCV::CSRRWI, Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2, AMFBS_None, { MCK_GPR, MCK_CSRSystemRegister, MCK_UImm5 }, }, 2103 { 1345 /* csrs */, RISCV::CSRRS, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, }, 2104 { 1345 /* csrs */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 2105 { 1350 /* csrsi */, RISCV::CSRRSI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 2106 { 1356 /* csrw */, RISCV::CSRRW, Convert__regX0__CSRSystemRegister1_0__Reg1_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_GPR }, }, 2107 { 1356 /* csrw */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 2108 { 1361 /* csrwi */, RISCV::CSRRWI, Convert__regX0__CSRSystemRegister1_0__UImm51_1, AMFBS_None, { MCK_CSRSystemRegister, MCK_UImm5 }, }, 2109 { 1367 /* div */, RISCV::DIV, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2110 { 1371 /* divu */, RISCV::DIVU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2111 { 1376 /* divuw */, RISCV::DIVUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2112 { 1382 /* divw */, RISCV::DIVW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2113 { 1387 /* ebreak */, RISCV::EBREAK, Convert_NoOperands, AMFBS_None, { }, }, 2114 { 1394 /* ecall */, RISCV::ECALL, Convert_NoOperands, AMFBS_None, { }, }, 2115 { 1400 /* fabs.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, }, 2116 { 1407 /* fabs.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, }, 2117 { 1414 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2118 { 1414 /* fadd.d */, RISCV::FADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 2119 { 1421 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2120 { 1421 /* fadd.s */, RISCV::FADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 2121 { 1428 /* fclass.d */, RISCV::FCLASS_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, }, 2122 { 1437 /* fclass.s */, RISCV::FCLASS_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, }, 2123 { 1446 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, }, 2124 { 1446 /* fcvt.d.l */, RISCV::FCVT_D_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, }, 2125 { 1455 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, }, 2126 { 1455 /* fcvt.d.lu */, RISCV::FCVT_D_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR, MCK_FRMArg }, }, 2127 { 1465 /* fcvt.d.s */, RISCV::FCVT_D_S, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR32 }, }, 2128 { 1474 /* fcvt.d.w */, RISCV::FCVT_D_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR }, }, 2129 { 1483 /* fcvt.d.wu */, RISCV::FCVT_D_WU, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_GPR }, }, 2130 { 1493 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, }, 2131 { 1493 /* fcvt.l.d */, RISCV::FCVT_L_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, }, 2132 { 1502 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32 }, }, 2133 { 1502 /* fcvt.l.s */, RISCV::FCVT_L_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, }, 2134 { 1511 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, }, 2135 { 1511 /* fcvt.lu.d */, RISCV::FCVT_LU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, }, 2136 { 1521 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32 }, }, 2137 { 1521 /* fcvt.lu.s */, RISCV::FCVT_LU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, }, 2138 { 1531 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64 }, }, 2139 { 1531 /* fcvt.s.d */, RISCV::FCVT_S_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR32, MCK_FPR64, MCK_FRMArg }, }, 2140 { 1540 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR }, }, 2141 { 1540 /* fcvt.s.l */, RISCV::FCVT_S_L, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, }, 2142 { 1549 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR }, }, 2143 { 1549 /* fcvt.s.lu */, RISCV::FCVT_S_LU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF_IsRV64, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, }, 2144 { 1559 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, }, 2145 { 1559 /* fcvt.s.w */, RISCV::FCVT_S_W, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, }, 2146 { 1568 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, }, 2147 { 1568 /* fcvt.s.wu */, RISCV::FCVT_S_WU, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR, MCK_FRMArg }, }, 2148 { 1578 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, }, 2149 { 1578 /* fcvt.w.d */, RISCV::FCVT_W_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, }, 2150 { 1587 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, }, 2151 { 1587 /* fcvt.w.s */, RISCV::FCVT_W_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, }, 2152 { 1596 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64 }, }, 2153 { 1596 /* fcvt.wu.d */, RISCV::FCVT_WU_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FRMArg }, }, 2154 { 1606 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, }, 2155 { 1606 /* fcvt.wu.s */, RISCV::FCVT_WU_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FRMArg }, }, 2156 { 1616 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2157 { 1616 /* fdiv.d */, RISCV::FDIV_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 2158 { 1623 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2159 { 1623 /* fdiv.s */, RISCV::FDIV_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 2160 { 1630 /* fence */, RISCV::FENCE, Convert__imm_95_15__imm_95_15, AMFBS_None, { }, }, 2161 { 1630 /* fence */, RISCV::FENCE, Convert__FenceArg1_0__FenceArg1_1, AMFBS_None, { MCK_FenceArg, MCK_FenceArg }, }, 2162 { 1636 /* fence.i */, RISCV::FENCE_I, Convert_NoOperands, AMFBS_None, { }, }, 2163 { 1644 /* fence.tso */, RISCV::FENCE_TSO, Convert_NoOperands, AMFBS_None, { }, }, 2164 { 1654 /* feq.d */, RISCV::FEQ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 2165 { 1660 /* feq.s */, RISCV::FEQ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 2166 { 1666 /* fge.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 2167 { 1672 /* fge.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 2168 { 1678 /* fgt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 2169 { 1684 /* fgt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 2170 { 1690 /* fld */, RISCV::PseudoFLD, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, }, 2171 { 1690 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, }, 2172 { 1690 /* fld */, RISCV::FLD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2173 { 1694 /* fle.d */, RISCV::FLE_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 2174 { 1700 /* fle.s */, RISCV::FLE_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 2175 { 1706 /* flt.d */, RISCV::FLT_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_GPR, MCK_FPR64, MCK_FPR64 }, }, 2176 { 1712 /* flt.s */, RISCV::FLT_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32, MCK_FPR32 }, }, 2177 { 1718 /* flw */, RISCV::PseudoFLW, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, }, 2178 { 1718 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, }, 2179 { 1718 /* flw */, RISCV::FLW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2180 { 1722 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2181 { 1722 /* fmadd.d */, RISCV::FMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 2182 { 1730 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2183 { 1730 /* fmadd.s */, RISCV::FMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 2184 { 1738 /* fmax.d */, RISCV::FMAX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2185 { 1745 /* fmax.s */, RISCV::FMAX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2186 { 1752 /* fmin.d */, RISCV::FMIN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2187 { 1759 /* fmin.s */, RISCV::FMIN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2188 { 1766 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2189 { 1766 /* fmsub.d */, RISCV::FMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 2190 { 1774 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2191 { 1774 /* fmsub.s */, RISCV::FMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 2192 { 1782 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2193 { 1782 /* fmul.d */, RISCV::FMUL_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 2194 { 1789 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2195 { 1789 /* fmul.s */, RISCV::FMUL_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 2196 { 1796 /* fmv.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, }, 2197 { 1802 /* fmv.d.x */, RISCV::FMV_D_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_FPR64, MCK_GPR }, }, 2198 { 1810 /* fmv.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, }, 2199 { 1816 /* fmv.w.x */, RISCV::FMV_W_X, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_GPR }, }, 2200 { 1824 /* fmv.x.d */, RISCV::FMV_X_D, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtD_IsRV64, { MCK_GPR, MCK_FPR64 }, }, 2201 { 1832 /* fmv.x.w */, RISCV::FMV_X_W, Convert__Reg1_0__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_FPR32 }, }, 2202 { 1840 /* fneg.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, }, 2203 { 1847 /* fneg.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, }, 2204 { 1854 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2205 { 1854 /* fnmadd.d */, RISCV::FNMADD_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 2206 { 1863 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2207 { 1863 /* fnmadd.s */, RISCV::FNMADD_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 2208 { 1872 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2209 { 1872 /* fnmsub.d */, RISCV::FNMSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 2210 { 1881 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2211 { 1881 /* fnmsub.s */, RISCV::FNMSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 2212 { 1890 /* frcsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtF, { MCK_GPR }, }, 2213 { 1896 /* frflags */, RISCV::CSRRS, Convert__Reg1_0__imm_95_1__regX0, AMFBS_HasStdExtF, { MCK_GPR }, }, 2214 { 1904 /* frrm */, RISCV::CSRRS, Convert__Reg1_0__imm_95_2__regX0, AMFBS_HasStdExtF, { MCK_GPR }, }, 2215 { 1909 /* frsr */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3__regX0, AMFBS_HasStdExtF, { MCK_GPR }, }, 2216 { 1914 /* fscsr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, }, 2217 { 1914 /* fscsr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, }, 2218 { 1920 /* fsd */, RISCV::PseudoFSD, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_BareSymbol, MCK_GPR }, }, 2219 { 1920 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtD, { MCK_FPR64, MCK__40_, MCK_GPR, MCK__41_ }, }, 2220 { 1920 /* fsd */, RISCV::FSD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtD, { MCK_FPR64, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2221 { 1924 /* fsflags */, RISCV::CSRRW, Convert__regX0__imm_95_1__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, }, 2222 { 1924 /* fsflags */, RISCV::CSRRW, Convert__Reg1_0__imm_95_1__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, }, 2223 { 1932 /* fsflagsi */, RISCV::CSRRWI, Convert__regX0__imm_95_1__UImm51_0, AMFBS_HasStdExtF, { MCK_UImm5 }, }, 2224 { 1932 /* fsflagsi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_1__UImm51_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_UImm5 }, }, 2225 { 1941 /* fsgnj.d */, RISCV::FSGNJ_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2226 { 1949 /* fsgnj.s */, RISCV::FSGNJ_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2227 { 1957 /* fsgnjn.d */, RISCV::FSGNJN_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2228 { 1966 /* fsgnjn.s */, RISCV::FSGNJN_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2229 { 1975 /* fsgnjx.d */, RISCV::FSGNJX_D, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2230 { 1984 /* fsgnjx.s */, RISCV::FSGNJX_S, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2231 { 1993 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64 }, }, 2232 { 1993 /* fsqrt.d */, RISCV::FSQRT_D, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 2233 { 2001 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32 }, }, 2234 { 2001 /* fsqrt.s */, RISCV::FSQRT_S, Convert__Reg1_0__Reg1_1__FRMArg1_2, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 2235 { 2009 /* fsrm */, RISCV::CSRRW, Convert__regX0__imm_95_2__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, }, 2236 { 2009 /* fsrm */, RISCV::CSRRW, Convert__Reg1_0__imm_95_2__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, }, 2237 { 2014 /* fsrmi */, RISCV::CSRRWI, Convert__regX0__imm_95_2__UImm51_0, AMFBS_HasStdExtF, { MCK_UImm5 }, }, 2238 { 2014 /* fsrmi */, RISCV::CSRRWI, Convert__Reg1_0__imm_95_2__UImm51_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_UImm5 }, }, 2239 { 2020 /* fssr */, RISCV::CSRRW, Convert__regX0__imm_95_3__Reg1_0, AMFBS_HasStdExtF, { MCK_GPR }, }, 2240 { 2020 /* fssr */, RISCV::CSRRW, Convert__Reg1_0__imm_95_3__Reg1_1, AMFBS_HasStdExtF, { MCK_GPR, MCK_GPR }, }, 2241 { 2025 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64 }, }, 2242 { 2025 /* fsub.d */, RISCV::FSUB_D, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtD, { MCK_FPR64, MCK_FPR64, MCK_FPR64, MCK_FRMArg }, }, 2243 { 2032 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32 }, }, 2244 { 2032 /* fsub.s */, RISCV::FSUB_S, Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3, AMFBS_HasStdExtF, { MCK_FPR32, MCK_FPR32, MCK_FPR32, MCK_FRMArg }, }, 2245 { 2039 /* fsw */, RISCV::PseudoFSW, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_BareSymbol, MCK_GPR }, }, 2246 { 2039 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_HasStdExtF, { MCK_FPR32, MCK__40_, MCK_GPR, MCK__41_ }, }, 2247 { 2039 /* fsw */, RISCV::FSW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_HasStdExtF, { MCK_FPR32, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2248 { 2043 /* j */, RISCV::JAL, Convert__regX0__SImm21Lsb0JAL1_0, AMFBS_None, { MCK_SImm21Lsb0JAL }, }, 2249 { 2045 /* jal */, RISCV::JAL, Convert__regX1__SImm21Lsb0JAL1_0, AMFBS_None, { MCK_SImm21Lsb0JAL }, }, 2250 { 2045 /* jal */, RISCV::JAL, Convert__Reg1_0__SImm21Lsb0JAL1_1, AMFBS_None, { MCK_GPR, MCK_SImm21Lsb0JAL }, }, 2251 { 2049 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, }, 2252 { 2049 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 2253 { 2049 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, }, 2254 { 2049 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2255 { 2049 /* jalr */, RISCV::JALR, Convert__regX1__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2256 { 2049 /* jalr */, RISCV::JALR, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2257 { 2054 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__imm_95_0, AMFBS_None, { MCK_GPR }, }, 2258 { 2054 /* jr */, RISCV::JALR, Convert__regX0__Reg1_0__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12 }, }, 2259 { 2054 /* jr */, RISCV::JALR, Convert__regX0__Reg1_2__SImm121_0, AMFBS_None, { MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2260 { 2057 /* la */, RISCV::PseudoLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 2261 { 2060 /* la.tls.gd */, RISCV::PseudoLA_TLS_GD, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 2262 { 2070 /* la.tls.ie */, RISCV::PseudoLA_TLS_IE, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 2263 { 2080 /* lb */, RISCV::PseudoLB, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 2264 { 2080 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2265 { 2080 /* lb */, RISCV::LB, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2266 { 2083 /* lbu */, RISCV::PseudoLBU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 2267 { 2083 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2268 { 2083 /* lbu */, RISCV::LBU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2269 { 2087 /* ld */, RISCV::PseudoLD, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, }, 2270 { 2087 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2271 { 2087 /* ld */, RISCV::LD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2272 { 2090 /* lh */, RISCV::PseudoLH, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 2273 { 2090 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2274 { 2090 /* lh */, RISCV::LH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2275 { 2093 /* lhu */, RISCV::PseudoLHU, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 2276 { 2093 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2277 { 2093 /* lhu */, RISCV::LHU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2278 { 2097 /* li */, RISCV::PseudoLI, Convert__Reg1_0__ImmXLenLI1_1, AMFBS_None, { MCK_GPR, MCK_ImmXLenLI }, }, 2279 { 2100 /* lla */, RISCV::PseudoLLA, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 2280 { 2104 /* lr.d */, RISCV::LR_D, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_AtomicMemOpOperand }, }, 2281 { 2109 /* lr.d.aq */, RISCV::LR_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_AtomicMemOpOperand }, }, 2282 { 2117 /* lr.d.aqrl */, RISCV::LR_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_AtomicMemOpOperand }, }, 2283 { 2127 /* lr.d.rl */, RISCV::LR_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_AtomicMemOpOperand }, }, 2284 { 2135 /* lr.w */, RISCV::LR_W, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_AtomicMemOpOperand }, }, 2285 { 2140 /* lr.w.aq */, RISCV::LR_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_AtomicMemOpOperand }, }, 2286 { 2148 /* lr.w.aqrl */, RISCV::LR_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_AtomicMemOpOperand }, }, 2287 { 2158 /* lr.w.rl */, RISCV::LR_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_AtomicMemOpOperand }, }, 2288 { 2166 /* lui */, RISCV::LUI, Convert__Reg1_0__UImm20LUI1_1, AMFBS_None, { MCK_GPR, MCK_UImm20LUI }, }, 2289 { 2170 /* lw */, RISCV::PseudoLW, Convert__Reg1_0__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol }, }, 2290 { 2170 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2291 { 2170 /* lw */, RISCV::LW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2292 { 2173 /* lwu */, RISCV::PseudoLWU, Convert__Reg1_0__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol }, }, 2293 { 2173 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2294 { 2173 /* lwu */, RISCV::LWU, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2295 { 2177 /* mret */, RISCV::MRET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, }, 2296 { 2182 /* mul */, RISCV::MUL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2297 { 2186 /* mulh */, RISCV::MULH, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2298 { 2191 /* mulhsu */, RISCV::MULHSU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2299 { 2198 /* mulhu */, RISCV::MULHU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2300 { 2204 /* mulw */, RISCV::MULW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2301 { 2209 /* mv */, RISCV::ADDI, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 2302 { 2212 /* neg */, RISCV::SUB, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 2303 { 2216 /* negw */, RISCV::SUBW, Convert__Reg1_0__regX0__Reg1_1, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, }, 2304 { 2221 /* nop */, RISCV::ADDI, Convert__regX0__regX0__imm_95_0, AMFBS_None, { }, }, 2305 { 2225 /* not */, RISCV::XORI, Convert__Reg1_0__Reg1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 2306 { 2229 /* or */, RISCV::OR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2307 { 2229 /* or */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2308 { 2232 /* ori */, RISCV::ORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2309 { 2236 /* rdcycle */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3072__regX0, AMFBS_None, { MCK_GPR }, }, 2310 { 2244 /* rdcycleh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3200__regX0, AMFBS_IsRV32, { MCK_GPR }, }, 2311 { 2253 /* rdinstret */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3074__regX0, AMFBS_None, { MCK_GPR }, }, 2312 { 2263 /* rdinstreth */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3202__regX0, AMFBS_IsRV32, { MCK_GPR }, }, 2313 { 2274 /* rdtime */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3073__regX0, AMFBS_None, { MCK_GPR }, }, 2314 { 2281 /* rdtimeh */, RISCV::CSRRS, Convert__Reg1_0__imm_95_3201__regX0, AMFBS_IsRV32, { MCK_GPR }, }, 2315 { 2289 /* rem */, RISCV::REM, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2316 { 2293 /* remu */, RISCV::REMU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2317 { 2298 /* remuw */, RISCV::REMUW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2318 { 2304 /* remw */, RISCV::REMW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_HasStdExtM_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2319 { 2309 /* ret */, RISCV::JALR, Convert__regX0__regX1__imm_95_0, AMFBS_None, { }, }, 2320 { 2313 /* sb */, RISCV::PseudoSB, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, }, 2321 { 2313 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2322 { 2313 /* sb */, RISCV::SB, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2323 { 2316 /* sc.d */, RISCV::SC_D, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 2324 { 2321 /* sc.d.aq */, RISCV::SC_D_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 2325 { 2329 /* sc.d.aqrl */, RISCV::SC_D_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 2326 { 2339 /* sc.d.rl */, RISCV::SC_D_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA_IsRV64, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 2327 { 2347 /* sc.w */, RISCV::SC_W, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 2328 { 2352 /* sc.w.aq */, RISCV::SC_W_AQ, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 2329 { 2360 /* sc.w.aqrl */, RISCV::SC_W_AQ_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 2330 { 2370 /* sc.w.rl */, RISCV::SC_W_RL, Convert__Reg1_0__AtomicMemOpOperand1_2__Reg1_1, AMFBS_HasStdExtA, { MCK_GPR, MCK_GPR, MCK_AtomicMemOpOperand }, }, 2331 { 2378 /* sd */, RISCV::PseudoSD, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_IsRV64, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, }, 2332 { 2378 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2333 { 2378 /* sd */, RISCV::SD, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_IsRV64, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2334 { 2381 /* seqz */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__imm_95_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 2335 { 2386 /* sext.w */, RISCV::ADDIW, Convert__Reg1_0__Reg1_1__imm_95_0, AMFBS_IsRV64, { MCK_GPR, MCK_GPR }, }, 2336 { 2393 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__regX0__regX0, AMFBS_None, { }, }, 2337 { 2393 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__regX0, AMFBS_None, { MCK_GPR }, }, 2338 { 2393 /* sfence.vma */, RISCV::SFENCE_VMA, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 2339 { 2404 /* sgt */, RISCV::SLT, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2340 { 2408 /* sgtu */, RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2341 { 2413 /* sgtz */, RISCV::SLT, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 2342 { 2418 /* sh */, RISCV::PseudoSH, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, }, 2343 { 2418 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2344 { 2418 /* sh */, RISCV::SH, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2345 { 2421 /* sll */, RISCV::SLL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2346 { 2421 /* sll */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 2347 { 2425 /* slli */, RISCV::SLLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 2348 { 2430 /* slliw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 2349 { 2436 /* sllw */, RISCV::SLLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2350 { 2436 /* sllw */, RISCV::SLLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 2351 { 2441 /* slt */, RISCV::SLT, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2352 { 2441 /* slt */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2353 { 2445 /* slti */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2354 { 2450 /* sltiu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2355 { 2456 /* sltu */, RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2356 { 2456 /* sltu */, RISCV::SLTIU, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2357 { 2461 /* sltz */, RISCV::SLT, Convert__Reg1_0__Reg1_1__regX0, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 2358 { 2466 /* snez */, RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, }, 2359 { 2471 /* sra */, RISCV::SRA, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2360 { 2471 /* sra */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 2361 { 2475 /* srai */, RISCV::SRAI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 2362 { 2480 /* sraiw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 2363 { 2486 /* sraw */, RISCV::SRAW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2364 { 2486 /* sraw */, RISCV::SRAIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 2365 { 2491 /* sret */, RISCV::SRET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, }, 2366 { 2496 /* srl */, RISCV::SRL, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2367 { 2496 /* srl */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 2368 { 2500 /* srli */, RISCV::SRLI, Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_UImmLog2XLen }, }, 2369 { 2505 /* srliw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 2370 { 2511 /* srlw */, RISCV::SRLW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2371 { 2511 /* srlw */, RISCV::SRLIW, Convert__Reg1_0__Reg1_1__UImm51_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_UImm5 }, }, 2372 { 2516 /* sub */, RISCV::SUB, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2373 { 2520 /* subw */, RISCV::SUBW, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_IsRV64, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2374 { 2525 /* sw */, RISCV::PseudoSW, Convert__Reg1_0__Reg1_2__BareSymbol1_1, AMFBS_None, { MCK_GPR, MCK_BareSymbol, MCK_GPR }, }, 2375 { 2525 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR, MCK__40_, MCK_GPR, MCK__41_ }, }, 2376 { 2525 /* sw */, RISCV::SW, Convert__Reg1_0__Reg1_3__SImm121_1, AMFBS_None, { MCK_GPR, MCK_SImm12, MCK__40_, MCK_GPR, MCK__41_ }, }, 2377 { 2528 /* tail */, RISCV::PseudoTAIL, Convert__CallSymbol1_0, AMFBS_None, { MCK_CallSymbol }, }, 2378 { 2533 /* unimp */, RISCV::UNIMP, Convert_NoOperands, AMFBS_None, { }, }, 2379 { 2539 /* uret */, RISCV::URET, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, }, 2380 { 2544 /* wfi */, RISCV::WFI, Convert__imm_95_0__imm_95_0, AMFBS_None, { }, }, 2381 { 2548 /* xor */, RISCV::XOR, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_GPR }, }, 2382 { 2548 /* xor */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2383 { 2552 /* xori */, RISCV::XORI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR, MCK_SImm12 }, }, 2384}; 2385 2386#include "llvm/Support/Debug.h" 2387#include "llvm/Support/Format.h" 2388 2389unsigned RISCVAsmParser:: 2390MatchInstructionImpl(const OperandVector &Operands, 2391 MCInst &Inst, 2392 uint64_t &ErrorInfo, 2393 FeatureBitset &MissingFeatures, 2394 bool matchingInlineAsm, unsigned VariantID) { 2395 // Eliminate obvious mismatches. 2396 if (Operands.size() > 6) { 2397 ErrorInfo = 6; 2398 return Match_InvalidOperand; 2399 } 2400 2401 // Get the current feature set. 2402 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 2403 2404 // Get the instruction mnemonic, which is the first token. 2405 StringRef Mnemonic = ((RISCVOperand&)*Operands[0]).getToken(); 2406 2407 // Process all MnemonicAliases to remap the mnemonic. 2408 applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); 2409 2410 // Some state to try to produce better error messages. 2411 bool HadMatchOtherThanFeatures = false; 2412 bool HadMatchOtherThanPredicate = false; 2413 unsigned RetCode = Match_InvalidOperand; 2414 MissingFeatures.set(); 2415 // Set ErrorInfo to the operand that mismatches if it is 2416 // wrong for all instances of the instruction. 2417 ErrorInfo = ~0ULL; 2418 // Find the appropriate table for this asm variant. 2419 const MatchEntry *Start, *End; 2420 switch (VariantID) { 2421 default: llvm_unreachable("invalid variant!"); 2422 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 2423 } 2424 // Search the table. 2425 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 2426 2427 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " << 2428 std::distance(MnemonicRange.first, MnemonicRange.second) << 2429 " encodings with mnemonic '" << Mnemonic << "'\n"); 2430 2431 // Return a more specific error code if no mnemonics match. 2432 if (MnemonicRange.first == MnemonicRange.second) 2433 return Match_MnemonicFail; 2434 2435 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 2436 it != ie; ++it) { 2437 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 2438 bool HasRequiredFeatures = 2439 (AvailableFeatures & RequiredFeatures) == RequiredFeatures; 2440 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " 2441 << MII.getName(it->Opcode) << "\n"); 2442 // equal_range guarantees that instruction mnemonic matches. 2443 assert(Mnemonic == it->getMnemonic()); 2444 bool OperandsValid = true; 2445 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 5; ++FormalIdx) { 2446 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); 2447 DEBUG_WITH_TYPE("asm-matcher", 2448 dbgs() << " Matching formal operand class " << getMatchClassName(Formal) 2449 << " against actual operand at index " << ActualIdx); 2450 if (ActualIdx < Operands.size()) 2451 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " ("; 2452 Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); 2453 else 2454 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": "); 2455 if (ActualIdx >= Operands.size()) { 2456 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range "); 2457 OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass); 2458 if (!OperandsValid) ErrorInfo = ActualIdx; 2459 break; 2460 } 2461 MCParsedAsmOperand &Actual = *Operands[ActualIdx]; 2462 unsigned Diag = validateOperandClass(Actual, Formal); 2463 if (Diag == Match_Success) { 2464 DEBUG_WITH_TYPE("asm-matcher", 2465 dbgs() << "match success using generic matcher\n"); 2466 ++ActualIdx; 2467 continue; 2468 } 2469 // If the generic handler indicates an invalid operand 2470 // failure, check for a special case. 2471 if (Diag != Match_Success) { 2472 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); 2473 if (TargetDiag == Match_Success) { 2474 DEBUG_WITH_TYPE("asm-matcher", 2475 dbgs() << "match success using target matcher\n"); 2476 ++ActualIdx; 2477 continue; 2478 } 2479 // If the target matcher returned a specific error code use 2480 // that, else use the one from the generic matcher. 2481 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures) 2482 Diag = TargetDiag; 2483 } 2484 // If current formal operand wasn't matched and it is optional 2485 // then try to match next formal operand 2486 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { 2487 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); 2488 continue; 2489 } 2490 // If this operand is broken for all of the instances of this 2491 // mnemonic, keep track of it so we can report loc info. 2492 // If we already had a match that only failed due to a 2493 // target predicate, that diagnostic is preferred. 2494 if (!HadMatchOtherThanPredicate && 2495 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) { 2496 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand)) 2497 RetCode = Diag; 2498 ErrorInfo = ActualIdx; 2499 } 2500 // Otherwise, just reject this instance of the mnemonic. 2501 OperandsValid = false; 2502 break; 2503 } 2504 2505 if (!OperandsValid) { 2506 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 2507 "operand mismatches, ignoring " 2508 "this opcode\n"); 2509 continue; 2510 } 2511 if (!HasRequiredFeatures) { 2512 HadMatchOtherThanFeatures = true; 2513 FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures; 2514 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:"; 2515 for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I) 2516 if (NewMissingFeatures[I]) 2517 dbgs() << ' ' << I; 2518 dbgs() << "\n"); 2519 if (NewMissingFeatures.count() <= 2520 MissingFeatures.count()) 2521 MissingFeatures = NewMissingFeatures; 2522 continue; 2523 } 2524 2525 Inst.clear(); 2526 2527 Inst.setOpcode(it->Opcode); 2528 // We have a potential match but have not rendered the operands. 2529 // Check the target predicate to handle any context sensitive 2530 // constraints. 2531 // For example, Ties that are referenced multiple times must be 2532 // checked here to ensure the input is the same for each match 2533 // constraints. If we leave it any later the ties will have been 2534 // canonicalized 2535 unsigned MatchResult; 2536 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { 2537 Inst.clear(); 2538 DEBUG_WITH_TYPE( 2539 "asm-matcher", 2540 dbgs() << "Early target match predicate failed with diag code " 2541 << MatchResult << "\n"); 2542 RetCode = MatchResult; 2543 HadMatchOtherThanPredicate = true; 2544 continue; 2545 } 2546 2547 if (matchingInlineAsm) { 2548 convertToMapAndConstraints(it->ConvertFn, Operands); 2549 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) 2550 return Match_InvalidTiedOperand; 2551 2552 return Match_Success; 2553 } 2554 2555 // We have selected a definite instruction, convert the parsed 2556 // operands into the appropriate MCInst. 2557 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); 2558 2559 // We have a potential match. Check the target predicate to 2560 // handle any context sensitive constraints. 2561 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { 2562 DEBUG_WITH_TYPE("asm-matcher", 2563 dbgs() << "Target match predicate failed with diag code " 2564 << MatchResult << "\n"); 2565 Inst.clear(); 2566 RetCode = MatchResult; 2567 HadMatchOtherThanPredicate = true; 2568 continue; 2569 } 2570 2571 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) 2572 return Match_InvalidTiedOperand; 2573 2574 DEBUG_WITH_TYPE( 2575 "asm-matcher", 2576 dbgs() << "Opcode result: complete match, selecting this opcode\n"); 2577 return Match_Success; 2578 } 2579 2580 // Okay, we had no match. Try to return a useful error code. 2581 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures) 2582 return RetCode; 2583 2584 ErrorInfo = 0; 2585 return Match_MissingFeature; 2586} 2587 2588namespace { 2589 struct OperandMatchEntry { 2590 uint16_t Mnemonic; 2591 uint8_t OperandMask; 2592 uint8_t Class; 2593 uint8_t RequiredFeaturesIdx; 2594 2595 StringRef getMnemonic() const { 2596 return StringRef(MnemonicTable + Mnemonic + 1, 2597 MnemonicTable[Mnemonic]); 2598 } 2599 }; 2600 2601 // Predicate for searching for an opcode. 2602 struct LessOpcodeOperand { 2603 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { 2604 return LHS.getMnemonic() < RHS; 2605 } 2606 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { 2607 return LHS < RHS.getMnemonic(); 2608 } 2609 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { 2610 return LHS.getMnemonic() < RHS.getMnemonic(); 2611 } 2612 }; 2613} // end anonymous namespace 2614 2615static const OperandMatchEntry OperandMatchTable[133] = { 2616 /* Operand List Mnemonic, Mask, Operand Class, Features */ 2617 { 0 /* add */, 8 /* 3 */, MCK_TPRelAddSymbol, AMFBS_None }, 2618 { 20 /* amoadd.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2619 { 29 /* amoadd.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2620 { 41 /* amoadd.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2621 { 55 /* amoadd.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2622 { 67 /* amoadd.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2623 { 76 /* amoadd.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2624 { 88 /* amoadd.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2625 { 102 /* amoadd.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2626 { 114 /* amoand.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2627 { 123 /* amoand.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2628 { 135 /* amoand.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2629 { 149 /* amoand.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2630 { 161 /* amoand.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2631 { 170 /* amoand.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2632 { 182 /* amoand.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2633 { 196 /* amoand.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2634 { 208 /* amomax.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2635 { 217 /* amomax.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2636 { 229 /* amomax.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2637 { 243 /* amomax.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2638 { 255 /* amomax.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2639 { 264 /* amomax.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2640 { 276 /* amomax.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2641 { 290 /* amomax.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2642 { 302 /* amomaxu.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2643 { 312 /* amomaxu.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2644 { 325 /* amomaxu.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2645 { 340 /* amomaxu.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2646 { 353 /* amomaxu.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2647 { 363 /* amomaxu.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2648 { 376 /* amomaxu.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2649 { 391 /* amomaxu.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2650 { 404 /* amomin.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2651 { 413 /* amomin.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2652 { 425 /* amomin.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2653 { 439 /* amomin.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2654 { 451 /* amomin.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2655 { 460 /* amomin.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2656 { 472 /* amomin.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2657 { 486 /* amomin.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2658 { 498 /* amominu.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2659 { 508 /* amominu.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2660 { 521 /* amominu.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2661 { 536 /* amominu.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2662 { 549 /* amominu.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2663 { 559 /* amominu.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2664 { 572 /* amominu.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2665 { 587 /* amominu.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2666 { 600 /* amoor.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2667 { 608 /* amoor.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2668 { 619 /* amoor.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2669 { 632 /* amoor.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2670 { 643 /* amoor.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2671 { 651 /* amoor.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2672 { 662 /* amoor.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2673 { 675 /* amoor.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2674 { 686 /* amoswap.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2675 { 696 /* amoswap.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2676 { 709 /* amoswap.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2677 { 724 /* amoswap.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2678 { 737 /* amoswap.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2679 { 747 /* amoswap.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2680 { 760 /* amoswap.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2681 { 775 /* amoswap.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2682 { 788 /* amoxor.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2683 { 797 /* amoxor.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2684 { 809 /* amoxor.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2685 { 823 /* amoxor.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2686 { 835 /* amoxor.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2687 { 844 /* amoxor.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2688 { 856 /* amoxor.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2689 { 870 /* amoxor.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2690 { 1285 /* call */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None }, 2691 { 1285 /* call */, 2 /* 1 */, MCK_CallSymbol, AMFBS_None }, 2692 { 1290 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 2693 { 1290 /* csrc */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 2694 { 1295 /* csrci */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 2695 { 1301 /* csrr */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2696 { 1306 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2697 { 1306 /* csrrc */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2698 { 1312 /* csrrci */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2699 { 1319 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2700 { 1319 /* csrrs */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2701 { 1325 /* csrrsi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2702 { 1332 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2703 { 1332 /* csrrw */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2704 { 1338 /* csrrwi */, 2 /* 1 */, MCK_CSRSystemRegister, AMFBS_None }, 2705 { 1345 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 2706 { 1345 /* csrs */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 2707 { 1350 /* csrsi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 2708 { 1356 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 2709 { 1356 /* csrw */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 2710 { 1361 /* csrwi */, 1 /* 0 */, MCK_CSRSystemRegister, AMFBS_None }, 2711 { 1690 /* fld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD }, 2712 { 1718 /* flw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF }, 2713 { 1920 /* fsd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtD }, 2714 { 2039 /* fsw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_HasStdExtF }, 2715 { 2043 /* j */, 1 /* 0 */, MCK_SImm21Lsb0JAL, AMFBS_None }, 2716 { 2045 /* jal */, 1 /* 0 */, MCK_SImm21Lsb0JAL, AMFBS_None }, 2717 { 2045 /* jal */, 2 /* 1 */, MCK_SImm21Lsb0JAL, AMFBS_None }, 2718 { 2057 /* la */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2719 { 2060 /* la.tls.gd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2720 { 2070 /* la.tls.ie */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2721 { 2080 /* lb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2722 { 2083 /* lbu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2723 { 2087 /* ld */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 }, 2724 { 2090 /* lh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2725 { 2093 /* lhu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2726 { 2100 /* lla */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2727 { 2104 /* lr.d */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2728 { 2109 /* lr.d.aq */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2729 { 2117 /* lr.d.aqrl */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2730 { 2127 /* lr.d.rl */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2731 { 2135 /* lr.w */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2732 { 2140 /* lr.w.aq */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2733 { 2148 /* lr.w.aqrl */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2734 { 2158 /* lr.w.rl */, 2 /* 1 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2735 { 2170 /* lw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2736 { 2173 /* lwu */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 }, 2737 { 2313 /* sb */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2738 { 2316 /* sc.d */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2739 { 2321 /* sc.d.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2740 { 2329 /* sc.d.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2741 { 2339 /* sc.d.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA_IsRV64 }, 2742 { 2347 /* sc.w */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2743 { 2352 /* sc.w.aq */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2744 { 2360 /* sc.w.aqrl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2745 { 2370 /* sc.w.rl */, 4 /* 2 */, MCK_AtomicMemOpOperand, AMFBS_HasStdExtA }, 2746 { 2378 /* sd */, 2 /* 1 */, MCK_BareSymbol, AMFBS_IsRV64 }, 2747 { 2418 /* sh */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2748 { 2525 /* sw */, 2 /* 1 */, MCK_BareSymbol, AMFBS_None }, 2749 { 2528 /* tail */, 1 /* 0 */, MCK_CallSymbol, AMFBS_None }, 2750}; 2751 2752OperandMatchResultTy RISCVAsmParser:: 2753tryCustomParseOperand(OperandVector &Operands, 2754 unsigned MCK) { 2755 2756 switch(MCK) { 2757 case MCK_AtomicMemOpOperand: 2758 return parseAtomicMemOp(Operands); 2759 case MCK_BareSymbol: 2760 return parseBareSymbol(Operands); 2761 case MCK_CSRSystemRegister: 2762 return parseCSRSystemRegister(Operands); 2763 case MCK_CallSymbol: 2764 return parseCallSymbol(Operands); 2765 case MCK_SImm21Lsb0JAL: 2766 return parseJALOffset(Operands); 2767 case MCK_TPRelAddSymbol: 2768 return parseOperandWithModifier(Operands); 2769 default: 2770 return MatchOperand_NoMatch; 2771 } 2772 return MatchOperand_NoMatch; 2773} 2774 2775OperandMatchResultTy RISCVAsmParser:: 2776MatchOperandParserImpl(OperandVector &Operands, 2777 StringRef Mnemonic, 2778 bool ParseForAllFeatures) { 2779 // Get the current feature set. 2780 const FeatureBitset &AvailableFeatures = getAvailableFeatures(); 2781 2782 // Get the next operand index. 2783 unsigned NextOpNum = Operands.size() - 1; 2784 // Search the table. 2785 auto MnemonicRange = 2786 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), 2787 Mnemonic, LessOpcodeOperand()); 2788 2789 if (MnemonicRange.first == MnemonicRange.second) 2790 return MatchOperand_NoMatch; 2791 2792 for (const OperandMatchEntry *it = MnemonicRange.first, 2793 *ie = MnemonicRange.second; it != ie; ++it) { 2794 // equal_range guarantees that instruction mnemonic matches. 2795 assert(Mnemonic == it->getMnemonic()); 2796 2797 // check if the available features match 2798 const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; 2799 if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures) 2800 continue; 2801 2802 // check if the operand in question has a custom parser. 2803 if (!(it->OperandMask & (1 << NextOpNum))) 2804 continue; 2805 2806 // call custom parse method to handle the operand 2807 OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class); 2808 if (Result != MatchOperand_NoMatch) 2809 return Result; 2810 } 2811 2812 // Okay, we had no match. 2813 return MatchOperand_NoMatch; 2814} 2815 2816#endif // GET_MATCHER_IMPLEMENTATION 2817 2818 2819#ifdef GET_MNEMONIC_SPELL_CHECKER 2820#undef GET_MNEMONIC_SPELL_CHECKER 2821 2822static std::string RISCVMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) { 2823 const unsigned MaxEditDist = 2; 2824 std::vector<StringRef> Candidates; 2825 StringRef Prev = ""; 2826 2827 // Find the appropriate table for this asm variant. 2828 const MatchEntry *Start, *End; 2829 switch (VariantID) { 2830 default: llvm_unreachable("invalid variant!"); 2831 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 2832 } 2833 2834 for (auto I = Start; I < End; I++) { 2835 // Ignore unsupported instructions. 2836 const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx]; 2837 if ((FBS & RequiredFeatures) != RequiredFeatures) 2838 continue; 2839 2840 StringRef T = I->getMnemonic(); 2841 // Avoid recomputing the edit distance for the same string. 2842 if (T.equals(Prev)) 2843 continue; 2844 2845 Prev = T; 2846 unsigned Dist = S.edit_distance(T, false, MaxEditDist); 2847 if (Dist <= MaxEditDist) 2848 Candidates.push_back(T); 2849 } 2850 2851 if (Candidates.empty()) 2852 return ""; 2853 2854 std::string Res = ", did you mean: "; 2855 unsigned i = 0; 2856 for( ; i < Candidates.size() - 1; i++) 2857 Res += Candidates[i].str() + ", "; 2858 return Res + Candidates[i].str() + "?"; 2859} 2860 2861#endif // GET_MNEMONIC_SPELL_CHECKER 2862