1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Compress instruction Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GEN_COMPRESS_INSTR 11#undef GEN_COMPRESS_INSTR 12 13static bool RISCVValidateMCOperand(const MCOperand &MCOp, 14 const MCSubtargetInfo &STI, 15 unsigned PredicateIndex) { 16 switch (PredicateIndex) { 17 default: 18 llvm_unreachable("Unknown MCOperandPredicate kind"); 19 break; 20 case 1: { 21 // uimm10_lsb00nonzero 22 23 int64_t Imm; 24 if (!MCOp.evaluateAsConstantImm(Imm)) 25 return false; 26 return isShiftedUInt<8, 2>(Imm) && (Imm != 0); 27 28 } 29 case 2: { 30 // simm6nonzero 31 32 int64_t Imm; 33 if (MCOp.evaluateAsConstantImm(Imm)) 34 return (Imm != 0) && isInt<6>(Imm); 35 return MCOp.isBareSymbolRef(); 36 37 } 38 case 3: { 39 // simm6 40 41 int64_t Imm; 42 if (MCOp.evaluateAsConstantImm(Imm)) 43 return isInt<6>(Imm); 44 return MCOp.isBareSymbolRef(); 45 46 } 47 case 4: { 48 // simm10_lsb0000nonzero 49 50 int64_t Imm; 51 if (!MCOp.evaluateAsConstantImm(Imm)) 52 return false; 53 return isShiftedInt<6, 4>(Imm) && (Imm != 0); 54 55 } 56 case 5: { 57 // simm9_lsb0 58 59 int64_t Imm; 60 if (MCOp.evaluateAsConstantImm(Imm)) 61 return isShiftedInt<8, 1>(Imm); 62 return MCOp.isBareSymbolRef(); 63 64 65 } 66 case 6: { 67 // uimm8_lsb000 68 69 int64_t Imm; 70 if (!MCOp.evaluateAsConstantImm(Imm)) 71 return false; 72 return isShiftedUInt<5, 3>(Imm); 73 74 } 75 case 7: { 76 // uimm9_lsb000 77 78 int64_t Imm; 79 if (!MCOp.evaluateAsConstantImm(Imm)) 80 return false; 81 return isShiftedUInt<6, 3>(Imm); 82 83 } 84 case 8: { 85 // uimm7_lsb00 86 87 int64_t Imm; 88 if (!MCOp.evaluateAsConstantImm(Imm)) 89 return false; 90 return isShiftedUInt<5, 2>(Imm); 91 92 } 93 case 9: { 94 // uimm8_lsb00 95 96 int64_t Imm; 97 if (!MCOp.evaluateAsConstantImm(Imm)) 98 return false; 99 return isShiftedUInt<6, 2>(Imm); 100 101 } 102 case 10: { 103 // simm12_lsb0 104 105 int64_t Imm; 106 if (MCOp.evaluateAsConstantImm(Imm)) 107 return isShiftedInt<11, 1>(Imm); 108 return MCOp.isBareSymbolRef(); 109 110 } 111 case 11: { 112 // c_lui_imm 113 114 int64_t Imm; 115 if (MCOp.evaluateAsConstantImm(Imm)) 116 return (Imm != 0) && (isUInt<5>(Imm) || 117 (Imm >= 0xfffe0 && Imm <= 0xfffff)); 118 return MCOp.isBareSymbolRef(); 119 120 } 121 case 12: { 122 // uimmlog2xlennonzero 123 124 int64_t Imm; 125 if (!MCOp.evaluateAsConstantImm(Imm)) 126 return false; 127 if (STI.getTargetTriple().isArch64Bit()) 128 return isUInt<6>(Imm) && (Imm != 0); 129 return isUInt<5>(Imm) && (Imm != 0); 130 131 } 132 } 133} 134 135static bool compressInst(MCInst& OutInst, 136 const MCInst &MI, 137 const MCSubtargetInfo &STI, 138 MCContext &Context) { 139 const MCRegisterInfo &MRI = *Context.getRegisterInfo(); 140 switch (MI.getOpcode()) { 141 default: return false; 142 case RISCV::ADD: { 143 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 144 (MI.getOperand(1).getReg() == RISCV::X0) && 145 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 146 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) { 147 // c.mv $rs1, $rs2 148 OutInst.setOpcode(RISCV::C_MV); 149 // Operand: rs1 150 OutInst.addOperand(MI.getOperand(0)); 151 // Operand: rs2 152 OutInst.addOperand(MI.getOperand(2)); 153 OutInst.setLoc(MI.getLoc()); 154 return true; 155 } // if 156 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 157 (MI.getOperand(2).getReg() == RISCV::X0) && 158 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 159 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 160 // c.mv $rs1, $rs2 161 OutInst.setOpcode(RISCV::C_MV); 162 // Operand: rs1 163 OutInst.addOperand(MI.getOperand(0)); 164 // Operand: rs2 165 OutInst.addOperand(MI.getOperand(1)); 166 OutInst.setLoc(MI.getLoc()); 167 return true; 168 } // if 169 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 170 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 171 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) && 172 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) { 173 // c.add $rs1, $rs2 174 OutInst.setOpcode(RISCV::C_ADD); 175 // Operand: rs1_wb 176 OutInst.addOperand(MI.getOperand(1)); 177 // Operand: rs1 178 OutInst.addOperand(MI.getOperand(1)); 179 // Operand: rs2 180 OutInst.addOperand(MI.getOperand(2)); 181 OutInst.setLoc(MI.getLoc()); 182 return true; 183 } // if 184 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 185 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 186 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg())) && 187 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 188 // c.add $rs1, $rs2 189 OutInst.setOpcode(RISCV::C_ADD); 190 // Operand: rs1_wb 191 OutInst.addOperand(MI.getOperand(2)); 192 // Operand: rs1 193 OutInst.addOperand(MI.getOperand(2)); 194 // Operand: rs2 195 OutInst.addOperand(MI.getOperand(1)); 196 OutInst.setLoc(MI.getLoc()); 197 return true; 198 } // if 199 break; 200 } // case ADD 201 case RISCV::ADDI: { 202 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 203 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 204 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 205 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 206 // c.addi4spn $rd, $rs1, $imm 207 OutInst.setOpcode(RISCV::C_ADDI4SPN); 208 // Operand: rd 209 OutInst.addOperand(MI.getOperand(0)); 210 // Operand: rs1 211 OutInst.addOperand(MI.getOperand(1)); 212 // Operand: imm 213 OutInst.addOperand(MI.getOperand(2)); 214 OutInst.setLoc(MI.getLoc()); 215 return true; 216 } // if 217 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 218 (MI.getOperand(0).getReg() == RISCV::X0) && 219 (MI.getOperand(1).getReg() == RISCV::X0) && 220 (MI.getOperand(2).isImm()) && 221 (MI.getOperand(2).getImm() == 0)) { 222 // c.nop 223 OutInst.setOpcode(RISCV::C_NOP); 224 OutInst.setLoc(MI.getLoc()); 225 return true; 226 } // if 227 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 228 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 229 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) && 230 RISCVValidateMCOperand(MI.getOperand(2), STI, 2)) { 231 // c.addi $rd, $imm 232 OutInst.setOpcode(RISCV::C_ADDI); 233 // Operand: rd_wb 234 OutInst.addOperand(MI.getOperand(1)); 235 // Operand: rd 236 OutInst.addOperand(MI.getOperand(1)); 237 // Operand: imm 238 OutInst.addOperand(MI.getOperand(2)); 239 OutInst.setLoc(MI.getLoc()); 240 return true; 241 } // if 242 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 243 (MI.getOperand(1).getReg() == RISCV::X0) && 244 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 245 RISCVValidateMCOperand(MI.getOperand(2), STI, 3)) { 246 // c.li $rd, $imm 247 OutInst.setOpcode(RISCV::C_LI); 248 // Operand: rd 249 OutInst.addOperand(MI.getOperand(0)); 250 // Operand: imm 251 OutInst.addOperand(MI.getOperand(2)); 252 OutInst.setLoc(MI.getLoc()); 253 return true; 254 } // if 255 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 256 (MI.getOperand(0).getReg() == RISCV::X2) && 257 (MI.getOperand(1).getReg() == RISCV::X2) && 258 RISCVValidateMCOperand(MI.getOperand(2), STI, 4)) { 259 // c.addi16sp $rd, $imm 260 OutInst.setOpcode(RISCV::C_ADDI16SP); 261 // Operand: rd_wb 262 OutInst.addOperand(MCOperand::createReg(RISCV::X2)); 263 // Operand: rd 264 OutInst.addOperand(MCOperand::createReg(RISCV::X2)); 265 // Operand: imm 266 OutInst.addOperand(MI.getOperand(2)); 267 OutInst.setLoc(MI.getLoc()); 268 return true; 269 } // if 270 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 271 (MI.getOperand(2).isImm()) && 272 (MI.getOperand(2).getImm() == 0) && 273 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 274 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 275 // c.mv $rs1, $rs2 276 OutInst.setOpcode(RISCV::C_MV); 277 // Operand: rs1 278 OutInst.addOperand(MI.getOperand(0)); 279 // Operand: rs2 280 OutInst.addOperand(MI.getOperand(1)); 281 OutInst.setLoc(MI.getLoc()); 282 return true; 283 } // if 284 break; 285 } // case ADDI 286 case RISCV::ADDIW: { 287 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 288 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 289 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 290 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) && 291 RISCVValidateMCOperand(MI.getOperand(2), STI, 3)) { 292 // c.addiw $rd, $imm 293 OutInst.setOpcode(RISCV::C_ADDIW); 294 // Operand: rd_wb 295 OutInst.addOperand(MI.getOperand(1)); 296 // Operand: rd 297 OutInst.addOperand(MI.getOperand(1)); 298 // Operand: imm 299 OutInst.addOperand(MI.getOperand(2)); 300 OutInst.setLoc(MI.getLoc()); 301 return true; 302 } // if 303 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 304 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 305 (MI.getOperand(1).getReg() == RISCV::X0) && 306 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 307 RISCVValidateMCOperand(MI.getOperand(2), STI, 3)) { 308 // c.li $rd, $imm 309 OutInst.setOpcode(RISCV::C_LI); 310 // Operand: rd 311 OutInst.addOperand(MI.getOperand(0)); 312 // Operand: imm 313 OutInst.addOperand(MI.getOperand(2)); 314 OutInst.setLoc(MI.getLoc()); 315 return true; 316 } // if 317 break; 318 } // case ADDIW 319 case RISCV::ADDW: { 320 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 321 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 322 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 323 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 324 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 325 // c.addw $rd, $rs2 326 OutInst.setOpcode(RISCV::C_ADDW); 327 // Operand: rd_wb 328 OutInst.addOperand(MI.getOperand(1)); 329 // Operand: rd 330 OutInst.addOperand(MI.getOperand(1)); 331 // Operand: rs2 332 OutInst.addOperand(MI.getOperand(2)); 333 OutInst.setLoc(MI.getLoc()); 334 return true; 335 } // if 336 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 337 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 338 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 339 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 340 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 341 // c.addw $rd, $rs2 342 OutInst.setOpcode(RISCV::C_ADDW); 343 // Operand: rd_wb 344 OutInst.addOperand(MI.getOperand(2)); 345 // Operand: rd 346 OutInst.addOperand(MI.getOperand(2)); 347 // Operand: rs2 348 OutInst.addOperand(MI.getOperand(1)); 349 OutInst.setLoc(MI.getLoc()); 350 return true; 351 } // if 352 break; 353 } // case ADDW 354 case RISCV::AND: { 355 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 356 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 357 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 358 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 359 // c.and $rd, $rs2 360 OutInst.setOpcode(RISCV::C_AND); 361 // Operand: rd_wb 362 OutInst.addOperand(MI.getOperand(1)); 363 // Operand: rd 364 OutInst.addOperand(MI.getOperand(1)); 365 // Operand: rs2 366 OutInst.addOperand(MI.getOperand(2)); 367 OutInst.setLoc(MI.getLoc()); 368 return true; 369 } // if 370 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 371 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 372 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 373 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 374 // c.and $rd, $rs2 375 OutInst.setOpcode(RISCV::C_AND); 376 // Operand: rd_wb 377 OutInst.addOperand(MI.getOperand(2)); 378 // Operand: rd 379 OutInst.addOperand(MI.getOperand(2)); 380 // Operand: rs2 381 OutInst.addOperand(MI.getOperand(1)); 382 OutInst.setLoc(MI.getLoc()); 383 return true; 384 } // if 385 break; 386 } // case AND 387 case RISCV::ANDI: { 388 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 389 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 390 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 391 RISCVValidateMCOperand(MI.getOperand(2), STI, 3)) { 392 // c.andi $rs1, $imm 393 OutInst.setOpcode(RISCV::C_ANDI); 394 // Operand: rs1_wb 395 OutInst.addOperand(MI.getOperand(1)); 396 // Operand: rs1 397 OutInst.addOperand(MI.getOperand(1)); 398 // Operand: imm 399 OutInst.addOperand(MI.getOperand(2)); 400 OutInst.setLoc(MI.getLoc()); 401 return true; 402 } // if 403 break; 404 } // case ANDI 405 case RISCV::BEQ: { 406 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 407 (MI.getOperand(1).getReg() == RISCV::X0) && 408 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 409 RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) { 410 // c.beqz $rs1, $imm 411 OutInst.setOpcode(RISCV::C_BEQZ); 412 // Operand: rs1 413 OutInst.addOperand(MI.getOperand(0)); 414 // Operand: imm 415 OutInst.addOperand(MI.getOperand(2)); 416 OutInst.setLoc(MI.getLoc()); 417 return true; 418 } // if 419 break; 420 } // case BEQ 421 case RISCV::BNE: { 422 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 423 (MI.getOperand(1).getReg() == RISCV::X0) && 424 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 425 RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) { 426 // c.bnez $rs1, $imm 427 OutInst.setOpcode(RISCV::C_BNEZ); 428 // Operand: rs1 429 OutInst.addOperand(MI.getOperand(0)); 430 // Operand: imm 431 OutInst.addOperand(MI.getOperand(2)); 432 OutInst.setLoc(MI.getLoc()); 433 return true; 434 } // if 435 break; 436 } // case BNE 437 case RISCV::EBREAK: { 438 if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) { 439 // c.ebreak 440 OutInst.setOpcode(RISCV::C_EBREAK); 441 OutInst.setLoc(MI.getLoc()); 442 return true; 443 } // if 444 break; 445 } // case EBREAK 446 case RISCV::FLD: { 447 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 448 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 449 (MRI.getRegClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg())) && 450 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 451 RISCVValidateMCOperand(MI.getOperand(2), STI, 6)) { 452 // c.fld $rd, ${imm}(${rs1}) 453 OutInst.setOpcode(RISCV::C_FLD); 454 // Operand: rd 455 OutInst.addOperand(MI.getOperand(0)); 456 // Operand: rs1 457 OutInst.addOperand(MI.getOperand(1)); 458 // Operand: imm 459 OutInst.addOperand(MI.getOperand(2)); 460 OutInst.setLoc(MI.getLoc()); 461 return true; 462 } // if 463 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 464 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 465 (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) && 466 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 467 RISCVValidateMCOperand(MI.getOperand(2), STI, 7)) { 468 // c.fldsp $rd, ${imm}(${rs1}) 469 OutInst.setOpcode(RISCV::C_FLDSP); 470 // Operand: rd 471 OutInst.addOperand(MI.getOperand(0)); 472 // Operand: rs1 473 OutInst.addOperand(MI.getOperand(1)); 474 // Operand: imm 475 OutInst.addOperand(MI.getOperand(2)); 476 OutInst.setLoc(MI.getLoc()); 477 return true; 478 } // if 479 break; 480 } // case FLD 481 case RISCV::FLW: { 482 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 483 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 484 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 485 (MRI.getRegClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg())) && 486 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 487 RISCVValidateMCOperand(MI.getOperand(2), STI, 8)) { 488 // c.flw $rd, ${imm}(${rs1}) 489 OutInst.setOpcode(RISCV::C_FLW); 490 // Operand: rd 491 OutInst.addOperand(MI.getOperand(0)); 492 // Operand: rs1 493 OutInst.addOperand(MI.getOperand(1)); 494 // Operand: imm 495 OutInst.addOperand(MI.getOperand(2)); 496 OutInst.setLoc(MI.getLoc()); 497 return true; 498 } // if 499 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 500 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 501 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 502 (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) && 503 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 504 RISCVValidateMCOperand(MI.getOperand(2), STI, 9)) { 505 // c.flwsp $rd, ${imm}(${rs1}) 506 OutInst.setOpcode(RISCV::C_FLWSP); 507 // Operand: rd 508 OutInst.addOperand(MI.getOperand(0)); 509 // Operand: rs1 510 OutInst.addOperand(MI.getOperand(1)); 511 // Operand: imm 512 OutInst.addOperand(MI.getOperand(2)); 513 OutInst.setLoc(MI.getLoc()); 514 return true; 515 } // if 516 break; 517 } // case FLW 518 case RISCV::FSD: { 519 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 520 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 521 (MRI.getRegClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg())) && 522 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 523 RISCVValidateMCOperand(MI.getOperand(2), STI, 6)) { 524 // c.fsd $rs2, ${imm}(${rs1}) 525 OutInst.setOpcode(RISCV::C_FSD); 526 // Operand: rs2 527 OutInst.addOperand(MI.getOperand(0)); 528 // Operand: rs1 529 OutInst.addOperand(MI.getOperand(1)); 530 // Operand: imm 531 OutInst.addOperand(MI.getOperand(2)); 532 OutInst.setLoc(MI.getLoc()); 533 return true; 534 } // if 535 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 536 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 537 (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) && 538 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 539 RISCVValidateMCOperand(MI.getOperand(2), STI, 7)) { 540 // c.fsdsp $rs2, ${imm}(${rs1}) 541 OutInst.setOpcode(RISCV::C_FSDSP); 542 // Operand: rs2 543 OutInst.addOperand(MI.getOperand(0)); 544 // Operand: rs1 545 OutInst.addOperand(MI.getOperand(1)); 546 // Operand: imm 547 OutInst.addOperand(MI.getOperand(2)); 548 OutInst.setLoc(MI.getLoc()); 549 return true; 550 } // if 551 break; 552 } // case FSD 553 case RISCV::FSW: { 554 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 555 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 556 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 557 (MRI.getRegClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg())) && 558 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 559 RISCVValidateMCOperand(MI.getOperand(2), STI, 8)) { 560 // c.fsw $rs2, ${imm}(${rs1}) 561 OutInst.setOpcode(RISCV::C_FSW); 562 // Operand: rs2 563 OutInst.addOperand(MI.getOperand(0)); 564 // Operand: rs1 565 OutInst.addOperand(MI.getOperand(1)); 566 // Operand: imm 567 OutInst.addOperand(MI.getOperand(2)); 568 OutInst.setLoc(MI.getLoc()); 569 return true; 570 } // if 571 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 572 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 573 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 574 (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) && 575 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 576 RISCVValidateMCOperand(MI.getOperand(2), STI, 9)) { 577 // c.fswsp $rs2, ${imm}(${rs1}) 578 OutInst.setOpcode(RISCV::C_FSWSP); 579 // Operand: rs2 580 OutInst.addOperand(MI.getOperand(0)); 581 // Operand: rs1 582 OutInst.addOperand(MI.getOperand(1)); 583 // Operand: imm 584 OutInst.addOperand(MI.getOperand(2)); 585 OutInst.setLoc(MI.getLoc()); 586 return true; 587 } // if 588 break; 589 } // case FSW 590 case RISCV::JAL: { 591 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 592 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 593 (MI.getOperand(0).getReg() == RISCV::X1) && 594 RISCVValidateMCOperand(MI.getOperand(1), STI, 10)) { 595 // c.jal $offset 596 OutInst.setOpcode(RISCV::C_JAL); 597 // Operand: offset 598 OutInst.addOperand(MI.getOperand(1)); 599 OutInst.setLoc(MI.getLoc()); 600 return true; 601 } // if 602 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 603 (MI.getOperand(0).getReg() == RISCV::X0) && 604 RISCVValidateMCOperand(MI.getOperand(1), STI, 10)) { 605 // c.j $offset 606 OutInst.setOpcode(RISCV::C_J); 607 // Operand: offset 608 OutInst.addOperand(MI.getOperand(1)); 609 OutInst.setLoc(MI.getLoc()); 610 return true; 611 } // if 612 break; 613 } // case JAL 614 case RISCV::JALR: { 615 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 616 (MI.getOperand(0).getReg() == RISCV::X0) && 617 (MI.getOperand(2).isImm()) && 618 (MI.getOperand(2).getImm() == 0) && 619 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 620 // c.jr $rs1 621 OutInst.setOpcode(RISCV::C_JR); 622 // Operand: rs1 623 OutInst.addOperand(MI.getOperand(1)); 624 OutInst.setLoc(MI.getLoc()); 625 return true; 626 } // if 627 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 628 (MI.getOperand(0).getReg() == RISCV::X1) && 629 (MI.getOperand(2).isImm()) && 630 (MI.getOperand(2).getImm() == 0) && 631 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 632 // c.jalr $rs1 633 OutInst.setOpcode(RISCV::C_JALR); 634 // Operand: rs1 635 OutInst.addOperand(MI.getOperand(1)); 636 OutInst.setLoc(MI.getLoc()); 637 return true; 638 } // if 639 break; 640 } // case JALR 641 case RISCV::LD: { 642 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 643 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 644 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 645 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 646 RISCVValidateMCOperand(MI.getOperand(2), STI, 6)) { 647 // c.ld $rd, ${imm}(${rs1}) 648 OutInst.setOpcode(RISCV::C_LD); 649 // Operand: rd 650 OutInst.addOperand(MI.getOperand(0)); 651 // Operand: rs1 652 OutInst.addOperand(MI.getOperand(1)); 653 // Operand: imm 654 OutInst.addOperand(MI.getOperand(2)); 655 OutInst.setLoc(MI.getLoc()); 656 return true; 657 } // if 658 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 659 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 660 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 661 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 662 RISCVValidateMCOperand(MI.getOperand(2), STI, 7)) { 663 // c.ldsp $rd, ${imm}(${rs1}) 664 OutInst.setOpcode(RISCV::C_LDSP); 665 // Operand: rd 666 OutInst.addOperand(MI.getOperand(0)); 667 // Operand: rs1 668 OutInst.addOperand(MI.getOperand(1)); 669 // Operand: imm 670 OutInst.addOperand(MI.getOperand(2)); 671 OutInst.setLoc(MI.getLoc()); 672 return true; 673 } // if 674 break; 675 } // case LD 676 case RISCV::LUI: { 677 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 678 (MRI.getRegClass(RISCV::GPRNoX0X2RegClassID).contains(MI.getOperand(0).getReg())) && 679 RISCVValidateMCOperand(MI.getOperand(1), STI, 11)) { 680 // c.lui $rd, $imm 681 OutInst.setOpcode(RISCV::C_LUI); 682 // Operand: rd 683 OutInst.addOperand(MI.getOperand(0)); 684 // Operand: imm 685 OutInst.addOperand(MI.getOperand(1)); 686 OutInst.setLoc(MI.getLoc()); 687 return true; 688 } // if 689 break; 690 } // case LUI 691 case RISCV::LW: { 692 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 693 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 694 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 695 RISCVValidateMCOperand(MI.getOperand(2), STI, 8)) { 696 // c.lw $rd, ${imm}(${rs1}) 697 OutInst.setOpcode(RISCV::C_LW); 698 // Operand: rd 699 OutInst.addOperand(MI.getOperand(0)); 700 // Operand: rs1 701 OutInst.addOperand(MI.getOperand(1)); 702 // Operand: imm 703 OutInst.addOperand(MI.getOperand(2)); 704 OutInst.setLoc(MI.getLoc()); 705 return true; 706 } // if 707 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 708 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 709 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 710 RISCVValidateMCOperand(MI.getOperand(2), STI, 9)) { 711 // c.lwsp $rd, ${imm}(${rs1}) 712 OutInst.setOpcode(RISCV::C_LWSP); 713 // Operand: rd 714 OutInst.addOperand(MI.getOperand(0)); 715 // Operand: rs1 716 OutInst.addOperand(MI.getOperand(1)); 717 // Operand: imm 718 OutInst.addOperand(MI.getOperand(2)); 719 OutInst.setLoc(MI.getLoc()); 720 return true; 721 } // if 722 break; 723 } // case LW 724 case RISCV::OR: { 725 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 726 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 727 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 728 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 729 // c.or $rd, $rs2 730 OutInst.setOpcode(RISCV::C_OR); 731 // Operand: rd_wb 732 OutInst.addOperand(MI.getOperand(1)); 733 // Operand: rd 734 OutInst.addOperand(MI.getOperand(1)); 735 // Operand: rs2 736 OutInst.addOperand(MI.getOperand(2)); 737 OutInst.setLoc(MI.getLoc()); 738 return true; 739 } // if 740 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 741 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 742 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 743 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 744 // c.or $rd, $rs2 745 OutInst.setOpcode(RISCV::C_OR); 746 // Operand: rd_wb 747 OutInst.addOperand(MI.getOperand(2)); 748 // Operand: rd 749 OutInst.addOperand(MI.getOperand(2)); 750 // Operand: rs2 751 OutInst.addOperand(MI.getOperand(1)); 752 OutInst.setLoc(MI.getLoc()); 753 return true; 754 } // if 755 break; 756 } // case OR 757 case RISCV::SD: { 758 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 759 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 760 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 761 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 762 RISCVValidateMCOperand(MI.getOperand(2), STI, 6)) { 763 // c.sd $rs2, ${imm}(${rs1}) 764 OutInst.setOpcode(RISCV::C_SD); 765 // Operand: rs2 766 OutInst.addOperand(MI.getOperand(0)); 767 // Operand: rs1 768 OutInst.addOperand(MI.getOperand(1)); 769 // Operand: imm 770 OutInst.addOperand(MI.getOperand(2)); 771 OutInst.setLoc(MI.getLoc()); 772 return true; 773 } // if 774 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 775 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 776 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 777 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 778 RISCVValidateMCOperand(MI.getOperand(2), STI, 7)) { 779 // c.sdsp $rs2, ${imm}(${rs1}) 780 OutInst.setOpcode(RISCV::C_SDSP); 781 // Operand: rs2 782 OutInst.addOperand(MI.getOperand(0)); 783 // Operand: rs1 784 OutInst.addOperand(MI.getOperand(1)); 785 // Operand: imm 786 OutInst.addOperand(MI.getOperand(2)); 787 OutInst.setLoc(MI.getLoc()); 788 return true; 789 } // if 790 break; 791 } // case SD 792 case RISCV::SLLI: { 793 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 794 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 795 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) && 796 RISCVValidateMCOperand(MI.getOperand(2), STI, 12)) { 797 // c.slli $rd, $imm 798 OutInst.setOpcode(RISCV::C_SLLI); 799 // Operand: rd_wb 800 OutInst.addOperand(MI.getOperand(1)); 801 // Operand: rd 802 OutInst.addOperand(MI.getOperand(1)); 803 // Operand: imm 804 OutInst.addOperand(MI.getOperand(2)); 805 OutInst.setLoc(MI.getLoc()); 806 return true; 807 } // if 808 break; 809 } // case SLLI 810 case RISCV::SRAI: { 811 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 812 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 813 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 814 RISCVValidateMCOperand(MI.getOperand(2), STI, 12)) { 815 // c.srai $rs1, $imm 816 OutInst.setOpcode(RISCV::C_SRAI); 817 // Operand: rs1_wb 818 OutInst.addOperand(MI.getOperand(1)); 819 // Operand: rs1 820 OutInst.addOperand(MI.getOperand(1)); 821 // Operand: imm 822 OutInst.addOperand(MI.getOperand(2)); 823 OutInst.setLoc(MI.getLoc()); 824 return true; 825 } // if 826 break; 827 } // case SRAI 828 case RISCV::SRLI: { 829 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 830 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 831 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 832 RISCVValidateMCOperand(MI.getOperand(2), STI, 12)) { 833 // c.srli $rs1, $imm 834 OutInst.setOpcode(RISCV::C_SRLI); 835 // Operand: rs1_wb 836 OutInst.addOperand(MI.getOperand(1)); 837 // Operand: rs1 838 OutInst.addOperand(MI.getOperand(1)); 839 // Operand: imm 840 OutInst.addOperand(MI.getOperand(2)); 841 OutInst.setLoc(MI.getLoc()); 842 return true; 843 } // if 844 break; 845 } // case SRLI 846 case RISCV::SUB: { 847 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 848 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 849 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 850 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 851 // c.sub $rd, $rs2 852 OutInst.setOpcode(RISCV::C_SUB); 853 // Operand: rd_wb 854 OutInst.addOperand(MI.getOperand(1)); 855 // Operand: rd 856 OutInst.addOperand(MI.getOperand(1)); 857 // Operand: rs2 858 OutInst.addOperand(MI.getOperand(2)); 859 OutInst.setLoc(MI.getLoc()); 860 return true; 861 } // if 862 break; 863 } // case SUB 864 case RISCV::SUBW: { 865 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 866 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 867 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 868 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 869 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 870 // c.subw $rd, $rs2 871 OutInst.setOpcode(RISCV::C_SUBW); 872 // Operand: rd_wb 873 OutInst.addOperand(MI.getOperand(1)); 874 // Operand: rd 875 OutInst.addOperand(MI.getOperand(1)); 876 // Operand: rs2 877 OutInst.addOperand(MI.getOperand(2)); 878 OutInst.setLoc(MI.getLoc()); 879 return true; 880 } // if 881 break; 882 } // case SUBW 883 case RISCV::SW: { 884 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 885 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 886 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 887 RISCVValidateMCOperand(MI.getOperand(2), STI, 8)) { 888 // c.sw $rs2, ${imm}(${rs1}) 889 OutInst.setOpcode(RISCV::C_SW); 890 // Operand: rs2 891 OutInst.addOperand(MI.getOperand(0)); 892 // Operand: rs1 893 OutInst.addOperand(MI.getOperand(1)); 894 // Operand: imm 895 OutInst.addOperand(MI.getOperand(2)); 896 OutInst.setLoc(MI.getLoc()); 897 return true; 898 } // if 899 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 900 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 901 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 902 RISCVValidateMCOperand(MI.getOperand(2), STI, 9)) { 903 // c.swsp $rs2, ${imm}(${rs1}) 904 OutInst.setOpcode(RISCV::C_SWSP); 905 // Operand: rs2 906 OutInst.addOperand(MI.getOperand(0)); 907 // Operand: rs1 908 OutInst.addOperand(MI.getOperand(1)); 909 // Operand: imm 910 OutInst.addOperand(MI.getOperand(2)); 911 OutInst.setLoc(MI.getLoc()); 912 return true; 913 } // if 914 break; 915 } // case SW 916 case RISCV::UNIMP: { 917 if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) { 918 // c.unimp 919 OutInst.setOpcode(RISCV::C_UNIMP); 920 OutInst.setLoc(MI.getLoc()); 921 return true; 922 } // if 923 break; 924 } // case UNIMP 925 case RISCV::XOR: { 926 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 927 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 928 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 929 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 930 // c.xor $rd, $rs2 931 OutInst.setOpcode(RISCV::C_XOR); 932 // Operand: rd_wb 933 OutInst.addOperand(MI.getOperand(1)); 934 // Operand: rd 935 OutInst.addOperand(MI.getOperand(1)); 936 // Operand: rs2 937 OutInst.addOperand(MI.getOperand(2)); 938 OutInst.setLoc(MI.getLoc()); 939 return true; 940 } // if 941 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 942 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 943 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 944 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 945 // c.xor $rd, $rs2 946 OutInst.setOpcode(RISCV::C_XOR); 947 // Operand: rd_wb 948 OutInst.addOperand(MI.getOperand(2)); 949 // Operand: rd 950 OutInst.addOperand(MI.getOperand(2)); 951 // Operand: rs2 952 OutInst.addOperand(MI.getOperand(1)); 953 OutInst.setLoc(MI.getLoc()); 954 return true; 955 } // if 956 957 } // case XOR 958 } // switch 959 return false; 960} 961 962#endif //GEN_COMPRESS_INSTR 963 964#ifdef GEN_UNCOMPRESS_INSTR 965#undef GEN_UNCOMPRESS_INSTR 966 967static bool RISCVValidateMCOperand(const MCOperand &MCOp, 968 const MCSubtargetInfo &STI, 969 unsigned PredicateIndex) { 970 switch (PredicateIndex) { 971 default: 972 llvm_unreachable("Unknown MCOperandPredicate kind"); 973 break; 974 case 1: { 975 // simm12 976 977 int64_t Imm; 978 if (MCOp.evaluateAsConstantImm(Imm)) 979 return isInt<12>(Imm); 980 return MCOp.isBareSymbolRef(); 981 982 } 983 case 2: { 984 // simm13_lsb0 985 986 int64_t Imm; 987 if (MCOp.evaluateAsConstantImm(Imm)) 988 return isShiftedInt<12, 1>(Imm); 989 return MCOp.isBareSymbolRef(); 990 991 } 992 case 3: { 993 // simm21_lsb0_jal 994 995 int64_t Imm; 996 if (MCOp.evaluateAsConstantImm(Imm)) 997 return isShiftedInt<20, 1>(Imm); 998 return MCOp.isBareSymbolRef(); 999 1000 } 1001 case 4: { 1002 // uimm20_lui 1003 1004 int64_t Imm; 1005 if (MCOp.evaluateAsConstantImm(Imm)) 1006 return isUInt<20>(Imm); 1007 return MCOp.isBareSymbolRef(); 1008 1009 } 1010 case 5: { 1011 // uimmlog2xlen 1012 1013 int64_t Imm; 1014 if (!MCOp.evaluateAsConstantImm(Imm)) 1015 return false; 1016 if (STI.getTargetTriple().isArch64Bit()) 1017 return isUInt<6>(Imm); 1018 return isUInt<5>(Imm); 1019 1020 } 1021 } 1022} 1023 1024static bool uncompressInst(MCInst& OutInst, 1025 const MCInst &MI, 1026 const MCRegisterInfo &MRI, 1027 const MCSubtargetInfo &STI) { 1028 switch (MI.getOpcode()) { 1029 default: return false; 1030 case RISCV::C_ADD: { 1031 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1032 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1033 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1034 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) { 1035 // add $rd, $rs1, $rs2 1036 OutInst.setOpcode(RISCV::ADD); 1037 // Operand: rd 1038 OutInst.addOperand(MI.getOperand(0)); 1039 // Operand: rs1 1040 OutInst.addOperand(MI.getOperand(0)); 1041 // Operand: rs2 1042 OutInst.addOperand(MI.getOperand(2)); 1043 OutInst.setLoc(MI.getLoc()); 1044 return true; 1045 } // if 1046 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1047 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1048 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) && 1049 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) { 1050 // add $rd, $rs1, $rs2 1051 OutInst.setOpcode(RISCV::ADD); 1052 // Operand: rd 1053 OutInst.addOperand(MI.getOperand(0)); 1054 // Operand: rs1 1055 OutInst.addOperand(MI.getOperand(2)); 1056 // Operand: rs2 1057 OutInst.addOperand(MI.getOperand(0)); 1058 OutInst.setLoc(MI.getLoc()); 1059 return true; 1060 } // if 1061 break; 1062 } // case C_ADD 1063 case RISCV::C_ADDI: { 1064 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1065 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1066 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1067 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1068 // addi $rd, $rs1, $imm12 1069 OutInst.setOpcode(RISCV::ADDI); 1070 // Operand: rd 1071 OutInst.addOperand(MI.getOperand(0)); 1072 // Operand: rs1 1073 OutInst.addOperand(MI.getOperand(0)); 1074 // Operand: imm12 1075 OutInst.addOperand(MI.getOperand(2)); 1076 OutInst.setLoc(MI.getLoc()); 1077 return true; 1078 } // if 1079 break; 1080 } // case C_ADDI 1081 case RISCV::C_ADDI16SP: { 1082 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1083 (MI.getOperand(0).getReg() == RISCV::X2) && 1084 (MI.getOperand(1).getReg() == RISCV::X2) && 1085 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1086 // addi $rd, $rs1, $imm12 1087 OutInst.setOpcode(RISCV::ADDI); 1088 // Operand: rd 1089 OutInst.addOperand(MCOperand::createReg(RISCV::X2)); 1090 // Operand: rs1 1091 OutInst.addOperand(MCOperand::createReg(RISCV::X2)); 1092 // Operand: imm12 1093 OutInst.addOperand(MI.getOperand(2)); 1094 OutInst.setLoc(MI.getLoc()); 1095 return true; 1096 } // if 1097 break; 1098 } // case C_ADDI16SP 1099 case RISCV::C_ADDI4SPN: { 1100 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1101 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1102 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1103 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1104 // addi $rd, $rs1, $imm12 1105 OutInst.setOpcode(RISCV::ADDI); 1106 // Operand: rd 1107 OutInst.addOperand(MI.getOperand(0)); 1108 // Operand: rs1 1109 OutInst.addOperand(MI.getOperand(1)); 1110 // Operand: imm12 1111 OutInst.addOperand(MI.getOperand(2)); 1112 OutInst.setLoc(MI.getLoc()); 1113 return true; 1114 } // if 1115 break; 1116 } // case C_ADDI4SPN 1117 case RISCV::C_ADDIW: { 1118 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1119 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1120 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1121 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1122 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1123 // addiw $rd, $rs1, $imm12 1124 OutInst.setOpcode(RISCV::ADDIW); 1125 // Operand: rd 1126 OutInst.addOperand(MI.getOperand(0)); 1127 // Operand: rs1 1128 OutInst.addOperand(MI.getOperand(0)); 1129 // Operand: imm12 1130 OutInst.addOperand(MI.getOperand(2)); 1131 OutInst.setLoc(MI.getLoc()); 1132 return true; 1133 } // if 1134 break; 1135 } // case C_ADDIW 1136 case RISCV::C_ADDW: { 1137 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1138 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1139 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1140 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1141 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) { 1142 // addw $rd, $rs1, $rs2 1143 OutInst.setOpcode(RISCV::ADDW); 1144 // Operand: rd 1145 OutInst.addOperand(MI.getOperand(0)); 1146 // Operand: rs1 1147 OutInst.addOperand(MI.getOperand(0)); 1148 // Operand: rs2 1149 OutInst.addOperand(MI.getOperand(2)); 1150 OutInst.setLoc(MI.getLoc()); 1151 return true; 1152 } // if 1153 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1154 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1155 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1156 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) && 1157 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) { 1158 // addw $rd, $rs1, $rs2 1159 OutInst.setOpcode(RISCV::ADDW); 1160 // Operand: rd 1161 OutInst.addOperand(MI.getOperand(0)); 1162 // Operand: rs1 1163 OutInst.addOperand(MI.getOperand(2)); 1164 // Operand: rs2 1165 OutInst.addOperand(MI.getOperand(0)); 1166 OutInst.setLoc(MI.getLoc()); 1167 return true; 1168 } // if 1169 break; 1170 } // case C_ADDW 1171 case RISCV::C_AND: { 1172 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1173 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1174 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1175 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) { 1176 // and $rd, $rs1, $rs2 1177 OutInst.setOpcode(RISCV::AND); 1178 // Operand: rd 1179 OutInst.addOperand(MI.getOperand(0)); 1180 // Operand: rs1 1181 OutInst.addOperand(MI.getOperand(0)); 1182 // Operand: rs2 1183 OutInst.addOperand(MI.getOperand(2)); 1184 OutInst.setLoc(MI.getLoc()); 1185 return true; 1186 } // if 1187 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1188 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1189 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) && 1190 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) { 1191 // and $rd, $rs1, $rs2 1192 OutInst.setOpcode(RISCV::AND); 1193 // Operand: rd 1194 OutInst.addOperand(MI.getOperand(0)); 1195 // Operand: rs1 1196 OutInst.addOperand(MI.getOperand(2)); 1197 // Operand: rs2 1198 OutInst.addOperand(MI.getOperand(0)); 1199 OutInst.setLoc(MI.getLoc()); 1200 return true; 1201 } // if 1202 break; 1203 } // case C_AND 1204 case RISCV::C_ANDI: { 1205 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1206 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1207 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1208 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1209 // andi $rd, $rs1, $imm12 1210 OutInst.setOpcode(RISCV::ANDI); 1211 // Operand: rd 1212 OutInst.addOperand(MI.getOperand(0)); 1213 // Operand: rs1 1214 OutInst.addOperand(MI.getOperand(0)); 1215 // Operand: imm12 1216 OutInst.addOperand(MI.getOperand(2)); 1217 OutInst.setLoc(MI.getLoc()); 1218 return true; 1219 } // if 1220 break; 1221 } // case C_ANDI 1222 case RISCV::C_BEQZ: { 1223 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1224 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1225 RISCVValidateMCOperand(MI.getOperand(1), STI, 2)) { 1226 // beq $rs1, $rs2, $imm12 1227 OutInst.setOpcode(RISCV::BEQ); 1228 // Operand: rs1 1229 OutInst.addOperand(MI.getOperand(0)); 1230 // Operand: rs2 1231 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1232 // Operand: imm12 1233 OutInst.addOperand(MI.getOperand(1)); 1234 OutInst.setLoc(MI.getLoc()); 1235 return true; 1236 } // if 1237 break; 1238 } // case C_BEQZ 1239 case RISCV::C_BNEZ: { 1240 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1241 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1242 RISCVValidateMCOperand(MI.getOperand(1), STI, 2)) { 1243 // bne $rs1, $rs2, $imm12 1244 OutInst.setOpcode(RISCV::BNE); 1245 // Operand: rs1 1246 OutInst.addOperand(MI.getOperand(0)); 1247 // Operand: rs2 1248 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1249 // Operand: imm12 1250 OutInst.addOperand(MI.getOperand(1)); 1251 OutInst.setLoc(MI.getLoc()); 1252 return true; 1253 } // if 1254 break; 1255 } // case C_BNEZ 1256 case RISCV::C_EBREAK: { 1257 if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) { 1258 // ebreak 1259 OutInst.setOpcode(RISCV::EBREAK); 1260 OutInst.setLoc(MI.getLoc()); 1261 return true; 1262 } // if 1263 break; 1264 } // case C_EBREAK 1265 case RISCV::C_FLD: { 1266 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1267 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 1268 (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) && 1269 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1270 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1271 // fld $rd, ${imm12}(${rs1}) 1272 OutInst.setOpcode(RISCV::FLD); 1273 // Operand: rd 1274 OutInst.addOperand(MI.getOperand(0)); 1275 // Operand: rs1 1276 OutInst.addOperand(MI.getOperand(1)); 1277 // Operand: imm12 1278 OutInst.addOperand(MI.getOperand(2)); 1279 OutInst.setLoc(MI.getLoc()); 1280 return true; 1281 } // if 1282 break; 1283 } // case C_FLD 1284 case RISCV::C_FLDSP: { 1285 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1286 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 1287 (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) && 1288 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1289 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1290 // fld $rd, ${imm12}(${rs1}) 1291 OutInst.setOpcode(RISCV::FLD); 1292 // Operand: rd 1293 OutInst.addOperand(MI.getOperand(0)); 1294 // Operand: rs1 1295 OutInst.addOperand(MI.getOperand(1)); 1296 // Operand: imm12 1297 OutInst.addOperand(MI.getOperand(2)); 1298 OutInst.setLoc(MI.getLoc()); 1299 return true; 1300 } // if 1301 break; 1302 } // case C_FLDSP 1303 case RISCV::C_FLW: { 1304 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 1305 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1306 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 1307 (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) && 1308 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1309 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1310 // flw $rd, ${imm12}(${rs1}) 1311 OutInst.setOpcode(RISCV::FLW); 1312 // Operand: rd 1313 OutInst.addOperand(MI.getOperand(0)); 1314 // Operand: rs1 1315 OutInst.addOperand(MI.getOperand(1)); 1316 // Operand: imm12 1317 OutInst.addOperand(MI.getOperand(2)); 1318 OutInst.setLoc(MI.getLoc()); 1319 return true; 1320 } // if 1321 break; 1322 } // case C_FLW 1323 case RISCV::C_FLWSP: { 1324 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 1325 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1326 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 1327 (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) && 1328 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1329 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1330 // flw $rd, ${imm12}(${rs1}) 1331 OutInst.setOpcode(RISCV::FLW); 1332 // Operand: rd 1333 OutInst.addOperand(MI.getOperand(0)); 1334 // Operand: rs1 1335 OutInst.addOperand(MI.getOperand(1)); 1336 // Operand: imm12 1337 OutInst.addOperand(MI.getOperand(2)); 1338 OutInst.setLoc(MI.getLoc()); 1339 return true; 1340 } // if 1341 break; 1342 } // case C_FLWSP 1343 case RISCV::C_FSD: { 1344 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1345 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 1346 (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) && 1347 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1348 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1349 // fsd $rs2, ${imm12}(${rs1}) 1350 OutInst.setOpcode(RISCV::FSD); 1351 // Operand: rs2 1352 OutInst.addOperand(MI.getOperand(0)); 1353 // Operand: rs1 1354 OutInst.addOperand(MI.getOperand(1)); 1355 // Operand: imm12 1356 OutInst.addOperand(MI.getOperand(2)); 1357 OutInst.setLoc(MI.getLoc()); 1358 return true; 1359 } // if 1360 break; 1361 } // case C_FSD 1362 case RISCV::C_FSDSP: { 1363 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1364 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 1365 (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) && 1366 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1367 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1368 // fsd $rs2, ${imm12}(${rs1}) 1369 OutInst.setOpcode(RISCV::FSD); 1370 // Operand: rs2 1371 OutInst.addOperand(MI.getOperand(0)); 1372 // Operand: rs1 1373 OutInst.addOperand(MI.getOperand(1)); 1374 // Operand: imm12 1375 OutInst.addOperand(MI.getOperand(2)); 1376 OutInst.setLoc(MI.getLoc()); 1377 return true; 1378 } // if 1379 break; 1380 } // case C_FSDSP 1381 case RISCV::C_FSW: { 1382 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 1383 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1384 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 1385 (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) && 1386 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1387 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1388 // fsw $rs2, ${imm12}(${rs1}) 1389 OutInst.setOpcode(RISCV::FSW); 1390 // Operand: rs2 1391 OutInst.addOperand(MI.getOperand(0)); 1392 // Operand: rs1 1393 OutInst.addOperand(MI.getOperand(1)); 1394 // Operand: imm12 1395 OutInst.addOperand(MI.getOperand(2)); 1396 OutInst.setLoc(MI.getLoc()); 1397 return true; 1398 } // if 1399 break; 1400 } // case C_FSW 1401 case RISCV::C_FSWSP: { 1402 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 1403 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1404 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 1405 (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) && 1406 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1407 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1408 // fsw $rs2, ${imm12}(${rs1}) 1409 OutInst.setOpcode(RISCV::FSW); 1410 // Operand: rs2 1411 OutInst.addOperand(MI.getOperand(0)); 1412 // Operand: rs1 1413 OutInst.addOperand(MI.getOperand(1)); 1414 // Operand: imm12 1415 OutInst.addOperand(MI.getOperand(2)); 1416 OutInst.setLoc(MI.getLoc()); 1417 return true; 1418 } // if 1419 break; 1420 } // case C_FSWSP 1421 case RISCV::C_J: { 1422 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1423 RISCVValidateMCOperand(MI.getOperand(0), STI, 3)) { 1424 // jal $rd, $imm20 1425 OutInst.setOpcode(RISCV::JAL); 1426 // Operand: rd 1427 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1428 // Operand: imm20 1429 OutInst.addOperand(MI.getOperand(0)); 1430 OutInst.setLoc(MI.getLoc()); 1431 return true; 1432 } // if 1433 break; 1434 } // case C_J 1435 case RISCV::C_JAL: { 1436 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 1437 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1438 RISCVValidateMCOperand(MI.getOperand(0), STI, 3)) { 1439 // jal $rd, $imm20 1440 OutInst.setOpcode(RISCV::JAL); 1441 // Operand: rd 1442 OutInst.addOperand(MCOperand::createReg(RISCV::X1)); 1443 // Operand: imm20 1444 OutInst.addOperand(MI.getOperand(0)); 1445 OutInst.setLoc(MI.getLoc()); 1446 return true; 1447 } // if 1448 break; 1449 } // case C_JAL 1450 case RISCV::C_JALR: { 1451 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1452 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1453 RISCVValidateMCOperand(MCOperand::createImm(0), STI, 1)) { 1454 // jalr $rd, ${imm12}(${rs1}) 1455 OutInst.setOpcode(RISCV::JALR); 1456 // Operand: rd 1457 OutInst.addOperand(MCOperand::createReg(RISCV::X1)); 1458 // Operand: rs1 1459 OutInst.addOperand(MI.getOperand(0)); 1460 // Operand: imm12 1461 OutInst.addOperand(MCOperand::createImm(0)); 1462 OutInst.setLoc(MI.getLoc()); 1463 return true; 1464 } // if 1465 break; 1466 } // case C_JALR 1467 case RISCV::C_JR: { 1468 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1469 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1470 RISCVValidateMCOperand(MCOperand::createImm(0), STI, 1)) { 1471 // jalr $rd, ${imm12}(${rs1}) 1472 OutInst.setOpcode(RISCV::JALR); 1473 // Operand: rd 1474 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1475 // Operand: rs1 1476 OutInst.addOperand(MI.getOperand(0)); 1477 // Operand: imm12 1478 OutInst.addOperand(MCOperand::createImm(0)); 1479 OutInst.setLoc(MI.getLoc()); 1480 return true; 1481 } // if 1482 break; 1483 } // case C_JR 1484 case RISCV::C_LD: { 1485 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1486 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1487 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1488 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1489 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1490 // ld $rd, ${imm12}(${rs1}) 1491 OutInst.setOpcode(RISCV::LD); 1492 // Operand: rd 1493 OutInst.addOperand(MI.getOperand(0)); 1494 // Operand: rs1 1495 OutInst.addOperand(MI.getOperand(1)); 1496 // Operand: imm12 1497 OutInst.addOperand(MI.getOperand(2)); 1498 OutInst.setLoc(MI.getLoc()); 1499 return true; 1500 } // if 1501 break; 1502 } // case C_LD 1503 case RISCV::C_LDSP: { 1504 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1505 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1506 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1507 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1508 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1509 // ld $rd, ${imm12}(${rs1}) 1510 OutInst.setOpcode(RISCV::LD); 1511 // Operand: rd 1512 OutInst.addOperand(MI.getOperand(0)); 1513 // Operand: rs1 1514 OutInst.addOperand(MI.getOperand(1)); 1515 // Operand: imm12 1516 OutInst.addOperand(MI.getOperand(2)); 1517 OutInst.setLoc(MI.getLoc()); 1518 return true; 1519 } // if 1520 break; 1521 } // case C_LDSP 1522 case RISCV::C_LI: { 1523 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1524 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1525 RISCVValidateMCOperand(MI.getOperand(1), STI, 1)) { 1526 // addi $rd, $rs1, $imm12 1527 OutInst.setOpcode(RISCV::ADDI); 1528 // Operand: rd 1529 OutInst.addOperand(MI.getOperand(0)); 1530 // Operand: rs1 1531 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1532 // Operand: imm12 1533 OutInst.addOperand(MI.getOperand(1)); 1534 OutInst.setLoc(MI.getLoc()); 1535 return true; 1536 } // if 1537 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1538 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1539 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1540 RISCVValidateMCOperand(MI.getOperand(1), STI, 1)) { 1541 // addiw $rd, $rs1, $imm12 1542 OutInst.setOpcode(RISCV::ADDIW); 1543 // Operand: rd 1544 OutInst.addOperand(MI.getOperand(0)); 1545 // Operand: rs1 1546 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1547 // Operand: imm12 1548 OutInst.addOperand(MI.getOperand(1)); 1549 OutInst.setLoc(MI.getLoc()); 1550 return true; 1551 } // if 1552 break; 1553 } // case C_LI 1554 case RISCV::C_LUI: { 1555 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1556 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1557 RISCVValidateMCOperand(MI.getOperand(1), STI, 4)) { 1558 // lui $rd, $imm20 1559 OutInst.setOpcode(RISCV::LUI); 1560 // Operand: rd 1561 OutInst.addOperand(MI.getOperand(0)); 1562 // Operand: imm20 1563 OutInst.addOperand(MI.getOperand(1)); 1564 OutInst.setLoc(MI.getLoc()); 1565 return true; 1566 } // if 1567 break; 1568 } // case C_LUI 1569 case RISCV::C_LW: { 1570 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1571 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1572 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1573 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1574 // lw $rd, ${imm12}(${rs1}) 1575 OutInst.setOpcode(RISCV::LW); 1576 // Operand: rd 1577 OutInst.addOperand(MI.getOperand(0)); 1578 // Operand: rs1 1579 OutInst.addOperand(MI.getOperand(1)); 1580 // Operand: imm12 1581 OutInst.addOperand(MI.getOperand(2)); 1582 OutInst.setLoc(MI.getLoc()); 1583 return true; 1584 } // if 1585 break; 1586 } // case C_LW 1587 case RISCV::C_LWSP: { 1588 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1589 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1590 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1591 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1592 // lw $rd, ${imm12}(${rs1}) 1593 OutInst.setOpcode(RISCV::LW); 1594 // Operand: rd 1595 OutInst.addOperand(MI.getOperand(0)); 1596 // Operand: rs1 1597 OutInst.addOperand(MI.getOperand(1)); 1598 // Operand: imm12 1599 OutInst.addOperand(MI.getOperand(2)); 1600 OutInst.setLoc(MI.getLoc()); 1601 return true; 1602 } // if 1603 break; 1604 } // case C_LWSP 1605 case RISCV::C_MV: { 1606 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1607 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1608 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()))) { 1609 // add $rd, $rs1, $rs2 1610 OutInst.setOpcode(RISCV::ADD); 1611 // Operand: rd 1612 OutInst.addOperand(MI.getOperand(0)); 1613 // Operand: rs1 1614 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1615 // Operand: rs2 1616 OutInst.addOperand(MI.getOperand(1)); 1617 OutInst.setLoc(MI.getLoc()); 1618 return true; 1619 } // if 1620 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1621 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1622 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg()))) { 1623 // add $rd, $rs1, $rs2 1624 OutInst.setOpcode(RISCV::ADD); 1625 // Operand: rd 1626 OutInst.addOperand(MI.getOperand(0)); 1627 // Operand: rs1 1628 OutInst.addOperand(MI.getOperand(1)); 1629 // Operand: rs2 1630 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1631 OutInst.setLoc(MI.getLoc()); 1632 return true; 1633 } // if 1634 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1635 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1636 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1637 RISCVValidateMCOperand(MCOperand::createImm(0), STI, 1)) { 1638 // addi $rd, $rs1, $imm12 1639 OutInst.setOpcode(RISCV::ADDI); 1640 // Operand: rd 1641 OutInst.addOperand(MI.getOperand(0)); 1642 // Operand: rs1 1643 OutInst.addOperand(MI.getOperand(1)); 1644 // Operand: imm12 1645 OutInst.addOperand(MCOperand::createImm(0)); 1646 OutInst.setLoc(MI.getLoc()); 1647 return true; 1648 } // if 1649 break; 1650 } // case C_MV 1651 case RISCV::C_NOP: { 1652 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1653 RISCVValidateMCOperand(MCOperand::createImm(0), STI, 1)) { 1654 // addi $rd, $rs1, $imm12 1655 OutInst.setOpcode(RISCV::ADDI); 1656 // Operand: rd 1657 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1658 // Operand: rs1 1659 OutInst.addOperand(MCOperand::createReg(RISCV::X0)); 1660 // Operand: imm12 1661 OutInst.addOperand(MCOperand::createImm(0)); 1662 OutInst.setLoc(MI.getLoc()); 1663 return true; 1664 } // if 1665 break; 1666 } // case C_NOP 1667 case RISCV::C_OR: { 1668 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1669 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1670 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1671 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) { 1672 // or $rd, $rs1, $rs2 1673 OutInst.setOpcode(RISCV::OR); 1674 // Operand: rd 1675 OutInst.addOperand(MI.getOperand(0)); 1676 // Operand: rs1 1677 OutInst.addOperand(MI.getOperand(0)); 1678 // Operand: rs2 1679 OutInst.addOperand(MI.getOperand(2)); 1680 OutInst.setLoc(MI.getLoc()); 1681 return true; 1682 } // if 1683 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1684 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1685 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) && 1686 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) { 1687 // or $rd, $rs1, $rs2 1688 OutInst.setOpcode(RISCV::OR); 1689 // Operand: rd 1690 OutInst.addOperand(MI.getOperand(0)); 1691 // Operand: rs1 1692 OutInst.addOperand(MI.getOperand(2)); 1693 // Operand: rs2 1694 OutInst.addOperand(MI.getOperand(0)); 1695 OutInst.setLoc(MI.getLoc()); 1696 return true; 1697 } // if 1698 break; 1699 } // case C_OR 1700 case RISCV::C_SD: { 1701 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1702 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1703 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1704 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1705 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1706 // sd $rs2, ${imm12}(${rs1}) 1707 OutInst.setOpcode(RISCV::SD); 1708 // Operand: rs2 1709 OutInst.addOperand(MI.getOperand(0)); 1710 // Operand: rs1 1711 OutInst.addOperand(MI.getOperand(1)); 1712 // Operand: imm12 1713 OutInst.addOperand(MI.getOperand(2)); 1714 OutInst.setLoc(MI.getLoc()); 1715 return true; 1716 } // if 1717 break; 1718 } // case C_SD 1719 case RISCV::C_SDSP: { 1720 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1721 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1722 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1723 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1724 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1725 // sd $rs2, ${imm12}(${rs1}) 1726 OutInst.setOpcode(RISCV::SD); 1727 // Operand: rs2 1728 OutInst.addOperand(MI.getOperand(0)); 1729 // Operand: rs1 1730 OutInst.addOperand(MI.getOperand(1)); 1731 // Operand: imm12 1732 OutInst.addOperand(MI.getOperand(2)); 1733 OutInst.setLoc(MI.getLoc()); 1734 return true; 1735 } // if 1736 break; 1737 } // case C_SDSP 1738 case RISCV::C_SLLI: { 1739 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1740 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1741 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1742 RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) { 1743 // slli $rd, $rs1, $shamt 1744 OutInst.setOpcode(RISCV::SLLI); 1745 // Operand: rd 1746 OutInst.addOperand(MI.getOperand(0)); 1747 // Operand: rs1 1748 OutInst.addOperand(MI.getOperand(0)); 1749 // Operand: shamt 1750 OutInst.addOperand(MI.getOperand(2)); 1751 OutInst.setLoc(MI.getLoc()); 1752 return true; 1753 } // if 1754 break; 1755 } // case C_SLLI 1756 case RISCV::C_SRAI: { 1757 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1758 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1759 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1760 RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) { 1761 // srai $rd, $rs1, $shamt 1762 OutInst.setOpcode(RISCV::SRAI); 1763 // Operand: rd 1764 OutInst.addOperand(MI.getOperand(0)); 1765 // Operand: rs1 1766 OutInst.addOperand(MI.getOperand(0)); 1767 // Operand: shamt 1768 OutInst.addOperand(MI.getOperand(2)); 1769 OutInst.setLoc(MI.getLoc()); 1770 return true; 1771 } // if 1772 break; 1773 } // case C_SRAI 1774 case RISCV::C_SRLI: { 1775 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1776 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1777 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1778 RISCVValidateMCOperand(MI.getOperand(2), STI, 5)) { 1779 // srli $rd, $rs1, $shamt 1780 OutInst.setOpcode(RISCV::SRLI); 1781 // Operand: rd 1782 OutInst.addOperand(MI.getOperand(0)); 1783 // Operand: rs1 1784 OutInst.addOperand(MI.getOperand(0)); 1785 // Operand: shamt 1786 OutInst.addOperand(MI.getOperand(2)); 1787 OutInst.setLoc(MI.getLoc()); 1788 return true; 1789 } // if 1790 break; 1791 } // case C_SRLI 1792 case RISCV::C_SUB: { 1793 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1794 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1795 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1796 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) { 1797 // sub $rd, $rs1, $rs2 1798 OutInst.setOpcode(RISCV::SUB); 1799 // Operand: rd 1800 OutInst.addOperand(MI.getOperand(0)); 1801 // Operand: rs1 1802 OutInst.addOperand(MI.getOperand(0)); 1803 // Operand: rs2 1804 OutInst.addOperand(MI.getOperand(2)); 1805 OutInst.setLoc(MI.getLoc()); 1806 return true; 1807 } // if 1808 break; 1809 } // case C_SUB 1810 case RISCV::C_SUBW: { 1811 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 1812 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1813 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1814 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1815 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) { 1816 // subw $rd, $rs1, $rs2 1817 OutInst.setOpcode(RISCV::SUBW); 1818 // Operand: rd 1819 OutInst.addOperand(MI.getOperand(0)); 1820 // Operand: rs1 1821 OutInst.addOperand(MI.getOperand(0)); 1822 // Operand: rs2 1823 OutInst.addOperand(MI.getOperand(2)); 1824 OutInst.setLoc(MI.getLoc()); 1825 return true; 1826 } // if 1827 break; 1828 } // case C_SUBW 1829 case RISCV::C_SW: { 1830 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1831 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1832 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1833 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1834 // sw $rs2, ${imm12}(${rs1}) 1835 OutInst.setOpcode(RISCV::SW); 1836 // Operand: rs2 1837 OutInst.addOperand(MI.getOperand(0)); 1838 // Operand: rs1 1839 OutInst.addOperand(MI.getOperand(1)); 1840 // Operand: imm12 1841 OutInst.addOperand(MI.getOperand(2)); 1842 OutInst.setLoc(MI.getLoc()); 1843 return true; 1844 } // if 1845 break; 1846 } // case C_SW 1847 case RISCV::C_SWSP: { 1848 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1849 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1850 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(1).getReg())) && 1851 RISCVValidateMCOperand(MI.getOperand(2), STI, 1)) { 1852 // sw $rs2, ${imm12}(${rs1}) 1853 OutInst.setOpcode(RISCV::SW); 1854 // Operand: rs2 1855 OutInst.addOperand(MI.getOperand(0)); 1856 // Operand: rs1 1857 OutInst.addOperand(MI.getOperand(1)); 1858 // Operand: imm12 1859 OutInst.addOperand(MI.getOperand(2)); 1860 OutInst.setLoc(MI.getLoc()); 1861 return true; 1862 } // if 1863 break; 1864 } // case C_SWSP 1865 case RISCV::C_UNIMP: { 1866 if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) { 1867 // unimp 1868 OutInst.setOpcode(RISCV::UNIMP); 1869 OutInst.setLoc(MI.getLoc()); 1870 return true; 1871 } // if 1872 break; 1873 } // case C_UNIMP 1874 case RISCV::C_XOR: { 1875 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1876 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1877 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1878 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg()))) { 1879 // xor $rd, $rs1, $rs2 1880 OutInst.setOpcode(RISCV::XOR); 1881 // Operand: rd 1882 OutInst.addOperand(MI.getOperand(0)); 1883 // Operand: rs1 1884 OutInst.addOperand(MI.getOperand(0)); 1885 // Operand: rs2 1886 OutInst.addOperand(MI.getOperand(2)); 1887 OutInst.setLoc(MI.getLoc()); 1888 return true; 1889 } // if 1890 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1891 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 1892 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(2).getReg())) && 1893 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg()))) { 1894 // xor $rd, $rs1, $rs2 1895 OutInst.setOpcode(RISCV::XOR); 1896 // Operand: rd 1897 OutInst.addOperand(MI.getOperand(0)); 1898 // Operand: rs1 1899 OutInst.addOperand(MI.getOperand(2)); 1900 // Operand: rs2 1901 OutInst.addOperand(MI.getOperand(0)); 1902 OutInst.setLoc(MI.getLoc()); 1903 return true; 1904 } // if 1905 1906 } // case C_XOR 1907 } // switch 1908 return false; 1909} 1910 1911#endif //GEN_UNCOMPRESS_INSTR 1912 1913 1914#ifdef GEN_CHECK_COMPRESS_INSTR 1915#undef GEN_CHECK_COMPRESS_INSTR 1916 1917static bool RISCVValidateMachineOperand(const MachineOperand &MO, 1918 const RISCVSubtarget *Subtarget, 1919 unsigned PredicateIndex) { 1920 int64_t Imm = MO.getImm(); 1921 switch (PredicateIndex) { 1922 default: 1923 llvm_unreachable("Unknown ImmLeaf Predicate kind"); 1924 break; 1925 case 1: { 1926 // simm6nonzero 1927 return (Imm != 0) && isInt<6>(Imm); 1928 } 1929 case 2: { 1930 // simm10_lsb0000nonzero 1931 return (Imm != 0) && isShiftedInt<6, 4>(Imm); 1932 } 1933 case 3: { 1934 // uimm10_lsb00nonzero 1935 return isShiftedUInt<8, 2>(Imm) && (Imm != 0); 1936 } 1937 case 4: { 1938 // simm6 1939 return isInt<6>(Imm); 1940 } 1941 case 5: { 1942 // simm9_lsb0 1943 return isShiftedInt<8, 1>(Imm); 1944 } 1945 case 6: { 1946 // uimm8_lsb000 1947 return isShiftedUInt<5, 3>(Imm); 1948 } 1949 case 7: { 1950 // uimm9_lsb000 1951 return isShiftedUInt<6, 3>(Imm); 1952 } 1953 case 8: { 1954 // uimm7_lsb00 1955 return isShiftedUInt<5, 2>(Imm); 1956 } 1957 case 9: { 1958 // uimm8_lsb00 1959 return isShiftedUInt<6, 2>(Imm); 1960 } 1961 case 10: { 1962 // simm12_lsb0 1963 return isShiftedInt<11, 1>(Imm); 1964 } 1965 case 11: { 1966 // c_lui_imm 1967 return (Imm != 0) && 1968 (isUInt<5>(Imm) || 1969 (Imm >= 0xfffe0 && Imm <= 0xfffff)); 1970 } 1971 case 12: { 1972 // uimmlog2xlennonzero 1973 1974 if (Subtarget->is64Bit()) 1975 return isUInt<6>(Imm) && (Imm != 0); 1976 return isUInt<5>(Imm) && (Imm != 0); 1977 1978 } 1979 } 1980} 1981 1982static bool isCompressibleInst(const MachineInstr& MI, 1983 const RISCVSubtarget *Subtarget, 1984 const MCRegisterInfo &MRI, 1985 const MCSubtargetInfo &STI) { 1986 switch (MI.getOpcode()) { 1987 default: return false; 1988 case RISCV::ADD: { 1989 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 1990 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 1991 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) && 1992 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) { 1993 // c.add $rs1, $rs2 1994 // Operand: rs1_wb 1995 // Operand: rs1 1996 // Operand: rs2 1997 return true; 1998 } // if 1999 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2000 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2001 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg())) && 2002 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 2003 // c.add $rs1, $rs2 2004 // Operand: rs1_wb 2005 // Operand: rs1 2006 // Operand: rs2 2007 return true; 2008 } // if 2009 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2010 (MI.getOperand(1).getReg() == RISCV::X0) && 2011 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 2012 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(2).getReg()))) { 2013 // c.mv $rs1, $rs2 2014 // Operand: rs1 2015 // Operand: rs2 2016 return true; 2017 } // if 2018 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2019 (MI.getOperand(2).getReg() == RISCV::X0) && 2020 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 2021 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 2022 // c.mv $rs1, $rs2 2023 // Operand: rs1 2024 // Operand: rs2 2025 return true; 2026 } // if 2027 break; 2028 } // case ADD 2029 case RISCV::ADDI: { 2030 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2031 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2032 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) && 2033 MI.getOperand(2).isImm() && 2034 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 1)) { 2035 // c.addi $rd, $imm 2036 // Operand: rd_wb 2037 // Operand: rd 2038 // Operand: imm 2039 return true; 2040 } // if 2041 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2042 (MI.getOperand(0).getReg() == RISCV::X2) && 2043 (MI.getOperand(1).getReg() == RISCV::X2) && 2044 MI.getOperand(2).isImm() && 2045 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 2)) { 2046 // c.addi16sp $rd, $imm 2047 // Operand: rd_wb 2048 // Operand: rd 2049 // Operand: imm 2050 return true; 2051 } // if 2052 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2053 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 2054 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 2055 MI.getOperand(2).isImm() && 2056 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 3)) { 2057 // c.addi4spn $rd, $rs1, $imm 2058 // Operand: rd 2059 // Operand: rs1 2060 // Operand: imm 2061 return true; 2062 } // if 2063 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2064 (MI.getOperand(1).getReg() == RISCV::X0) && 2065 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 2066 MI.getOperand(2).isImm() && 2067 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 4)) { 2068 // c.li $rd, $imm 2069 // Operand: rd 2070 // Operand: imm 2071 return true; 2072 } // if 2073 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2074 (MI.getOperand(2).isImm()) && 2075 (MI.getOperand(2).getImm() == 0) && 2076 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 2077 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 2078 // c.mv $rs1, $rs2 2079 // Operand: rs1 2080 // Operand: rs2 2081 return true; 2082 } // if 2083 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2084 (MI.getOperand(0).getReg() == RISCV::X0) && 2085 (MI.getOperand(1).getReg() == RISCV::X0) && 2086 (MI.getOperand(2).isImm()) && 2087 (MI.getOperand(2).getImm() == 0)) { 2088 // c.nop 2089 return true; 2090 } // if 2091 break; 2092 } // case ADDI 2093 case RISCV::ADDIW: { 2094 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2095 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2096 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2097 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) && 2098 MI.getOperand(2).isImm() && 2099 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 4)) { 2100 // c.addiw $rd, $imm 2101 // Operand: rd_wb 2102 // Operand: rd 2103 // Operand: imm 2104 return true; 2105 } // if 2106 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2107 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2108 (MI.getOperand(1).getReg() == RISCV::X0) && 2109 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 2110 MI.getOperand(2).isImm() && 2111 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 4)) { 2112 // c.li $rd, $imm 2113 // Operand: rd 2114 // Operand: imm 2115 return true; 2116 } // if 2117 break; 2118 } // case ADDIW 2119 case RISCV::ADDW: { 2120 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2121 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2122 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2123 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2124 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 2125 // c.addw $rd, $rs2 2126 // Operand: rd_wb 2127 // Operand: rd 2128 // Operand: rs2 2129 return true; 2130 } // if 2131 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2132 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2133 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2134 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 2135 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 2136 // c.addw $rd, $rs2 2137 // Operand: rd_wb 2138 // Operand: rd 2139 // Operand: rs2 2140 return true; 2141 } // if 2142 break; 2143 } // case ADDW 2144 case RISCV::AND: { 2145 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2146 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2147 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2148 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 2149 // c.and $rd, $rs2 2150 // Operand: rd_wb 2151 // Operand: rd 2152 // Operand: rs2 2153 return true; 2154 } // if 2155 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2156 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2157 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 2158 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 2159 // c.and $rd, $rs2 2160 // Operand: rd_wb 2161 // Operand: rd 2162 // Operand: rs2 2163 return true; 2164 } // if 2165 break; 2166 } // case AND 2167 case RISCV::ANDI: { 2168 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2169 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2170 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2171 MI.getOperand(2).isImm() && 2172 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 4)) { 2173 // c.andi $rs1, $imm 2174 // Operand: rs1_wb 2175 // Operand: rs1 2176 // Operand: imm 2177 return true; 2178 } // if 2179 break; 2180 } // case ANDI 2181 case RISCV::BEQ: { 2182 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2183 (MI.getOperand(1).getReg() == RISCV::X0) && 2184 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 2185 MI.getOperand(2).isImm() && 2186 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 5)) { 2187 // c.beqz $rs1, $imm 2188 // Operand: rs1 2189 // Operand: imm 2190 return true; 2191 } // if 2192 break; 2193 } // case BEQ 2194 case RISCV::BNE: { 2195 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2196 (MI.getOperand(1).getReg() == RISCV::X0) && 2197 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 2198 MI.getOperand(2).isImm() && 2199 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 5)) { 2200 // c.bnez $rs1, $imm 2201 // Operand: rs1 2202 // Operand: imm 2203 return true; 2204 } // if 2205 break; 2206 } // case BNE 2207 case RISCV::EBREAK: { 2208 if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) { 2209 // c.ebreak 2210 return true; 2211 } // if 2212 break; 2213 } // case EBREAK 2214 case RISCV::FLD: { 2215 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2216 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 2217 (MRI.getRegClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg())) && 2218 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2219 MI.getOperand(2).isImm() && 2220 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 6)) { 2221 // c.fld $rd, ${imm}(${rs1}) 2222 // Operand: rd 2223 // Operand: rs1 2224 // Operand: imm 2225 return true; 2226 } // if 2227 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2228 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 2229 (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) && 2230 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 2231 MI.getOperand(2).isImm() && 2232 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 7)) { 2233 // c.fldsp $rd, ${imm}(${rs1}) 2234 // Operand: rd 2235 // Operand: rs1 2236 // Operand: imm 2237 return true; 2238 } // if 2239 break; 2240 } // case FLD 2241 case RISCV::FLW: { 2242 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 2243 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2244 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 2245 (MRI.getRegClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg())) && 2246 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2247 MI.getOperand(2).isImm() && 2248 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 8)) { 2249 // c.flw $rd, ${imm}(${rs1}) 2250 // Operand: rd 2251 // Operand: rs1 2252 // Operand: imm 2253 return true; 2254 } // if 2255 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 2256 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2257 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 2258 (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) && 2259 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 2260 MI.getOperand(2).isImm() && 2261 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 9)) { 2262 // c.flwsp $rd, ${imm}(${rs1}) 2263 // Operand: rd 2264 // Operand: rs1 2265 // Operand: imm 2266 return true; 2267 } // if 2268 break; 2269 } // case FLW 2270 case RISCV::FSD: { 2271 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2272 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 2273 (MRI.getRegClass(RISCV::FPR64CRegClassID).contains(MI.getOperand(0).getReg())) && 2274 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2275 MI.getOperand(2).isImm() && 2276 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 6)) { 2277 // c.fsd $rs2, ${imm}(${rs1}) 2278 // Operand: rs2 2279 // Operand: rs1 2280 // Operand: imm 2281 return true; 2282 } // if 2283 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2284 STI.getFeatureBits()[RISCV::FeatureStdExtD] && 2285 (MRI.getRegClass(RISCV::FPR64RegClassID).contains(MI.getOperand(0).getReg())) && 2286 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 2287 MI.getOperand(2).isImm() && 2288 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 7)) { 2289 // c.fsdsp $rs2, ${imm}(${rs1}) 2290 // Operand: rs2 2291 // Operand: rs1 2292 // Operand: imm 2293 return true; 2294 } // if 2295 break; 2296 } // case FSD 2297 case RISCV::FSW: { 2298 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 2299 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2300 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 2301 (MRI.getRegClass(RISCV::FPR32CRegClassID).contains(MI.getOperand(0).getReg())) && 2302 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2303 MI.getOperand(2).isImm() && 2304 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 8)) { 2305 // c.fsw $rs2, ${imm}(${rs1}) 2306 // Operand: rs2 2307 // Operand: rs1 2308 // Operand: imm 2309 return true; 2310 } // if 2311 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 2312 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2313 STI.getFeatureBits()[RISCV::FeatureStdExtF] && 2314 (MRI.getRegClass(RISCV::FPR32RegClassID).contains(MI.getOperand(0).getReg())) && 2315 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 2316 MI.getOperand(2).isImm() && 2317 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 9)) { 2318 // c.fswsp $rs2, ${imm}(${rs1}) 2319 // Operand: rs2 2320 // Operand: rs1 2321 // Operand: imm 2322 return true; 2323 } // if 2324 break; 2325 } // case FSW 2326 case RISCV::JAL: { 2327 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2328 (MI.getOperand(0).getReg() == RISCV::X0) && 2329 MI.getOperand(1).isImm() && 2330 RISCVValidateMachineOperand(MI.getOperand(1), Subtarget, 10)) { 2331 // c.j $offset 2332 // Operand: offset 2333 return true; 2334 } // if 2335 if (!STI.getFeatureBits()[RISCV::Feature64Bit] && 2336 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2337 (MI.getOperand(0).getReg() == RISCV::X1) && 2338 MI.getOperand(1).isImm() && 2339 RISCVValidateMachineOperand(MI.getOperand(1), Subtarget, 10)) { 2340 // c.jal $offset 2341 // Operand: offset 2342 return true; 2343 } // if 2344 break; 2345 } // case JAL 2346 case RISCV::JALR: { 2347 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2348 (MI.getOperand(0).getReg() == RISCV::X1) && 2349 (MI.getOperand(2).isImm()) && 2350 (MI.getOperand(2).getImm() == 0) && 2351 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 2352 // c.jalr $rs1 2353 // Operand: rs1 2354 return true; 2355 } // if 2356 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2357 (MI.getOperand(0).getReg() == RISCV::X0) && 2358 (MI.getOperand(2).isImm()) && 2359 (MI.getOperand(2).getImm() == 0) && 2360 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg()))) { 2361 // c.jr $rs1 2362 // Operand: rs1 2363 return true; 2364 } // if 2365 break; 2366 } // case JALR 2367 case RISCV::LD: { 2368 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2369 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2370 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 2371 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2372 MI.getOperand(2).isImm() && 2373 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 6)) { 2374 // c.ld $rd, ${imm}(${rs1}) 2375 // Operand: rd 2376 // Operand: rs1 2377 // Operand: imm 2378 return true; 2379 } // if 2380 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2381 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2382 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 2383 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 2384 MI.getOperand(2).isImm() && 2385 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 7)) { 2386 // c.ldsp $rd, ${imm}(${rs1}) 2387 // Operand: rd 2388 // Operand: rs1 2389 // Operand: imm 2390 return true; 2391 } // if 2392 break; 2393 } // case LD 2394 case RISCV::LUI: { 2395 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2396 (MRI.getRegClass(RISCV::GPRNoX0X2RegClassID).contains(MI.getOperand(0).getReg())) && 2397 MI.getOperand(1).isImm() && 2398 RISCVValidateMachineOperand(MI.getOperand(1), Subtarget, 11)) { 2399 // c.lui $rd, $imm 2400 // Operand: rd 2401 // Operand: imm 2402 return true; 2403 } // if 2404 break; 2405 } // case LUI 2406 case RISCV::LW: { 2407 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2408 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 2409 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2410 MI.getOperand(2).isImm() && 2411 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 8)) { 2412 // c.lw $rd, ${imm}(${rs1}) 2413 // Operand: rd 2414 // Operand: rs1 2415 // Operand: imm 2416 return true; 2417 } // if 2418 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2419 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(0).getReg())) && 2420 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 2421 MI.getOperand(2).isImm() && 2422 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 9)) { 2423 // c.lwsp $rd, ${imm}(${rs1}) 2424 // Operand: rd 2425 // Operand: rs1 2426 // Operand: imm 2427 return true; 2428 } // if 2429 break; 2430 } // case LW 2431 case RISCV::OR: { 2432 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2433 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2434 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2435 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 2436 // c.or $rd, $rs2 2437 // Operand: rd_wb 2438 // Operand: rd 2439 // Operand: rs2 2440 return true; 2441 } // if 2442 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2443 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2444 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 2445 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 2446 // c.or $rd, $rs2 2447 // Operand: rd_wb 2448 // Operand: rd 2449 // Operand: rs2 2450 return true; 2451 } // if 2452 break; 2453 } // case OR 2454 case RISCV::SD: { 2455 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2456 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2457 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 2458 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2459 MI.getOperand(2).isImm() && 2460 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 6)) { 2461 // c.sd $rs2, ${imm}(${rs1}) 2462 // Operand: rs2 2463 // Operand: rs1 2464 // Operand: imm 2465 return true; 2466 } // if 2467 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2468 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2469 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 2470 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 2471 MI.getOperand(2).isImm() && 2472 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 7)) { 2473 // c.sdsp $rs2, ${imm}(${rs1}) 2474 // Operand: rs2 2475 // Operand: rs1 2476 // Operand: imm 2477 return true; 2478 } // if 2479 break; 2480 } // case SD 2481 case RISCV::SLLI: { 2482 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2483 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2484 (MRI.getRegClass(RISCV::GPRNoX0RegClassID).contains(MI.getOperand(1).getReg())) && 2485 MI.getOperand(2).isImm() && 2486 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 12)) { 2487 // c.slli $rd, $imm 2488 // Operand: rd_wb 2489 // Operand: rd 2490 // Operand: imm 2491 return true; 2492 } // if 2493 break; 2494 } // case SLLI 2495 case RISCV::SRAI: { 2496 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2497 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2498 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2499 MI.getOperand(2).isImm() && 2500 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 12)) { 2501 // c.srai $rs1, $imm 2502 // Operand: rs1_wb 2503 // Operand: rs1 2504 // Operand: imm 2505 return true; 2506 } // if 2507 break; 2508 } // case SRAI 2509 case RISCV::SRLI: { 2510 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2511 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2512 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2513 MI.getOperand(2).isImm() && 2514 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 12)) { 2515 // c.srli $rs1, $imm 2516 // Operand: rs1_wb 2517 // Operand: rs1 2518 // Operand: imm 2519 return true; 2520 } // if 2521 break; 2522 } // case SRLI 2523 case RISCV::SUB: { 2524 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2525 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2526 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2527 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 2528 // c.sub $rd, $rs2 2529 // Operand: rd_wb 2530 // Operand: rd 2531 // Operand: rs2 2532 return true; 2533 } // if 2534 break; 2535 } // case SUB 2536 case RISCV::SUBW: { 2537 if (STI.getFeatureBits()[RISCV::Feature64Bit] && 2538 STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2539 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2540 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2541 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 2542 // c.subw $rd, $rs2 2543 // Operand: rd_wb 2544 // Operand: rd 2545 // Operand: rs2 2546 return true; 2547 } // if 2548 break; 2549 } // case SUBW 2550 case RISCV::SW: { 2551 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2552 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(0).getReg())) && 2553 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2554 MI.getOperand(2).isImm() && 2555 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 8)) { 2556 // c.sw $rs2, ${imm}(${rs1}) 2557 // Operand: rs2 2558 // Operand: rs1 2559 // Operand: imm 2560 return true; 2561 } // if 2562 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2563 (MRI.getRegClass(RISCV::GPRRegClassID).contains(MI.getOperand(0).getReg())) && 2564 (MRI.getRegClass(RISCV::SPRegClassID).contains(MI.getOperand(1).getReg())) && 2565 MI.getOperand(2).isImm() && 2566 RISCVValidateMachineOperand(MI.getOperand(2), Subtarget, 9)) { 2567 // c.swsp $rs2, ${imm}(${rs1}) 2568 // Operand: rs2 2569 // Operand: rs1 2570 // Operand: imm 2571 return true; 2572 } // if 2573 break; 2574 } // case SW 2575 case RISCV::UNIMP: { 2576 if (STI.getFeatureBits()[RISCV::FeatureStdExtC]) { 2577 // c.unimp 2578 return true; 2579 } // if 2580 break; 2581 } // case UNIMP 2582 case RISCV::XOR: { 2583 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2584 (MI.getOperand(1).getReg() == MI.getOperand(0).getReg()) && 2585 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg())) && 2586 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg()))) { 2587 // c.xor $rd, $rs2 2588 // Operand: rd_wb 2589 // Operand: rd 2590 // Operand: rs2 2591 return true; 2592 } // if 2593 if (STI.getFeatureBits()[RISCV::FeatureStdExtC] && 2594 (MI.getOperand(2).getReg() == MI.getOperand(0).getReg()) && 2595 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(2).getReg())) && 2596 (MRI.getRegClass(RISCV::GPRCRegClassID).contains(MI.getOperand(1).getReg()))) { 2597 // c.xor $rd, $rs2 2598 // Operand: rd_wb 2599 // Operand: rd 2600 // Operand: rs2 2601 return true; 2602 } // if 2603 2604 } // case XOR 2605 } // switch 2606 return false; 2607} 2608 2609#endif //GEN_CHECK_COMPRESS_INSTR 2610