1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Global Instruction Selector for the RISCV target *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_GLOBALISEL_PREDICATE_BITSET 10const unsigned MAX_SUBTARGET_PREDICATES = 6; 11using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>; 12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET 13 14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL 15 mutable MatcherState State; 16 typedef ComplexRendererFns(RISCVInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; 17 typedef void(RISCVInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr&, int) const; 18 const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo; 19 static RISCVInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; 20 static RISCVInstructionSelector::CustomRendererFn CustomRenderers[]; 21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; 22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; 23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; 24 const int64_t *getMatchTable() const override; 25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI) const override; 26#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL 27 28#ifdef GET_GLOBALISEL_TEMPORARIES_INIT 29, State(0), 30ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) 31#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT 32 33#ifdef GET_GLOBALISEL_IMPL 34// Bits for subtarget features that participate in instruction matching. 35enum SubtargetFeatureBits : uint8_t { 36 Feature_HasStdExtMBit = 4, 37 Feature_HasStdExtABit = 5, 38 Feature_HasStdExtFBit = 0, 39 Feature_HasStdExtDBit = 1, 40 Feature_IsRV64Bit = 3, 41 Feature_IsRV32Bit = 2, 42}; 43 44PredicateBitset RISCVInstructionSelector:: 45computeAvailableModuleFeatures(const RISCVSubtarget *Subtarget) const { 46 PredicateBitset Features; 47 if (Subtarget->hasStdExtM()) 48 Features.set(Feature_HasStdExtMBit); 49 if (Subtarget->hasStdExtA()) 50 Features.set(Feature_HasStdExtABit); 51 if (Subtarget->hasStdExtF()) 52 Features.set(Feature_HasStdExtFBit); 53 if (Subtarget->hasStdExtD()) 54 Features.set(Feature_HasStdExtDBit); 55 if (Subtarget->is64Bit()) 56 Features.set(Feature_IsRV64Bit); 57 if (!Subtarget->is64Bit()) 58 Features.set(Feature_IsRV32Bit); 59 return Features; 60} 61 62void RISCVInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { 63 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const RISCVSubtarget*)&MF.getSubtarget(), &MF); 64} 65PredicateBitset RISCVInstructionSelector:: 66computeAvailableFunctionFeatures(const RISCVSubtarget *Subtarget, const MachineFunction *MF) const { 67 PredicateBitset Features; 68 return Features; 69} 70 71// LLT Objects. 72enum { 73 GILLT_s32, 74 GILLT_s64, 75}; 76const static size_t NumTypeObjects = 2; 77const static LLT TypeObjects[] = { 78 LLT::scalar(32), 79 LLT::scalar(64), 80}; 81 82// Feature bitsets. 83enum { 84 GIFBS_Invalid, 85 GIFBS_HasStdExtA, 86 GIFBS_HasStdExtD, 87 GIFBS_HasStdExtF, 88 GIFBS_HasStdExtM, 89 GIFBS_IsRV32, 90 GIFBS_IsRV64, 91 GIFBS_HasStdExtA_IsRV64, 92 GIFBS_HasStdExtD_IsRV32, 93 GIFBS_HasStdExtD_IsRV64, 94}; 95const static PredicateBitset FeatureBitsets[] { 96 {}, // GIFBS_Invalid 97 {Feature_HasStdExtABit, }, 98 {Feature_HasStdExtDBit, }, 99 {Feature_HasStdExtFBit, }, 100 {Feature_HasStdExtMBit, }, 101 {Feature_IsRV32Bit, }, 102 {Feature_IsRV64Bit, }, 103 {Feature_HasStdExtABit, Feature_IsRV64Bit, }, 104 {Feature_HasStdExtDBit, Feature_IsRV32Bit, }, 105 {Feature_HasStdExtDBit, Feature_IsRV64Bit, }, 106}; 107 108// ComplexPattern predicates. 109enum { 110 GICP_Invalid, 111}; 112// See constructor for table contents 113 114// PatFrag predicates. 115enum { 116 GIPFP_I64_Predicate_c_lui_imm = GIPFP_I64_Invalid + 1, 117 GIPFP_I64_Predicate_immbottomxlenset, 118 GIPFP_I64_Predicate_immzero, 119 GIPFP_I64_Predicate_simm10_lsb0000nonzero, 120 GIPFP_I64_Predicate_simm12, 121 GIPFP_I64_Predicate_simm12_lsb0, 122 GIPFP_I64_Predicate_simm32, 123 GIPFP_I64_Predicate_simm32hi20, 124 GIPFP_I64_Predicate_simm6, 125 GIPFP_I64_Predicate_simm6nonzero, 126 GIPFP_I64_Predicate_simm9_lsb0, 127 GIPFP_I64_Predicate_uimm10_lsb00nonzero, 128 GIPFP_I64_Predicate_uimm5, 129 GIPFP_I64_Predicate_uimm7_lsb00, 130 GIPFP_I64_Predicate_uimm8_lsb00, 131 GIPFP_I64_Predicate_uimm8_lsb000, 132 GIPFP_I64_Predicate_uimm9_lsb000, 133 GIPFP_I64_Predicate_uimmlog2xlen, 134 GIPFP_I64_Predicate_uimmlog2xlennonzero, 135}; 136bool RISCVInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { 137 switch (PredicateID) { 138 case GIPFP_I64_Predicate_c_lui_imm: { 139 return (Imm != 0) && 140 (isUInt<5>(Imm) || 141 (Imm >= 0xfffe0 && Imm <= 0xfffff)); 142 llvm_unreachable("ImmediateCode should have returned"); 143 return false; 144 } 145 case GIPFP_I64_Predicate_immbottomxlenset: { 146 147 if (Subtarget->is64Bit()) 148 return countTrailingOnes<uint64_t>(Imm) >= 6; 149 return countTrailingOnes<uint64_t>(Imm) >= 5; 150 151 llvm_unreachable("ImmediateCode should have returned"); 152 return false; 153 } 154 case GIPFP_I64_Predicate_immzero: { 155 return (Imm == 0); 156 llvm_unreachable("ImmediateCode should have returned"); 157 return false; 158 } 159 case GIPFP_I64_Predicate_simm10_lsb0000nonzero: { 160 return (Imm != 0) && isShiftedInt<6, 4>(Imm); 161 llvm_unreachable("ImmediateCode should have returned"); 162 return false; 163 } 164 case GIPFP_I64_Predicate_simm12: { 165 return isInt<12>(Imm); 166 llvm_unreachable("ImmediateCode should have returned"); 167 return false; 168 } 169 case GIPFP_I64_Predicate_simm12_lsb0: { 170 return isShiftedInt<11, 1>(Imm); 171 llvm_unreachable("ImmediateCode should have returned"); 172 return false; 173 } 174 case GIPFP_I64_Predicate_simm32: { 175 return isInt<32>(Imm); 176 llvm_unreachable("ImmediateCode should have returned"); 177 return false; 178 } 179 case GIPFP_I64_Predicate_simm32hi20: { 180 return isShiftedInt<20, 12>(Imm); 181 llvm_unreachable("ImmediateCode should have returned"); 182 return false; 183 } 184 case GIPFP_I64_Predicate_simm6: { 185 return isInt<6>(Imm); 186 llvm_unreachable("ImmediateCode should have returned"); 187 return false; 188 } 189 case GIPFP_I64_Predicate_simm6nonzero: { 190 return (Imm != 0) && isInt<6>(Imm); 191 llvm_unreachable("ImmediateCode should have returned"); 192 return false; 193 } 194 case GIPFP_I64_Predicate_simm9_lsb0: { 195 return isShiftedInt<8, 1>(Imm); 196 llvm_unreachable("ImmediateCode should have returned"); 197 return false; 198 } 199 case GIPFP_I64_Predicate_uimm10_lsb00nonzero: { 200 return isShiftedUInt<8, 2>(Imm) && (Imm != 0); 201 llvm_unreachable("ImmediateCode should have returned"); 202 return false; 203 } 204 case GIPFP_I64_Predicate_uimm5: { 205 return isUInt<5>(Imm); 206 llvm_unreachable("ImmediateCode should have returned"); 207 return false; 208 } 209 case GIPFP_I64_Predicate_uimm7_lsb00: { 210 return isShiftedUInt<5, 2>(Imm); 211 llvm_unreachable("ImmediateCode should have returned"); 212 return false; 213 } 214 case GIPFP_I64_Predicate_uimm8_lsb00: { 215 return isShiftedUInt<6, 2>(Imm); 216 llvm_unreachable("ImmediateCode should have returned"); 217 return false; 218 } 219 case GIPFP_I64_Predicate_uimm8_lsb000: { 220 return isShiftedUInt<5, 3>(Imm); 221 llvm_unreachable("ImmediateCode should have returned"); 222 return false; 223 } 224 case GIPFP_I64_Predicate_uimm9_lsb000: { 225 return isShiftedUInt<6, 3>(Imm); 226 llvm_unreachable("ImmediateCode should have returned"); 227 return false; 228 } 229 case GIPFP_I64_Predicate_uimmlog2xlen: { 230 231 if (Subtarget->is64Bit()) 232 return isUInt<6>(Imm); 233 return isUInt<5>(Imm); 234 235 llvm_unreachable("ImmediateCode should have returned"); 236 return false; 237 } 238 case GIPFP_I64_Predicate_uimmlog2xlennonzero: { 239 240 if (Subtarget->is64Bit()) 241 return isUInt<6>(Imm) && (Imm != 0); 242 return isUInt<5>(Imm) && (Imm != 0); 243 244 llvm_unreachable("ImmediateCode should have returned"); 245 return false; 246 } 247 } 248 llvm_unreachable("Unknown predicate"); 249 return false; 250} 251bool RISCVInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { 252 llvm_unreachable("Unknown predicate"); 253 return false; 254} 255bool RISCVInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { 256 llvm_unreachable("Unknown predicate"); 257 return false; 258} 259bool RISCVInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI) const { 260 const MachineFunction &MF = *MI.getParent()->getParent(); 261 const MachineRegisterInfo &MRI = MF.getRegInfo(); 262 (void)MRI; 263 llvm_unreachable("Unknown predicate"); 264 return false; 265} 266 267RISCVInstructionSelector::ComplexMatcherMemFn 268RISCVInstructionSelector::ComplexPredicateFns[] = { 269 nullptr, // GICP_Invalid 270}; 271 272// Custom renderers. 273enum { 274 GICR_Invalid, 275}; 276RISCVInstructionSelector::CustomRendererFn 277RISCVInstructionSelector::CustomRenderers[] = { 278 nullptr, // GICR_Invalid 279}; 280 281bool RISCVInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { 282 MachineFunction &MF = *I.getParent()->getParent(); 283 MachineRegisterInfo &MRI = MF.getRegInfo(); 284 const PredicateBitset AvailableFeatures = getAvailableFeatures(); 285 NewMIVector OutMIs; 286 State.MIs.clear(); 287 State.MIs.push_back(&I); 288 289 if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) { 290 return true; 291 } 292 293 return false; 294} 295 296const int64_t *RISCVInstructionSelector::getMatchTable() const { 297 constexpr static int64_t MatchTable0[] = { 298 GIM_SwitchOpcode, /*MI*/0, /*[*/35, 168, /*)*//*default:*//*Label 44*/ 28266, 299 /*TargetOpcode::G_ADD*//*Label 0*/ 138, 300 /*TargetOpcode::G_SUB*//*Label 1*/ 325, 301 /*TargetOpcode::G_MUL*//*Label 2*/ 406, 302 /*TargetOpcode::G_SDIV*//*Label 3*/ 493, 303 /*TargetOpcode::G_UDIV*//*Label 4*/ 580, 304 /*TargetOpcode::G_SREM*//*Label 5*/ 667, 305 /*TargetOpcode::G_UREM*//*Label 6*/ 754, 306 /*TargetOpcode::G_AND*//*Label 7*/ 841, 307 /*TargetOpcode::G_OR*//*Label 8*/ 1166, 308 /*TargetOpcode::G_XOR*//*Label 9*/ 1353, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 309 /*TargetOpcode::G_BITCAST*//*Label 10*/ 1540, 0, 0, 310 /*TargetOpcode::G_READCYCLECOUNTER*//*Label 11*/ 1827, 311 /*TargetOpcode::G_LOAD*//*Label 12*/ 1918, 312 /*TargetOpcode::G_SEXTLOAD*//*Label 13*/ 6036, 313 /*TargetOpcode::G_ZEXTLOAD*//*Label 14*/ 7130, 0, 0, 0, 314 /*TargetOpcode::G_STORE*//*Label 15*/ 8224, 0, 0, 0, 315 /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 16*/ 9563, 316 /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 17*/ 10608, 317 /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 18*/ 11653, 318 /*TargetOpcode::G_ATOMICRMW_AND*//*Label 19*/ 13808, 0, 319 /*TargetOpcode::G_ATOMICRMW_OR*//*Label 20*/ 14853, 320 /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 21*/ 15898, 321 /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 22*/ 16943, 322 /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 23*/ 17988, 323 /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 24*/ 19033, 324 /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 25*/ 20078, 0, 0, 325 /*TargetOpcode::G_FENCE*//*Label 26*/ 21123, 0, 0, 0, 0, 0, 0, 326 /*TargetOpcode::G_CONSTANT*//*Label 27*/ 21392, 0, 0, 0, 0, 0, 0, 327 /*TargetOpcode::G_SHL*//*Label 28*/ 21483, 328 /*TargetOpcode::G_LSHR*//*Label 29*/ 21835, 329 /*TargetOpcode::G_ASHR*//*Label 30*/ 22187, 330 /*TargetOpcode::G_ICMP*//*Label 31*/ 22539, 331 /*TargetOpcode::G_FCMP*//*Label 32*/ 24755, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 332 /*TargetOpcode::G_UMULH*//*Label 33*/ 25936, 333 /*TargetOpcode::G_SMULH*//*Label 34*/ 26023, 0, 0, 0, 334 /*TargetOpcode::G_FMA*//*Label 35*/ 26110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 335 /*TargetOpcode::G_FPEXT*//*Label 36*/ 27245, 336 /*TargetOpcode::G_FPTRUNC*//*Label 37*/ 27273, 337 /*TargetOpcode::G_FPTOSI*//*Label 38*/ 27362, 338 /*TargetOpcode::G_FPTOUI*//*Label 39*/ 27541, 339 /*TargetOpcode::G_SITOFP*//*Label 40*/ 27720, 340 /*TargetOpcode::G_UITOFP*//*Label 41*/ 27897, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 341 /*TargetOpcode::G_BR*//*Label 42*/ 28074, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 342 /*TargetOpcode::G_FSQRT*//*Label 43*/ 28087, 343 // Label 0: @138 344 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 47*/ 324, 345 /*GILLT_s32*//*Label 45*/ 146, 346 /*GILLT_s64*//*Label 46*/ 258, 347 // Label 45: @146 348 GIM_Try, /*On fail goto*//*Label 48*/ 257, 349 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 350 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 351 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 353 GIM_Try, /*On fail goto*//*Label 49*/ 197, // Rule ID 35 // 354 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 355 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 356 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 357 // MIs[1] Operand 1 358 // No operand predicates 359 GIM_CheckIsSafeToFold, /*InsnID*/1, 360 // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 361 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI, 362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 364 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 365 GIR_EraseFromParent, /*InsnID*/0, 366 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 367 // GIR_Coverage, 35, 368 GIR_Done, 369 // Label 49: @197 370 GIM_Try, /*On fail goto*//*Label 50*/ 230, // Rule ID 37 // 371 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 372 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 373 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 374 // MIs[1] Operand 1 375 // No operand predicates 376 GIM_CheckIsSafeToFold, /*InsnID*/1, 377 // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ADDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 378 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI, 379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 381 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 382 GIR_EraseFromParent, /*InsnID*/0, 383 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 384 // GIR_Coverage, 37, 385 GIR_Done, 386 // Label 50: @230 387 GIM_Try, /*On fail goto*//*Label 51*/ 243, // Rule ID 32 // 388 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 389 // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 390 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::ADD, 391 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 392 // GIR_Coverage, 32, 393 GIR_Done, 394 // Label 51: @243 395 GIM_Try, /*On fail goto*//*Label 52*/ 256, // Rule ID 34 // 396 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 397 // (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (ADD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 398 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::ADD, 399 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 400 // GIR_Coverage, 34, 401 GIR_Done, 402 // Label 52: @256 403 GIM_Reject, 404 // Label 48: @257 405 GIM_Reject, 406 // Label 46: @258 407 GIM_Try, /*On fail goto*//*Label 53*/ 323, 408 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 409 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 412 GIM_Try, /*On fail goto*//*Label 54*/ 309, // Rule ID 36 // 413 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 414 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 415 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 416 // MIs[1] Operand 1 417 // No operand predicates 418 GIM_CheckIsSafeToFold, /*InsnID*/1, 419 // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) => (ADDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 420 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI, 421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 423 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 424 GIR_EraseFromParent, /*InsnID*/0, 425 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 426 // GIR_Coverage, 36, 427 GIR_Done, 428 // Label 54: @309 429 GIM_Try, /*On fail goto*//*Label 55*/ 322, // Rule ID 33 // 430 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 431 // (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (ADD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 432 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::ADD, 433 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 434 // GIR_Coverage, 33, 435 GIR_Done, 436 // Label 55: @322 437 GIM_Reject, 438 // Label 53: @323 439 GIM_Reject, 440 // Label 47: @324 441 GIM_Reject, 442 // Label 1: @325 443 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 58*/ 405, 444 /*GILLT_s32*//*Label 56*/ 333, 445 /*GILLT_s64*//*Label 57*/ 375, 446 // Label 56: @333 447 GIM_Try, /*On fail goto*//*Label 59*/ 374, 448 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 449 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 451 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 452 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 453 GIM_Try, /*On fail goto*//*Label 60*/ 364, // Rule ID 38 // 454 // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 455 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB, 456 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 457 // GIR_Coverage, 38, 458 GIR_Done, 459 // Label 60: @364 460 GIM_Try, /*On fail goto*//*Label 61*/ 373, // Rule ID 40 // 461 // (sub:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SUB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 462 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB, 463 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 464 // GIR_Coverage, 40, 465 GIR_Done, 466 // Label 61: @373 467 GIM_Reject, 468 // Label 59: @374 469 GIM_Reject, 470 // Label 57: @375 471 GIM_Try, /*On fail goto*//*Label 62*/ 404, // Rule ID 39 // 472 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 473 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 475 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 476 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 477 // (sub:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SUB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 478 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SUB, 479 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 480 // GIR_Coverage, 39, 481 GIR_Done, 482 // Label 62: @404 483 GIM_Reject, 484 // Label 58: @405 485 GIM_Reject, 486 // Label 2: @406 487 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 65*/ 492, 488 /*GILLT_s32*//*Label 63*/ 414, 489 /*GILLT_s64*//*Label 64*/ 460, 490 // Label 63: @414 491 GIM_Try, /*On fail goto*//*Label 66*/ 459, 492 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 493 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 496 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 497 GIM_Try, /*On fail goto*//*Label 67*/ 447, // Rule ID 473 // 498 GIM_CheckFeatures, GIFBS_HasStdExtM, 499 // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 500 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MUL, 501 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 502 // GIR_Coverage, 473, 503 GIR_Done, 504 // Label 67: @447 505 GIM_Try, /*On fail goto*//*Label 68*/ 458, // Rule ID 475 // 506 GIM_CheckFeatures, GIFBS_HasStdExtM, 507 // (mul:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MUL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 508 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MUL, 509 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 510 // GIR_Coverage, 475, 511 GIR_Done, 512 // Label 68: @458 513 GIM_Reject, 514 // Label 66: @459 515 GIM_Reject, 516 // Label 64: @460 517 GIM_Try, /*On fail goto*//*Label 69*/ 491, // Rule ID 474 // 518 GIM_CheckFeatures, GIFBS_HasStdExtM, 519 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 520 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 524 // (mul:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MUL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 525 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MUL, 526 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 527 // GIR_Coverage, 474, 528 GIR_Done, 529 // Label 69: @491 530 GIM_Reject, 531 // Label 65: @492 532 GIM_Reject, 533 // Label 3: @493 534 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 72*/ 579, 535 /*GILLT_s32*//*Label 70*/ 501, 536 /*GILLT_s64*//*Label 71*/ 547, 537 // Label 70: @501 538 GIM_Try, /*On fail goto*//*Label 73*/ 546, 539 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 540 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 544 GIM_Try, /*On fail goto*//*Label 74*/ 534, // Rule ID 482 // 545 GIM_CheckFeatures, GIFBS_HasStdExtM, 546 // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 547 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIV, 548 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 549 // GIR_Coverage, 482, 550 GIR_Done, 551 // Label 74: @534 552 GIM_Try, /*On fail goto*//*Label 75*/ 545, // Rule ID 484 // 553 GIM_CheckFeatures, GIFBS_HasStdExtM, 554 // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIV:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 555 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIV, 556 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 557 // GIR_Coverage, 484, 558 GIR_Done, 559 // Label 75: @545 560 GIM_Reject, 561 // Label 73: @546 562 GIM_Reject, 563 // Label 71: @547 564 GIM_Try, /*On fail goto*//*Label 76*/ 578, // Rule ID 483 // 565 GIM_CheckFeatures, GIFBS_HasStdExtM, 566 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 567 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 569 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 571 // (sdiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (DIV:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 572 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIV, 573 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 574 // GIR_Coverage, 483, 575 GIR_Done, 576 // Label 76: @578 577 GIM_Reject, 578 // Label 72: @579 579 GIM_Reject, 580 // Label 4: @580 581 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 79*/ 666, 582 /*GILLT_s32*//*Label 77*/ 588, 583 /*GILLT_s64*//*Label 78*/ 634, 584 // Label 77: @588 585 GIM_Try, /*On fail goto*//*Label 80*/ 633, 586 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 587 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 588 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 591 GIM_Try, /*On fail goto*//*Label 81*/ 621, // Rule ID 485 // 592 GIM_CheckFeatures, GIFBS_HasStdExtM, 593 // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 594 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIVU, 595 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 596 // GIR_Coverage, 485, 597 GIR_Done, 598 // Label 81: @621 599 GIM_Try, /*On fail goto*//*Label 82*/ 632, // Rule ID 487 // 600 GIM_CheckFeatures, GIFBS_HasStdExtM, 601 // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (DIVU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 602 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIVU, 603 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 604 // GIR_Coverage, 487, 605 GIR_Done, 606 // Label 82: @632 607 GIM_Reject, 608 // Label 80: @633 609 GIM_Reject, 610 // Label 78: @634 611 GIM_Try, /*On fail goto*//*Label 83*/ 665, // Rule ID 486 // 612 GIM_CheckFeatures, GIFBS_HasStdExtM, 613 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 614 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 617 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 618 // (udiv:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (DIVU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 619 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::DIVU, 620 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 621 // GIR_Coverage, 486, 622 GIR_Done, 623 // Label 83: @665 624 GIM_Reject, 625 // Label 79: @666 626 GIM_Reject, 627 // Label 5: @667 628 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 86*/ 753, 629 /*GILLT_s32*//*Label 84*/ 675, 630 /*GILLT_s64*//*Label 85*/ 721, 631 // Label 84: @675 632 GIM_Try, /*On fail goto*//*Label 87*/ 720, 633 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 634 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 638 GIM_Try, /*On fail goto*//*Label 88*/ 708, // Rule ID 488 // 639 GIM_CheckFeatures, GIFBS_HasStdExtM, 640 // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REM:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 641 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REM, 642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 643 // GIR_Coverage, 488, 644 GIR_Done, 645 // Label 88: @708 646 GIM_Try, /*On fail goto*//*Label 89*/ 719, // Rule ID 490 // 647 GIM_CheckFeatures, GIFBS_HasStdExtM, 648 // (srem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REM:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 649 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REM, 650 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 651 // GIR_Coverage, 490, 652 GIR_Done, 653 // Label 89: @719 654 GIM_Reject, 655 // Label 87: @720 656 GIM_Reject, 657 // Label 85: @721 658 GIM_Try, /*On fail goto*//*Label 90*/ 752, // Rule ID 489 // 659 GIM_CheckFeatures, GIFBS_HasStdExtM, 660 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 661 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 662 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 663 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 665 // (srem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (REM:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 666 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REM, 667 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 668 // GIR_Coverage, 489, 669 GIR_Done, 670 // Label 90: @752 671 GIM_Reject, 672 // Label 86: @753 673 GIM_Reject, 674 // Label 6: @754 675 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 93*/ 840, 676 /*GILLT_s32*//*Label 91*/ 762, 677 /*GILLT_s64*//*Label 92*/ 808, 678 // Label 91: @762 679 GIM_Try, /*On fail goto*//*Label 94*/ 807, 680 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 681 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 684 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 685 GIM_Try, /*On fail goto*//*Label 95*/ 795, // Rule ID 491 // 686 GIM_CheckFeatures, GIFBS_HasStdExtM, 687 // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 688 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REMU, 689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 690 // GIR_Coverage, 491, 691 GIR_Done, 692 // Label 95: @795 693 GIM_Try, /*On fail goto*//*Label 96*/ 806, // Rule ID 493 // 694 GIM_CheckFeatures, GIFBS_HasStdExtM, 695 // (urem:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (REMU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 696 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REMU, 697 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 698 // GIR_Coverage, 493, 699 GIR_Done, 700 // Label 96: @806 701 GIM_Reject, 702 // Label 94: @807 703 GIM_Reject, 704 // Label 92: @808 705 GIM_Try, /*On fail goto*//*Label 97*/ 839, // Rule ID 492 // 706 GIM_CheckFeatures, GIFBS_HasStdExtM, 707 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 708 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 710 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 712 // (urem:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (REMU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 713 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::REMU, 714 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 715 // GIR_Coverage, 492, 716 GIR_Done, 717 // Label 97: @839 718 GIM_Reject, 719 // Label 93: @840 720 GIM_Reject, 721 // Label 7: @841 722 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 100*/ 1165, 723 /*GILLT_s32*//*Label 98*/ 849, 724 /*GILLT_s64*//*Label 99*/ 1053, 725 // Label 98: @849 726 GIM_Try, /*On fail goto*//*Label 101*/ 1052, 727 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 728 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 729 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 731 GIM_Try, /*On fail goto*//*Label 102*/ 913, // Rule ID 361 // 732 GIM_CheckFeatures, GIFBS_IsRV64, 733 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295, 734 // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }) => (SRLI:{ *:[i32] } (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 32:{ *:[i32] }), 32:{ *:[i32] }) 735 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 736 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI, 737 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 738 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 739 GIR_AddImm, /*InsnID*/1, /*Imm*/32, 740 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 741 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI, 742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 743 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 744 GIR_AddImm, /*InsnID*/0, /*Imm*/32, 745 GIR_EraseFromParent, /*InsnID*/0, 746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 747 // GIR_Coverage, 361, 748 GIR_Done, 749 // Label 102: @913 750 GIM_Try, /*On fail goto*//*Label 103*/ 959, // Rule ID 363 // 751 GIM_CheckFeatures, GIFBS_IsRV64, 752 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295, 753 // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 4294967295:{ *:[i32] }) => (SRLI:{ *:[i32] } (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 32:{ *:[i32] }), 32:{ *:[i32] }) 754 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 755 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI, 756 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 757 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 758 GIR_AddImm, /*InsnID*/1, /*Imm*/32, 759 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 760 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI, 761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 762 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 763 GIR_AddImm, /*InsnID*/0, /*Imm*/32, 764 GIR_EraseFromParent, /*InsnID*/0, 765 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 766 // GIR_Coverage, 363, 767 GIR_Done, 768 // Label 103: @959 769 GIM_Try, /*On fail goto*//*Label 104*/ 992, // Rule ID 50 // 770 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 771 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 772 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 773 // MIs[1] Operand 1 774 // No operand predicates 775 GIM_CheckIsSafeToFold, /*InsnID*/1, 776 // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 777 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI, 778 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 779 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 780 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 781 GIR_EraseFromParent, /*InsnID*/0, 782 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 783 // GIR_Coverage, 50, 784 GIR_Done, 785 // Label 104: @992 786 GIM_Try, /*On fail goto*//*Label 105*/ 1025, // Rule ID 52 // 787 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 788 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 789 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 790 // MIs[1] Operand 1 791 // No operand predicates 792 GIM_CheckIsSafeToFold, /*InsnID*/1, 793 // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ANDI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 794 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI, 795 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 796 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 797 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 798 GIR_EraseFromParent, /*InsnID*/0, 799 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 800 // GIR_Coverage, 52, 801 GIR_Done, 802 // Label 105: @1025 803 GIM_Try, /*On fail goto*//*Label 106*/ 1038, // Rule ID 47 // 804 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 805 // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 806 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND, 807 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 808 // GIR_Coverage, 47, 809 GIR_Done, 810 // Label 106: @1038 811 GIM_Try, /*On fail goto*//*Label 107*/ 1051, // Rule ID 49 // 812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 813 // (and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (AND:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 814 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND, 815 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 816 // GIR_Coverage, 49, 817 GIR_Done, 818 // Label 107: @1051 819 GIM_Reject, 820 // Label 101: @1052 821 GIM_Reject, 822 // Label 99: @1053 823 GIM_Try, /*On fail goto*//*Label 108*/ 1164, 824 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 825 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 828 GIM_Try, /*On fail goto*//*Label 109*/ 1117, // Rule ID 362 // 829 GIM_CheckFeatures, GIFBS_IsRV64, 830 GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 4294967295, 831 // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 4294967295:{ *:[i64] }) => (SRLI:{ *:[i64] } (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 32:{ *:[i64] }), 32:{ *:[i64] }) 832 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 833 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLLI, 834 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 835 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1 836 GIR_AddImm, /*InsnID*/1, /*Imm*/32, 837 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 838 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI, 839 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 840 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 841 GIR_AddImm, /*InsnID*/0, /*Imm*/32, 842 GIR_EraseFromParent, /*InsnID*/0, 843 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 844 // GIR_Coverage, 362, 845 GIR_Done, 846 // Label 109: @1117 847 GIM_Try, /*On fail goto*//*Label 110*/ 1150, // Rule ID 51 // 848 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 849 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 850 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 851 // MIs[1] Operand 1 852 // No operand predicates 853 GIM_CheckIsSafeToFold, /*InsnID*/1, 854 // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) => (ANDI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 855 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ANDI, 856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 858 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 859 GIR_EraseFromParent, /*InsnID*/0, 860 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 861 // GIR_Coverage, 51, 862 GIR_Done, 863 // Label 110: @1150 864 GIM_Try, /*On fail goto*//*Label 111*/ 1163, // Rule ID 48 // 865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 866 // (and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (AND:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 867 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AND, 868 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 869 // GIR_Coverage, 48, 870 GIR_Done, 871 // Label 111: @1163 872 GIM_Reject, 873 // Label 108: @1164 874 GIM_Reject, 875 // Label 100: @1165 876 GIM_Reject, 877 // Label 8: @1166 878 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 114*/ 1352, 879 /*GILLT_s32*//*Label 112*/ 1174, 880 /*GILLT_s64*//*Label 113*/ 1286, 881 // Label 112: @1174 882 GIM_Try, /*On fail goto*//*Label 115*/ 1285, 883 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 884 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 885 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 887 GIM_Try, /*On fail goto*//*Label 116*/ 1225, // Rule ID 44 // 888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 889 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 890 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 891 // MIs[1] Operand 1 892 // No operand predicates 893 GIM_CheckIsSafeToFold, /*InsnID*/1, 894 // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI, 896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 898 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 899 GIR_EraseFromParent, /*InsnID*/0, 900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 901 // GIR_Coverage, 44, 902 GIR_Done, 903 // Label 116: @1225 904 GIM_Try, /*On fail goto*//*Label 117*/ 1258, // Rule ID 46 // 905 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 906 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 907 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 908 // MIs[1] Operand 1 909 // No operand predicates 910 GIM_CheckIsSafeToFold, /*InsnID*/1, 911 // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (ORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 912 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI, 913 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 914 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 915 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 916 GIR_EraseFromParent, /*InsnID*/0, 917 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 918 // GIR_Coverage, 46, 919 GIR_Done, 920 // Label 117: @1258 921 GIM_Try, /*On fail goto*//*Label 118*/ 1271, // Rule ID 41 // 922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 923 // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 924 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::OR, 925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 926 // GIR_Coverage, 41, 927 GIR_Done, 928 // Label 118: @1271 929 GIM_Try, /*On fail goto*//*Label 119*/ 1284, // Rule ID 43 // 930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 931 // (or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (OR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 932 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::OR, 933 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 934 // GIR_Coverage, 43, 935 GIR_Done, 936 // Label 119: @1284 937 GIM_Reject, 938 // Label 115: @1285 939 GIM_Reject, 940 // Label 113: @1286 941 GIM_Try, /*On fail goto*//*Label 120*/ 1351, 942 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 943 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 944 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 946 GIM_Try, /*On fail goto*//*Label 121*/ 1337, // Rule ID 45 // 947 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 948 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 949 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 950 // MIs[1] Operand 1 951 // No operand predicates 952 GIM_CheckIsSafeToFold, /*InsnID*/1, 953 // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) => (ORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ORI, 955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 957 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 958 GIR_EraseFromParent, /*InsnID*/0, 959 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 960 // GIR_Coverage, 45, 961 GIR_Done, 962 // Label 121: @1337 963 GIM_Try, /*On fail goto*//*Label 122*/ 1350, // Rule ID 42 // 964 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 965 // (or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (OR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 966 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::OR, 967 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 968 // GIR_Coverage, 42, 969 GIR_Done, 970 // Label 122: @1350 971 GIM_Reject, 972 // Label 120: @1351 973 GIM_Reject, 974 // Label 114: @1352 975 GIM_Reject, 976 // Label 9: @1353 977 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 125*/ 1539, 978 /*GILLT_s32*//*Label 123*/ 1361, 979 /*GILLT_s64*//*Label 124*/ 1473, 980 // Label 123: @1361 981 GIM_Try, /*On fail goto*//*Label 126*/ 1472, 982 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 983 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 984 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 986 GIM_Try, /*On fail goto*//*Label 127*/ 1412, // Rule ID 56 // 987 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 988 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 989 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 990 // MIs[1] Operand 1 991 // No operand predicates 992 GIM_CheckIsSafeToFold, /*InsnID*/1, 993 // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 994 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 995 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 996 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 997 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 998 GIR_EraseFromParent, /*InsnID*/0, 999 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1000 // GIR_Coverage, 56, 1001 GIR_Done, 1002 // Label 127: @1412 1003 GIM_Try, /*On fail goto*//*Label 128*/ 1445, // Rule ID 58 // 1004 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1005 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1006 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 1007 // MIs[1] Operand 1 1008 // No operand predicates 1009 GIM_CheckIsSafeToFold, /*InsnID*/1, 1010 // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) => (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1011 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 1012 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 1014 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 1015 GIR_EraseFromParent, /*InsnID*/0, 1016 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1017 // GIR_Coverage, 58, 1018 GIR_Done, 1019 // Label 128: @1445 1020 GIM_Try, /*On fail goto*//*Label 129*/ 1458, // Rule ID 53 // 1021 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 1022 // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 1023 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::XOR, 1024 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1025 // GIR_Coverage, 53, 1026 GIR_Done, 1027 // Label 129: @1458 1028 GIM_Try, /*On fail goto*//*Label 130*/ 1471, // Rule ID 55 // 1029 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 1030 // (xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 1031 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::XOR, 1032 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1033 // GIR_Coverage, 55, 1034 GIR_Done, 1035 // Label 130: @1471 1036 GIM_Reject, 1037 // Label 126: @1472 1038 GIM_Reject, 1039 // Label 124: @1473 1040 GIM_Try, /*On fail goto*//*Label 131*/ 1538, 1041 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1042 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 1043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1044 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1045 GIM_Try, /*On fail goto*//*Label 132*/ 1524, // Rule ID 57 // 1046 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 1047 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 1048 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 1049 // MIs[1] Operand 1 1050 // No operand predicates 1051 GIM_CheckIsSafeToFold, /*InsnID*/1, 1052 // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) => (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 1053 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 1054 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1055 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 1056 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 1057 GIR_EraseFromParent, /*InsnID*/0, 1058 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1059 // GIR_Coverage, 57, 1060 GIR_Done, 1061 // Label 132: @1524 1062 GIM_Try, /*On fail goto*//*Label 133*/ 1537, // Rule ID 54 // 1063 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 1064 // (xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 1065 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::XOR, 1066 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1067 // GIR_Coverage, 54, 1068 GIR_Done, 1069 // Label 133: @1537 1070 GIM_Reject, 1071 // Label 131: @1538 1072 GIM_Reject, 1073 // Label 125: @1539 1074 GIM_Reject, 1075 // Label 10: @1540 1076 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 136*/ 1826, 1077 /*GILLT_s32*//*Label 134*/ 1548, 1078 /*GILLT_s64*//*Label 135*/ 1710, 1079 // Label 134: @1548 1080 GIM_Try, /*On fail goto*//*Label 137*/ 1571, // Rule ID 1067 // 1081 GIM_CheckFeatures, GIFBS_HasStdExtF, 1082 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 1084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1085 // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FMV_W_X:{ *:[f32] } GPR:{ *:[i32] }:$rs1) 1086 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_W_X, 1087 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1088 // GIR_Coverage, 1067, 1089 GIR_Done, 1090 // Label 137: @1571 1091 GIM_Try, /*On fail goto*//*Label 138*/ 1594, // Rule ID 1068 // 1092 GIM_CheckFeatures, GIFBS_HasStdExtF, 1093 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 1095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1096 // (bitconvert:{ *:[f32] } GPR:{ *:[i64] }:$rs1) => (FMV_W_X:{ *:[f32] } GPR:{ *:[i64] }:$rs1) 1097 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_W_X, 1098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1099 // GIR_Coverage, 1068, 1100 GIR_Done, 1101 // Label 138: @1594 1102 GIM_Try, /*On fail goto*//*Label 139*/ 1617, // Rule ID 1069 // 1103 GIM_CheckFeatures, GIFBS_HasStdExtF, 1104 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 1106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1107 // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$rs1) => (FMV_W_X:{ *:[f32] } GPR:{ *:[i32] }:$rs1) 1108 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_W_X, 1109 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1110 // GIR_Coverage, 1069, 1111 GIR_Done, 1112 // Label 139: @1617 1113 GIM_Try, /*On fail goto*//*Label 140*/ 1640, // Rule ID 1070 // 1114 GIM_CheckFeatures, GIFBS_HasStdExtF, 1115 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1116 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 1118 // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FMV_X_W:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) 1119 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_W, 1120 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1121 // GIR_Coverage, 1070, 1122 GIR_Done, 1123 // Label 140: @1640 1124 GIM_Try, /*On fail goto*//*Label 141*/ 1663, // Rule ID 1072 // 1125 GIM_CheckFeatures, GIFBS_HasStdExtF, 1126 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 1129 // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) => (FMV_X_W:{ *:[i32] } FPR32:{ *:[f32] }:$rs1) 1130 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_W, 1131 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1132 // GIR_Coverage, 1072, 1133 GIR_Done, 1134 // Label 141: @1663 1135 GIM_Try, /*On fail goto*//*Label 142*/ 1686, // Rule ID 1318 // 1136 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 1137 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1138 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 1140 // (bitconvert:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FMV_X_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) 1141 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_D, 1142 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1143 // GIR_Coverage, 1318, 1144 GIR_Done, 1145 // Label 142: @1686 1146 GIM_Try, /*On fail goto*//*Label 143*/ 1709, // Rule ID 1320 // 1147 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 1148 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1149 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 1151 // (bitconvert:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FMV_X_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) 1152 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_D, 1153 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1154 // GIR_Coverage, 1320, 1155 GIR_Done, 1156 // Label 143: @1709 1157 GIM_Reject, 1158 // Label 135: @1710 1159 GIM_Try, /*On fail goto*//*Label 144*/ 1733, // Rule ID 1071 // 1160 GIM_CheckFeatures, GIFBS_HasStdExtF, 1161 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 1164 // (bitconvert:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) => (FMV_X_W:{ *:[i64] } FPR32:{ *:[f32] }:$rs1) 1165 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_W, 1166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1167 // GIR_Coverage, 1071, 1168 GIR_Done, 1169 // Label 144: @1733 1170 GIM_Try, /*On fail goto*//*Label 145*/ 1756, // Rule ID 1315 // 1171 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 1172 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 1174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1175 // (bitconvert:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FMV_D_X:{ *:[f64] } GPR:{ *:[i32] }:$rs1) 1176 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_D_X, 1177 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1178 // GIR_Coverage, 1315, 1179 GIR_Done, 1180 // Label 145: @1756 1181 GIM_Try, /*On fail goto*//*Label 146*/ 1779, // Rule ID 1316 // 1182 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 1183 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 1185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1186 // (bitconvert:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FMV_D_X:{ *:[f64] } GPR:{ *:[i64] }:$rs1) 1187 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_D_X, 1188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1189 // GIR_Coverage, 1316, 1190 GIR_Done, 1191 // Label 146: @1779 1192 GIM_Try, /*On fail goto*//*Label 147*/ 1802, // Rule ID 1317 // 1193 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 1194 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 1195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 1196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1197 // (bitconvert:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FMV_D_X:{ *:[f64] } GPR:{ *:[i32] }:$rs1) 1198 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_D_X, 1199 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1200 // GIR_Coverage, 1317, 1201 GIR_Done, 1202 // Label 147: @1802 1203 GIM_Try, /*On fail goto*//*Label 148*/ 1825, // Rule ID 1319 // 1204 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 1205 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 1206 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 1208 // (bitconvert:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FMV_X_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) 1209 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FMV_X_D, 1210 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1211 // GIR_Coverage, 1319, 1212 GIR_Done, 1213 // Label 148: @1825 1214 GIM_Reject, 1215 // Label 136: @1826 1216 GIM_Reject, 1217 // Label 11: @1827 1218 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 151*/ 1917, 1219 /*GILLT_s32*//*Label 149*/ 1835, 1220 /*GILLT_s64*//*Label 150*/ 1889, 1221 // Label 149: @1835 1222 GIM_Try, /*On fail goto*//*Label 152*/ 1888, 1223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1224 GIM_Try, /*On fail goto*//*Label 153*/ 1864, // Rule ID 468 // 1225 GIM_CheckFeatures, GIFBS_IsRV64, 1226 // (readcyclecounter:{ *:[i32] }) => (CSRRS:{ *:[i32] } 3072:{ *:[i32] }, X0:{ *:[i32] }) 1227 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CSRRS, 1228 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1229 GIR_AddImm, /*InsnID*/0, /*Imm*/3072, 1230 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 1231 GIR_EraseFromParent, /*InsnID*/0, 1232 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1233 // GIR_Coverage, 468, 1234 GIR_Done, 1235 // Label 153: @1864 1236 GIM_Try, /*On fail goto*//*Label 154*/ 1887, // Rule ID 470 // 1237 GIM_CheckFeatures, GIFBS_IsRV64, 1238 // (readcyclecounter:{ *:[i32] }) => (CSRRS:{ *:[i32] } 3072:{ *:[i32] }, X0:{ *:[i32] }) 1239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CSRRS, 1240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1241 GIR_AddImm, /*InsnID*/0, /*Imm*/3072, 1242 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 1243 GIR_EraseFromParent, /*InsnID*/0, 1244 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1245 // GIR_Coverage, 470, 1246 GIR_Done, 1247 // Label 154: @1887 1248 GIM_Reject, 1249 // Label 152: @1888 1250 GIM_Reject, 1251 // Label 150: @1889 1252 GIM_Try, /*On fail goto*//*Label 155*/ 1916, // Rule ID 469 // 1253 GIM_CheckFeatures, GIFBS_IsRV64, 1254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1255 // (readcyclecounter:{ *:[i64] }) => (CSRRS:{ *:[i64] } 3072:{ *:[i64] }, X0:{ *:[i64] }) 1256 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::CSRRS, 1257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1258 GIR_AddImm, /*InsnID*/0, /*Imm*/3072, 1259 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 1260 GIR_EraseFromParent, /*InsnID*/0, 1261 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1262 // GIR_Coverage, 469, 1263 GIR_Done, 1264 // Label 155: @1916 1265 GIM_Reject, 1266 // Label 151: @1917 1267 GIM_Reject, 1268 // Label 12: @1918 1269 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 158*/ 6035, 1270 /*GILLT_s32*//*Label 156*/ 1926, 1271 /*GILLT_s64*//*Label 157*/ 4542, 1272 // Label 156: @1926 1273 GIM_Try, /*On fail goto*//*Label 159*/ 2003, // Rule ID 581 // 1274 GIM_CheckFeatures, GIFBS_HasStdExtA, 1275 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 1276 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1278 // MIs[0] Operand 1 1279 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1280 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1281 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1282 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1283 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1284 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1285 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1286 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1287 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1288 // MIs[2] Operand 1 1289 // No operand predicates 1290 GIM_CheckIsSafeToFold, /*InsnID*/1, 1291 GIM_CheckIsSafeToFold, /*InsnID*/2, 1292 // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1293 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 1294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1296 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1297 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1298 GIR_EraseFromParent, /*InsnID*/0, 1299 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1300 // GIR_Coverage, 581, 1301 GIR_Done, 1302 // Label 159: @2003 1303 GIM_Try, /*On fail goto*//*Label 160*/ 2080, // Rule ID 583 // 1304 GIM_CheckFeatures, GIFBS_HasStdExtA, 1305 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 1306 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1308 // MIs[0] Operand 1 1309 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1310 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1311 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1312 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1313 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1314 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1315 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1316 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1317 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1318 // MIs[2] Operand 1 1319 // No operand predicates 1320 GIM_CheckIsSafeToFold, /*InsnID*/1, 1321 GIM_CheckIsSafeToFold, /*InsnID*/2, 1322 // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1323 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 1324 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1326 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1327 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1328 GIR_EraseFromParent, /*InsnID*/0, 1329 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1330 // GIR_Coverage, 583, 1331 GIR_Done, 1332 // Label 160: @2080 1333 GIM_Try, /*On fail goto*//*Label 161*/ 2157, // Rule ID 596 // 1334 GIM_CheckFeatures, GIFBS_HasStdExtA, 1335 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 1336 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1338 // MIs[0] Operand 1 1339 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1340 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1341 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1342 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1343 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1344 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1345 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1346 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1347 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1348 // MIs[2] Operand 1 1349 // No operand predicates 1350 GIM_CheckIsSafeToFold, /*InsnID*/1, 1351 GIM_CheckIsSafeToFold, /*InsnID*/2, 1352 // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 1354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1355 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1356 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1357 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1358 GIR_EraseFromParent, /*InsnID*/0, 1359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1360 // GIR_Coverage, 596, 1361 GIR_Done, 1362 // Label 161: @2157 1363 GIM_Try, /*On fail goto*//*Label 162*/ 2234, // Rule ID 598 // 1364 GIM_CheckFeatures, GIFBS_HasStdExtA, 1365 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 1366 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1368 // MIs[0] Operand 1 1369 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1370 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1371 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1372 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1373 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1374 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1375 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1376 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1377 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1378 // MIs[2] Operand 1 1379 // No operand predicates 1380 GIM_CheckIsSafeToFold, /*InsnID*/1, 1381 GIM_CheckIsSafeToFold, /*InsnID*/2, 1382 // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1383 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 1384 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1386 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1387 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1388 GIR_EraseFromParent, /*InsnID*/0, 1389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1390 // GIR_Coverage, 598, 1391 GIR_Done, 1392 // Label 162: @2234 1393 GIM_Try, /*On fail goto*//*Label 163*/ 2311, // Rule ID 611 // 1394 GIM_CheckFeatures, GIFBS_HasStdExtA, 1395 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 1396 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1398 // MIs[0] Operand 1 1399 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1400 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1401 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1402 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1403 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1404 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1405 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1406 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1407 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1408 // MIs[2] Operand 1 1409 // No operand predicates 1410 GIM_CheckIsSafeToFold, /*InsnID*/1, 1411 GIM_CheckIsSafeToFold, /*InsnID*/2, 1412 // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1413 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 1414 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1415 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1416 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1417 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1418 GIR_EraseFromParent, /*InsnID*/0, 1419 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1420 // GIR_Coverage, 611, 1421 GIR_Done, 1422 // Label 163: @2311 1423 GIM_Try, /*On fail goto*//*Label 164*/ 2388, // Rule ID 613 // 1424 GIM_CheckFeatures, GIFBS_HasStdExtA, 1425 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 1426 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1428 // MIs[0] Operand 1 1429 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1430 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1431 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1432 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1433 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1434 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1435 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1436 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1437 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1438 // MIs[2] Operand 1 1439 // No operand predicates 1440 GIM_CheckIsSafeToFold, /*InsnID*/1, 1441 GIM_CheckIsSafeToFold, /*InsnID*/2, 1442 // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1443 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 1444 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1445 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1446 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1447 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1448 GIR_EraseFromParent, /*InsnID*/0, 1449 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1450 // GIR_Coverage, 613, 1451 GIR_Done, 1452 // Label 164: @2388 1453 GIM_Try, /*On fail goto*//*Label 165*/ 2465, // Rule ID 854 // 1454 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 1455 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 1456 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1458 // MIs[0] Operand 1 1459 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1460 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1461 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1462 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1463 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1464 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1465 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1466 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1467 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1468 // MIs[2] Operand 1 1469 // No operand predicates 1470 GIM_CheckIsSafeToFold, /*InsnID*/1, 1471 GIM_CheckIsSafeToFold, /*InsnID*/2, 1472 // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1473 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 1474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1476 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1477 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1478 GIR_EraseFromParent, /*InsnID*/0, 1479 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1480 // GIR_Coverage, 854, 1481 GIR_Done, 1482 // Label 165: @2465 1483 GIM_Try, /*On fail goto*//*Label 166*/ 2542, // Rule ID 856 // 1484 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 1485 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 1486 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1488 // MIs[0] Operand 1 1489 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1490 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1491 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1492 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1493 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1494 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1495 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1496 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1497 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1498 // MIs[2] Operand 1 1499 // No operand predicates 1500 GIM_CheckIsSafeToFold, /*InsnID*/1, 1501 GIM_CheckIsSafeToFold, /*InsnID*/2, 1502 // (atomic_load:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1503 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 1504 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1505 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1506 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1507 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1508 GIR_EraseFromParent, /*InsnID*/0, 1509 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1510 // GIR_Coverage, 856, 1511 GIR_Done, 1512 // Label 166: @2542 1513 GIM_Try, /*On fail goto*//*Label 167*/ 2619, // Rule ID 264 // 1514 GIM_CheckFeatures, GIFBS_IsRV32, 1515 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1516 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1518 // MIs[0] Operand 1 1519 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1520 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1521 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1522 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1523 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1524 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1525 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1526 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1527 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1528 // MIs[2] Operand 1 1529 // No operand predicates 1530 GIM_CheckIsSafeToFold, /*InsnID*/1, 1531 GIM_CheckIsSafeToFold, /*InsnID*/2, 1532 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1533 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 1534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1536 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1537 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1538 GIR_EraseFromParent, /*InsnID*/0, 1539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1540 // GIR_Coverage, 264, 1541 GIR_Done, 1542 // Label 167: @2619 1543 GIM_Try, /*On fail goto*//*Label 168*/ 2696, // Rule ID 266 // 1544 GIM_CheckFeatures, GIFBS_IsRV32, 1545 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1546 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1548 // MIs[0] Operand 1 1549 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1550 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1551 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1552 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1553 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1554 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1555 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1556 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1557 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1558 // MIs[2] Operand 1 1559 // No operand predicates 1560 GIM_CheckIsSafeToFold, /*InsnID*/1, 1561 GIM_CheckIsSafeToFold, /*InsnID*/2, 1562 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1563 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 1564 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1565 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1566 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1567 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1568 GIR_EraseFromParent, /*InsnID*/0, 1569 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1570 // GIR_Coverage, 266, 1571 GIR_Done, 1572 // Label 168: @2696 1573 GIM_Try, /*On fail goto*//*Label 169*/ 2773, // Rule ID 429 // 1574 GIM_CheckFeatures, GIFBS_IsRV64, 1575 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1576 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1578 // MIs[0] Operand 1 1579 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1580 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1581 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1582 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1583 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1584 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1585 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1586 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1587 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1588 // MIs[2] Operand 1 1589 // No operand predicates 1590 GIM_CheckIsSafeToFold, /*InsnID*/1, 1591 GIM_CheckIsSafeToFold, /*InsnID*/2, 1592 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1593 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 1594 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1595 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1596 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1597 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1598 GIR_EraseFromParent, /*InsnID*/0, 1599 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1600 // GIR_Coverage, 429, 1601 GIR_Done, 1602 // Label 169: @2773 1603 GIM_Try, /*On fail goto*//*Label 170*/ 2850, // Rule ID 431 // 1604 GIM_CheckFeatures, GIFBS_IsRV64, 1605 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1606 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1608 // MIs[0] Operand 1 1609 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1610 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1611 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1612 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1613 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1614 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1615 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1616 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1617 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1618 // MIs[2] Operand 1 1619 // No operand predicates 1620 GIM_CheckIsSafeToFold, /*InsnID*/1, 1621 GIM_CheckIsSafeToFold, /*InsnID*/2, 1622 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1623 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 1624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1626 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1627 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1628 GIR_EraseFromParent, /*InsnID*/0, 1629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1630 // GIR_Coverage, 431, 1631 GIR_Done, 1632 // Label 170: @2850 1633 GIM_Try, /*On fail goto*//*Label 171*/ 2927, // Rule ID 1136 // 1634 GIM_CheckFeatures, GIFBS_HasStdExtF, 1635 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1636 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 1638 // MIs[0] Operand 1 1639 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1640 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1641 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1642 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1643 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1644 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1645 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1646 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1647 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1648 // MIs[2] Operand 1 1649 // No operand predicates 1650 GIM_CheckIsSafeToFold, /*InsnID*/1, 1651 GIM_CheckIsSafeToFold, /*InsnID*/2, 1652 // (ld:{ *:[f32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1653 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW, 1654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1655 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1656 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1657 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1658 GIR_EraseFromParent, /*InsnID*/0, 1659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1660 // GIR_Coverage, 1136, 1661 GIR_Done, 1662 // Label 171: @2927 1663 GIM_Try, /*On fail goto*//*Label 172*/ 3004, // Rule ID 1137 // 1664 GIM_CheckFeatures, GIFBS_HasStdExtF, 1665 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1666 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 1668 // MIs[0] Operand 1 1669 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 1670 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1671 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1672 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 1673 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 1674 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1675 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1676 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1677 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1678 // MIs[2] Operand 1 1679 // No operand predicates 1680 GIM_CheckIsSafeToFold, /*InsnID*/1, 1681 GIM_CheckIsSafeToFold, /*InsnID*/2, 1682 // (ld:{ *:[f32] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 1683 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW, 1684 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1685 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1686 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1687 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1688 GIR_EraseFromParent, /*InsnID*/0, 1689 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1690 // GIR_Coverage, 1137, 1691 GIR_Done, 1692 // Label 172: @3004 1693 GIM_Try, /*On fail goto*//*Label 173*/ 3081, // Rule ID 1138 // 1694 GIM_CheckFeatures, GIFBS_HasStdExtF, 1695 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1696 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 1698 // MIs[0] Operand 1 1699 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1700 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1701 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1702 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1703 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1704 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1705 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1706 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1707 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1708 // MIs[2] Operand 1 1709 // No operand predicates 1710 GIM_CheckIsSafeToFold, /*InsnID*/1, 1711 GIM_CheckIsSafeToFold, /*InsnID*/2, 1712 // (ld:{ *:[f32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1713 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW, 1714 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1716 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1717 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1718 GIR_EraseFromParent, /*InsnID*/0, 1719 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1720 // GIR_Coverage, 1138, 1721 GIR_Done, 1722 // Label 173: @3081 1723 GIM_Try, /*On fail goto*//*Label 174*/ 3160, // Rule ID 219 // 1724 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1725 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 1726 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1728 // MIs[0] Operand 1 1729 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1730 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1731 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1732 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1733 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1734 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1735 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1736 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1737 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1738 // MIs[2] Operand 1 1739 // No operand predicates 1740 GIM_CheckIsSafeToFold, /*InsnID*/1, 1741 GIM_CheckIsSafeToFold, /*InsnID*/2, 1742 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 1744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1746 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1747 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1748 GIR_EraseFromParent, /*InsnID*/0, 1749 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1750 // GIR_Coverage, 219, 1751 GIR_Done, 1752 // Label 174: @3160 1753 GIM_Try, /*On fail goto*//*Label 175*/ 3239, // Rule ID 221 // 1754 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1755 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 1756 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1758 // MIs[0] Operand 1 1759 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1760 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1761 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1762 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1763 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1764 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1765 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1766 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1767 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1768 // MIs[2] Operand 1 1769 // No operand predicates 1770 GIM_CheckIsSafeToFold, /*InsnID*/1, 1771 GIM_CheckIsSafeToFold, /*InsnID*/2, 1772 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 1774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1776 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1777 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1778 GIR_EraseFromParent, /*InsnID*/0, 1779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1780 // GIR_Coverage, 221, 1781 GIR_Done, 1782 // Label 175: @3239 1783 GIM_Try, /*On fail goto*//*Label 176*/ 3318, // Rule ID 249 // 1784 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1785 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 1786 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1788 // MIs[0] Operand 1 1789 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1790 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1791 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1792 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1793 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1794 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1795 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1796 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1797 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1798 // MIs[2] Operand 1 1799 // No operand predicates 1800 GIM_CheckIsSafeToFold, /*InsnID*/1, 1801 GIM_CheckIsSafeToFold, /*InsnID*/2, 1802 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1803 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 1804 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1805 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1806 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1807 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1808 GIR_EraseFromParent, /*InsnID*/0, 1809 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1810 // GIR_Coverage, 249, 1811 GIR_Done, 1812 // Label 176: @3318 1813 GIM_Try, /*On fail goto*//*Label 177*/ 3397, // Rule ID 251 // 1814 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1815 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 1816 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1818 // MIs[0] Operand 1 1819 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1821 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1822 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1823 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1824 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1825 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1826 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1827 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1828 // MIs[2] Operand 1 1829 // No operand predicates 1830 GIM_CheckIsSafeToFold, /*InsnID*/1, 1831 GIM_CheckIsSafeToFold, /*InsnID*/2, 1832 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 1834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1836 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1837 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1838 GIR_EraseFromParent, /*InsnID*/0, 1839 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1840 // GIR_Coverage, 251, 1841 GIR_Done, 1842 // Label 177: @3397 1843 GIM_Try, /*On fail goto*//*Label 178*/ 3478, // Rule ID 399 // 1844 GIM_CheckFeatures, GIFBS_IsRV64, 1845 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1846 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 1847 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1849 // MIs[0] Operand 1 1850 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1851 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1852 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1853 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1854 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1855 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1856 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1857 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1858 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1859 // MIs[2] Operand 1 1860 // No operand predicates 1861 GIM_CheckIsSafeToFold, /*InsnID*/1, 1862 GIM_CheckIsSafeToFold, /*InsnID*/2, 1863 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1864 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 1865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1866 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1867 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1868 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1869 GIR_EraseFromParent, /*InsnID*/0, 1870 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1871 // GIR_Coverage, 399, 1872 GIR_Done, 1873 // Label 178: @3478 1874 GIM_Try, /*On fail goto*//*Label 179*/ 3559, // Rule ID 401 // 1875 GIM_CheckFeatures, GIFBS_IsRV64, 1876 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 1877 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 1878 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 1879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1880 // MIs[0] Operand 1 1881 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1882 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 1883 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 1884 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 1885 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 1886 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1887 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 1888 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 1889 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 1890 // MIs[2] Operand 1 1891 // No operand predicates 1892 GIM_CheckIsSafeToFold, /*InsnID*/1, 1893 GIM_CheckIsSafeToFold, /*InsnID*/2, 1894 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 1895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 1896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 1898 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 1899 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 1900 GIR_EraseFromParent, /*InsnID*/0, 1901 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1902 // GIR_Coverage, 401, 1903 GIR_Done, 1904 // Label 179: @3559 1905 GIM_Try, /*On fail goto*//*Label 180*/ 3605, // Rule ID 575 // 1906 GIM_CheckFeatures, GIFBS_HasStdExtA, 1907 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 1908 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1910 // MIs[0] rs1 1911 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1913 // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 1914 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 1915 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1916 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 1917 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 1918 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 1919 GIR_EraseFromParent, /*InsnID*/0, 1920 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1921 // GIR_Coverage, 575, 1922 GIR_Done, 1923 // Label 180: @3605 1924 GIM_Try, /*On fail goto*//*Label 181*/ 3651, // Rule ID 577 // 1925 GIM_CheckFeatures, GIFBS_HasStdExtA, 1926 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 1927 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1928 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1929 // MIs[0] rs1 1930 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1931 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1932 // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 1933 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 1934 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1935 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 1936 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 1937 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 1938 GIR_EraseFromParent, /*InsnID*/0, 1939 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1940 // GIR_Coverage, 577, 1941 GIR_Done, 1942 // Label 181: @3651 1943 GIM_Try, /*On fail goto*//*Label 182*/ 3697, // Rule ID 590 // 1944 GIM_CheckFeatures, GIFBS_HasStdExtA, 1945 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 1946 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1947 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1948 // MIs[0] rs1 1949 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1950 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1951 // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 1952 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 1953 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1954 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 1955 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 1956 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 1957 GIR_EraseFromParent, /*InsnID*/0, 1958 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1959 // GIR_Coverage, 590, 1960 GIR_Done, 1961 // Label 182: @3697 1962 GIM_Try, /*On fail goto*//*Label 183*/ 3743, // Rule ID 592 // 1963 GIM_CheckFeatures, GIFBS_HasStdExtA, 1964 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 1965 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1967 // MIs[0] rs1 1968 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1969 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1970 // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 1971 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 1972 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1973 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 1974 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 1975 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 1976 GIR_EraseFromParent, /*InsnID*/0, 1977 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1978 // GIR_Coverage, 592, 1979 GIR_Done, 1980 // Label 183: @3743 1981 GIM_Try, /*On fail goto*//*Label 184*/ 3789, // Rule ID 605 // 1982 GIM_CheckFeatures, GIFBS_HasStdExtA, 1983 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 1984 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 1985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 1986 // MIs[0] rs1 1987 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 1988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 1989 // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 1990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 1991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 1992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 1993 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 1994 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 1995 GIR_EraseFromParent, /*InsnID*/0, 1996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 1997 // GIR_Coverage, 605, 1998 GIR_Done, 1999 // Label 184: @3789 2000 GIM_Try, /*On fail goto*//*Label 185*/ 3835, // Rule ID 607 // 2001 GIM_CheckFeatures, GIFBS_HasStdExtA, 2002 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 2003 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2005 // MIs[0] rs1 2006 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2007 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2008 // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2009 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2010 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2011 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2012 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2013 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2014 GIR_EraseFromParent, /*InsnID*/0, 2015 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2016 // GIR_Coverage, 607, 2017 GIR_Done, 2018 // Label 185: @3835 2019 GIM_Try, /*On fail goto*//*Label 186*/ 3881, // Rule ID 848 // 2020 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 2021 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 2022 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2024 // MIs[0] rs1 2025 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2027 // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_64>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2028 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 2029 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2030 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2031 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2032 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2033 GIR_EraseFromParent, /*InsnID*/0, 2034 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2035 // GIR_Coverage, 848, 2036 GIR_Done, 2037 // Label 186: @3881 2038 GIM_Try, /*On fail goto*//*Label 187*/ 3927, // Rule ID 850 // 2039 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 2040 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 2041 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2043 // MIs[0] rs1 2044 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2046 // (atomic_load:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_atomic_load_64>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 2048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2050 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2051 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2052 GIR_EraseFromParent, /*InsnID*/0, 2053 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2054 // GIR_Coverage, 850, 2055 GIR_Done, 2056 // Label 187: @3927 2057 GIM_Try, /*On fail goto*//*Label 188*/ 3973, // Rule ID 258 // 2058 GIM_CheckFeatures, GIFBS_IsRV32, 2059 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2060 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2062 // MIs[0] rs1 2063 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2065 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2066 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2067 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2068 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2069 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2070 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2071 GIR_EraseFromParent, /*InsnID*/0, 2072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2073 // GIR_Coverage, 258, 2074 GIR_Done, 2075 // Label 188: @3973 2076 GIM_Try, /*On fail goto*//*Label 189*/ 4019, // Rule ID 260 // 2077 GIM_CheckFeatures, GIFBS_IsRV32, 2078 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2079 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2081 // MIs[0] rs1 2082 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2084 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2085 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2087 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2088 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2089 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2090 GIR_EraseFromParent, /*InsnID*/0, 2091 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2092 // GIR_Coverage, 260, 2093 GIR_Done, 2094 // Label 189: @4019 2095 GIM_Try, /*On fail goto*//*Label 190*/ 4065, // Rule ID 423 // 2096 GIM_CheckFeatures, GIFBS_IsRV64, 2097 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2098 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2100 // MIs[0] rs1 2101 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2103 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2104 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 2105 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2106 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2107 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2108 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2109 GIR_EraseFromParent, /*InsnID*/0, 2110 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2111 // GIR_Coverage, 423, 2112 GIR_Done, 2113 // Label 190: @4065 2114 GIM_Try, /*On fail goto*//*Label 191*/ 4111, // Rule ID 425 // 2115 GIM_CheckFeatures, GIFBS_IsRV64, 2116 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2117 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2119 // MIs[0] rs1 2120 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2122 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2123 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 2124 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2125 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2126 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2127 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2128 GIR_EraseFromParent, /*InsnID*/0, 2129 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2130 // GIR_Coverage, 425, 2131 GIR_Done, 2132 // Label 191: @4111 2133 GIM_Try, /*On fail goto*//*Label 192*/ 4157, // Rule ID 1130 // 2134 GIM_CheckFeatures, GIFBS_HasStdExtF, 2135 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2136 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2137 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 2138 // MIs[0] rs1 2139 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2141 // (ld:{ *:[f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW, 2143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2145 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2146 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2147 GIR_EraseFromParent, /*InsnID*/0, 2148 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2149 // GIR_Coverage, 1130, 2150 GIR_Done, 2151 // Label 192: @4157 2152 GIM_Try, /*On fail goto*//*Label 193*/ 4203, // Rule ID 1131 // 2153 GIM_CheckFeatures, GIFBS_HasStdExtF, 2154 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2155 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2156 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 2157 // MIs[0] rs1 2158 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2160 // (ld:{ *:[f32] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2161 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW, 2162 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2163 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2164 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2165 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2166 GIR_EraseFromParent, /*InsnID*/0, 2167 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2168 // GIR_Coverage, 1131, 2169 GIR_Done, 2170 // Label 193: @4203 2171 GIM_Try, /*On fail goto*//*Label 194*/ 4249, // Rule ID 1132 // 2172 GIM_CheckFeatures, GIFBS_HasStdExtF, 2173 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2174 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2175 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 2176 // MIs[0] rs1 2177 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2179 // (ld:{ *:[f32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLW:{ *:[f32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2180 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLW, 2181 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2182 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2183 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2184 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2185 GIR_EraseFromParent, /*InsnID*/0, 2186 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2187 // GIR_Coverage, 1132, 2188 GIR_Done, 2189 // Label 194: @4249 2190 GIM_Try, /*On fail goto*//*Label 195*/ 4297, // Rule ID 213 // 2191 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2192 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 2193 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2195 // MIs[0] rs1 2196 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2198 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2199 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 2200 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2201 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2202 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2203 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2204 GIR_EraseFromParent, /*InsnID*/0, 2205 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2206 // GIR_Coverage, 213, 2207 GIR_Done, 2208 // Label 195: @4297 2209 GIM_Try, /*On fail goto*//*Label 196*/ 4345, // Rule ID 215 // 2210 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2211 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 2212 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2214 // MIs[0] rs1 2215 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2217 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2218 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 2219 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2220 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2221 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2222 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2223 GIR_EraseFromParent, /*InsnID*/0, 2224 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2225 // GIR_Coverage, 215, 2226 GIR_Done, 2227 // Label 196: @4345 2228 GIM_Try, /*On fail goto*//*Label 197*/ 4393, // Rule ID 243 // 2229 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2230 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 2231 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2233 // MIs[0] rs1 2234 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2235 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2236 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2237 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 2238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2240 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2241 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2242 GIR_EraseFromParent, /*InsnID*/0, 2243 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2244 // GIR_Coverage, 243, 2245 GIR_Done, 2246 // Label 197: @4393 2247 GIM_Try, /*On fail goto*//*Label 198*/ 4441, // Rule ID 245 // 2248 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2249 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 2250 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2252 // MIs[0] rs1 2253 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2255 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2256 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 2257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2259 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2260 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2261 GIR_EraseFromParent, /*InsnID*/0, 2262 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2263 // GIR_Coverage, 245, 2264 GIR_Done, 2265 // Label 198: @4441 2266 GIM_Try, /*On fail goto*//*Label 199*/ 4491, // Rule ID 393 // 2267 GIM_CheckFeatures, GIFBS_IsRV64, 2268 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2269 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 2270 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2272 // MIs[0] rs1 2273 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2274 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2275 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2276 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2277 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2278 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2279 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2280 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2281 GIR_EraseFromParent, /*InsnID*/0, 2282 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2283 // GIR_Coverage, 393, 2284 GIR_Done, 2285 // Label 199: @4491 2286 GIM_Try, /*On fail goto*//*Label 200*/ 4541, // Rule ID 395 // 2287 GIM_CheckFeatures, GIFBS_IsRV64, 2288 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2289 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 2290 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2292 // MIs[0] rs1 2293 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2295 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2296 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2297 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2298 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2299 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2300 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2301 GIR_EraseFromParent, /*InsnID*/0, 2302 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2303 // GIR_Coverage, 395, 2304 GIR_Done, 2305 // Label 200: @4541 2306 GIM_Reject, 2307 // Label 157: @4542 2308 GIM_Try, /*On fail goto*//*Label 201*/ 4619, // Rule ID 582 // 2309 GIM_CheckFeatures, GIFBS_HasStdExtA, 2310 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 2311 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2313 // MIs[0] Operand 1 2314 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2315 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2316 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2317 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2318 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2319 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2320 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2321 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2322 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2323 // MIs[2] Operand 1 2324 // No operand predicates 2325 GIM_CheckIsSafeToFold, /*InsnID*/1, 2326 GIM_CheckIsSafeToFold, /*InsnID*/2, 2327 // (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 2329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2331 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2332 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2333 GIR_EraseFromParent, /*InsnID*/0, 2334 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2335 // GIR_Coverage, 582, 2336 GIR_Done, 2337 // Label 201: @4619 2338 GIM_Try, /*On fail goto*//*Label 202*/ 4696, // Rule ID 597 // 2339 GIM_CheckFeatures, GIFBS_HasStdExtA, 2340 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 2341 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2343 // MIs[0] Operand 1 2344 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2345 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2346 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2347 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2348 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2349 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2350 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2351 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2352 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2353 // MIs[2] Operand 1 2354 // No operand predicates 2355 GIM_CheckIsSafeToFold, /*InsnID*/1, 2356 GIM_CheckIsSafeToFold, /*InsnID*/2, 2357 // (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2358 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 2359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2361 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2362 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2363 GIR_EraseFromParent, /*InsnID*/0, 2364 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2365 // GIR_Coverage, 597, 2366 GIR_Done, 2367 // Label 202: @4696 2368 GIM_Try, /*On fail goto*//*Label 203*/ 4773, // Rule ID 612 // 2369 GIM_CheckFeatures, GIFBS_HasStdExtA, 2370 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 2371 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2373 // MIs[0] Operand 1 2374 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2375 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2376 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2377 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2378 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2379 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2380 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2381 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2382 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2383 // MIs[2] Operand 1 2384 // No operand predicates 2385 GIM_CheckIsSafeToFold, /*InsnID*/1, 2386 GIM_CheckIsSafeToFold, /*InsnID*/2, 2387 // (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2388 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2389 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2390 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2391 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2392 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2393 GIR_EraseFromParent, /*InsnID*/0, 2394 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2395 // GIR_Coverage, 612, 2396 GIR_Done, 2397 // Label 203: @4773 2398 GIM_Try, /*On fail goto*//*Label 204*/ 4850, // Rule ID 855 // 2399 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 2400 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 2401 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2402 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2403 // MIs[0] Operand 1 2404 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2405 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2406 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2407 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2408 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2409 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2410 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2411 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2412 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2413 // MIs[2] Operand 1 2414 // No operand predicates 2415 GIM_CheckIsSafeToFold, /*InsnID*/1, 2416 GIM_CheckIsSafeToFold, /*InsnID*/2, 2417 // (atomic_load:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_atomic_load_64>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2418 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 2419 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2420 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2421 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2422 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2423 GIR_EraseFromParent, /*InsnID*/0, 2424 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2425 // GIR_Coverage, 855, 2426 GIR_Done, 2427 // Label 204: @4850 2428 GIM_Try, /*On fail goto*//*Label 205*/ 4927, // Rule ID 265 // 2429 GIM_CheckFeatures, GIFBS_IsRV32, 2430 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2431 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2432 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2433 // MIs[0] Operand 1 2434 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2435 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2436 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2437 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2438 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2439 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2440 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2441 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2442 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2443 // MIs[2] Operand 1 2444 // No operand predicates 2445 GIM_CheckIsSafeToFold, /*InsnID*/1, 2446 GIM_CheckIsSafeToFold, /*InsnID*/2, 2447 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2448 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2450 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2451 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2452 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2453 GIR_EraseFromParent, /*InsnID*/0, 2454 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2455 // GIR_Coverage, 265, 2456 GIR_Done, 2457 // Label 205: @4927 2458 GIM_Try, /*On fail goto*//*Label 206*/ 5004, // Rule ID 430 // 2459 GIM_CheckFeatures, GIFBS_IsRV64, 2460 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2461 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2462 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2463 // MIs[0] Operand 1 2464 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2465 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2466 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2467 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2468 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2469 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2470 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2471 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2472 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2473 // MIs[2] Operand 1 2474 // No operand predicates 2475 GIM_CheckIsSafeToFold, /*InsnID*/1, 2476 GIM_CheckIsSafeToFold, /*InsnID*/2, 2477 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2478 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 2479 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2480 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2481 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2482 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2483 GIR_EraseFromParent, /*InsnID*/0, 2484 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2485 // GIR_Coverage, 430, 2486 GIR_Done, 2487 // Label 206: @5004 2488 GIM_Try, /*On fail goto*//*Label 207*/ 5081, // Rule ID 1279 // 2489 GIM_CheckFeatures, GIFBS_HasStdExtD, 2490 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2491 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 2493 // MIs[0] Operand 1 2494 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2495 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2496 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2497 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2498 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2499 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2500 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2501 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2502 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2503 // MIs[2] Operand 1 2504 // No operand predicates 2505 GIM_CheckIsSafeToFold, /*InsnID*/1, 2506 GIM_CheckIsSafeToFold, /*InsnID*/2, 2507 // (ld:{ *:[f64] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 2508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD, 2509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2510 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2511 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2512 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2513 GIR_EraseFromParent, /*InsnID*/0, 2514 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2515 // GIR_Coverage, 1279, 2516 GIR_Done, 2517 // Label 207: @5081 2518 GIM_Try, /*On fail goto*//*Label 208*/ 5158, // Rule ID 1280 // 2519 GIM_CheckFeatures, GIFBS_HasStdExtD, 2520 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2521 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 2523 // MIs[0] Operand 1 2524 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2525 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2526 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2527 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2528 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2529 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2530 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2531 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2532 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2533 // MIs[2] Operand 1 2534 // No operand predicates 2535 GIM_CheckIsSafeToFold, /*InsnID*/1, 2536 GIM_CheckIsSafeToFold, /*InsnID*/2, 2537 // (ld:{ *:[f64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2538 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD, 2539 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2540 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2541 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2542 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2543 GIR_EraseFromParent, /*InsnID*/0, 2544 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2545 // GIR_Coverage, 1280, 2546 GIR_Done, 2547 // Label 208: @5158 2548 GIM_Try, /*On fail goto*//*Label 209*/ 5235, // Rule ID 1281 // 2549 GIM_CheckFeatures, GIFBS_HasStdExtD, 2550 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2551 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 2553 // MIs[0] Operand 1 2554 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2555 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2556 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2557 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2558 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2559 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2560 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2561 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2562 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2563 // MIs[2] Operand 1 2564 // No operand predicates 2565 GIM_CheckIsSafeToFold, /*InsnID*/1, 2566 GIM_CheckIsSafeToFold, /*InsnID*/2, 2567 // (ld:{ *:[f64] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 2568 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD, 2569 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2570 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2571 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2572 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2573 GIR_EraseFromParent, /*InsnID*/0, 2574 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2575 // GIR_Coverage, 1281, 2576 GIR_Done, 2577 // Label 209: @5235 2578 GIM_Try, /*On fail goto*//*Label 210*/ 5314, // Rule ID 220 // 2579 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2580 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 2581 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2583 // MIs[0] Operand 1 2584 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2585 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2586 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2587 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2588 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2589 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2590 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2591 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2592 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2593 // MIs[2] Operand 1 2594 // No operand predicates 2595 GIM_CheckIsSafeToFold, /*InsnID*/1, 2596 GIM_CheckIsSafeToFold, /*InsnID*/2, 2597 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2598 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 2599 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2600 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2601 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2602 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2603 GIR_EraseFromParent, /*InsnID*/0, 2604 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2605 // GIR_Coverage, 220, 2606 GIR_Done, 2607 // Label 210: @5314 2608 GIM_Try, /*On fail goto*//*Label 211*/ 5393, // Rule ID 250 // 2609 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2610 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 2611 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2613 // MIs[0] Operand 1 2614 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2615 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2616 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2617 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2618 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2619 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2620 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2621 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2622 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2623 // MIs[2] Operand 1 2624 // No operand predicates 2625 GIM_CheckIsSafeToFold, /*InsnID*/1, 2626 GIM_CheckIsSafeToFold, /*InsnID*/2, 2627 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2628 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 2629 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2631 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2632 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2633 GIR_EraseFromParent, /*InsnID*/0, 2634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2635 // GIR_Coverage, 250, 2636 GIR_Done, 2637 // Label 211: @5393 2638 GIM_Try, /*On fail goto*//*Label 212*/ 5474, // Rule ID 400 // 2639 GIM_CheckFeatures, GIFBS_IsRV64, 2640 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2641 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 2642 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2643 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2644 // MIs[0] Operand 1 2645 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2646 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2647 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2648 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 2649 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 2650 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2651 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2652 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2653 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2654 // MIs[2] Operand 1 2655 // No operand predicates 2656 GIM_CheckIsSafeToFold, /*InsnID*/1, 2657 GIM_CheckIsSafeToFold, /*InsnID*/2, 2658 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 2659 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2660 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2661 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2662 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2663 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2664 GIR_EraseFromParent, /*InsnID*/0, 2665 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2666 // GIR_Coverage, 400, 2667 GIR_Done, 2668 // Label 212: @5474 2669 GIM_Try, /*On fail goto*//*Label 213*/ 5520, // Rule ID 576 // 2670 GIM_CheckFeatures, GIFBS_HasStdExtA, 2671 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 2672 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2673 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2674 // MIs[0] rs1 2675 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2677 // (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2678 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 2679 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2680 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2681 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2682 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2683 GIR_EraseFromParent, /*InsnID*/0, 2684 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2685 // GIR_Coverage, 576, 2686 GIR_Done, 2687 // Label 213: @5520 2688 GIM_Try, /*On fail goto*//*Label 214*/ 5566, // Rule ID 591 // 2689 GIM_CheckFeatures, GIFBS_HasStdExtA, 2690 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 2691 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2692 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2693 // MIs[0] rs1 2694 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2696 // (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2697 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 2698 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2699 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2700 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2701 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2702 GIR_EraseFromParent, /*InsnID*/0, 2703 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2704 // GIR_Coverage, 591, 2705 GIR_Done, 2706 // Label 214: @5566 2707 GIM_Try, /*On fail goto*//*Label 215*/ 5612, // Rule ID 606 // 2708 GIM_CheckFeatures, GIFBS_HasStdExtA, 2709 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 2710 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2711 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2712 // MIs[0] rs1 2713 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2714 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2715 // (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2716 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2717 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2718 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2719 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2720 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2721 GIR_EraseFromParent, /*InsnID*/0, 2722 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2723 // GIR_Coverage, 606, 2724 GIR_Done, 2725 // Label 215: @5612 2726 GIM_Try, /*On fail goto*//*Label 216*/ 5658, // Rule ID 849 // 2727 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 2728 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 2729 GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Unordered, 2730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2731 // MIs[0] rs1 2732 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2734 // (atomic_load:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_atomic_load_64>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2735 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 2736 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2737 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2738 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2739 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2740 GIR_EraseFromParent, /*InsnID*/0, 2741 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2742 // GIR_Coverage, 849, 2743 GIR_Done, 2744 // Label 216: @5658 2745 GIM_Try, /*On fail goto*//*Label 217*/ 5704, // Rule ID 259 // 2746 GIM_CheckFeatures, GIFBS_IsRV32, 2747 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2748 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2750 // MIs[0] rs1 2751 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2752 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2753 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2754 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2755 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2756 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2757 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2758 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2759 GIR_EraseFromParent, /*InsnID*/0, 2760 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2761 // GIR_Coverage, 259, 2762 GIR_Done, 2763 // Label 217: @5704 2764 GIM_Try, /*On fail goto*//*Label 218*/ 5750, // Rule ID 424 // 2765 GIM_CheckFeatures, GIFBS_IsRV64, 2766 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2767 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2768 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2769 // MIs[0] rs1 2770 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2771 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2772 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (LD:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2773 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LD, 2774 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2775 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2776 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2777 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2778 GIR_EraseFromParent, /*InsnID*/0, 2779 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2780 // GIR_Coverage, 424, 2781 GIR_Done, 2782 // Label 218: @5750 2783 GIM_Try, /*On fail goto*//*Label 219*/ 5796, // Rule ID 1273 // 2784 GIM_CheckFeatures, GIFBS_HasStdExtD, 2785 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2786 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2787 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 2788 // MIs[0] rs1 2789 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2791 // (ld:{ *:[f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD, 2793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2795 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2796 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2797 GIR_EraseFromParent, /*InsnID*/0, 2798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2799 // GIR_Coverage, 1273, 2800 GIR_Done, 2801 // Label 219: @5796 2802 GIM_Try, /*On fail goto*//*Label 220*/ 5842, // Rule ID 1274 // 2803 GIM_CheckFeatures, GIFBS_HasStdExtD, 2804 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2805 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2806 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 2807 // MIs[0] rs1 2808 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2810 // (ld:{ *:[f64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD, 2812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2814 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2815 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2816 GIR_EraseFromParent, /*InsnID*/0, 2817 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2818 // GIR_Coverage, 1274, 2819 GIR_Done, 2820 // Label 220: @5842 2821 GIM_Try, /*On fail goto*//*Label 221*/ 5888, // Rule ID 1275 // 2822 GIM_CheckFeatures, GIFBS_HasStdExtD, 2823 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2824 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 2826 // MIs[0] rs1 2827 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2829 // (ld:{ *:[f64] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_load>> => (FLD:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 2830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FLD, 2831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2833 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2834 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2835 GIR_EraseFromParent, /*InsnID*/0, 2836 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2837 // GIR_Coverage, 1275, 2838 GIR_Done, 2839 // Label 221: @5888 2840 GIM_Try, /*On fail goto*//*Label 222*/ 5936, // Rule ID 214 // 2841 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2842 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 2843 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2844 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2845 // MIs[0] rs1 2846 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2848 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2849 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 2850 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2852 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2853 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2854 GIR_EraseFromParent, /*InsnID*/0, 2855 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2856 // GIR_Coverage, 214, 2857 GIR_Done, 2858 // Label 222: @5936 2859 GIM_Try, /*On fail goto*//*Label 223*/ 5984, // Rule ID 244 // 2860 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2861 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 2862 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2864 // MIs[0] rs1 2865 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2867 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2868 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 2869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2870 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2871 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2872 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2873 GIR_EraseFromParent, /*InsnID*/0, 2874 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2875 // GIR_Coverage, 244, 2876 GIR_Done, 2877 // Label 223: @5984 2878 GIM_Try, /*On fail goto*//*Label 224*/ 6034, // Rule ID 394 // 2879 GIM_CheckFeatures, GIFBS_IsRV64, 2880 GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 2881 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 2882 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2883 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2884 // MIs[0] rs1 2885 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 2886 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2887 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 2888 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 2889 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 2891 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 2892 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 2893 GIR_EraseFromParent, /*InsnID*/0, 2894 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2895 // GIR_Coverage, 394, 2896 GIR_Done, 2897 // Label 224: @6034 2898 GIM_Reject, 2899 // Label 158: @6035 2900 GIM_Reject, 2901 // Label 13: @6036 2902 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 227*/ 7129, 2903 /*GILLT_s32*//*Label 225*/ 6044, 2904 /*GILLT_s64*//*Label 226*/ 6767, 2905 // Label 225: @6044 2906 GIM_Try, /*On fail goto*//*Label 228*/ 6119, // Rule ID 204 // 2907 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 2908 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2910 // MIs[0] Operand 1 2911 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2912 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2913 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2914 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2915 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2916 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2917 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2918 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2919 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2920 // MIs[2] Operand 1 2921 // No operand predicates 2922 GIM_CheckIsSafeToFold, /*InsnID*/1, 2923 GIM_CheckIsSafeToFold, /*InsnID*/2, 2924 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 2925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 2926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2928 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2929 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2930 GIR_EraseFromParent, /*InsnID*/0, 2931 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2932 // GIR_Coverage, 204, 2933 GIR_Done, 2934 // Label 228: @6119 2935 GIM_Try, /*On fail goto*//*Label 229*/ 6194, // Rule ID 206 // 2936 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 2937 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2939 // MIs[0] Operand 1 2940 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2941 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2942 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2943 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2944 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2945 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2946 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2947 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2948 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2949 // MIs[2] Operand 1 2950 // No operand predicates 2951 GIM_CheckIsSafeToFold, /*InsnID*/1, 2952 GIM_CheckIsSafeToFold, /*InsnID*/2, 2953 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 2954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 2955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2957 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2958 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2959 GIR_EraseFromParent, /*InsnID*/0, 2960 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2961 // GIR_Coverage, 206, 2962 GIR_Done, 2963 // Label 229: @6194 2964 GIM_Try, /*On fail goto*//*Label 230*/ 6269, // Rule ID 234 // 2965 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 2966 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2968 // MIs[0] Operand 1 2969 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2970 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 2971 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 2972 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 2973 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 2974 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 2975 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 2976 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 2977 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 2978 // MIs[2] Operand 1 2979 // No operand predicates 2980 GIM_CheckIsSafeToFold, /*InsnID*/1, 2981 GIM_CheckIsSafeToFold, /*InsnID*/2, 2982 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 2983 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 2984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 2985 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 2986 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 2987 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 2988 GIR_EraseFromParent, /*InsnID*/0, 2989 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 2990 // GIR_Coverage, 234, 2991 GIR_Done, 2992 // Label 230: @6269 2993 GIM_Try, /*On fail goto*//*Label 231*/ 6344, // Rule ID 236 // 2994 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 2995 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 2996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 2997 // MIs[0] Operand 1 2998 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 2999 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3000 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3001 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3002 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3003 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3004 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3005 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3006 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3007 // MIs[2] Operand 1 3008 // No operand predicates 3009 GIM_CheckIsSafeToFold, /*InsnID*/1, 3010 GIM_CheckIsSafeToFold, /*InsnID*/2, 3011 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3012 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 3013 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3014 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3015 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3016 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3017 GIR_EraseFromParent, /*InsnID*/0, 3018 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3019 // GIR_Coverage, 236, 3020 GIR_Done, 3021 // Label 231: @6344 3022 GIM_Try, /*On fail goto*//*Label 232*/ 6421, // Rule ID 384 // 3023 GIM_CheckFeatures, GIFBS_IsRV64, 3024 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3025 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3026 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3027 // MIs[0] Operand 1 3028 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3029 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3030 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3031 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3032 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3033 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3034 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3035 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3036 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3037 // MIs[2] Operand 1 3038 // No operand predicates 3039 GIM_CheckIsSafeToFold, /*InsnID*/1, 3040 GIM_CheckIsSafeToFold, /*InsnID*/2, 3041 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 3043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3044 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3045 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3046 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3047 GIR_EraseFromParent, /*InsnID*/0, 3048 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3049 // GIR_Coverage, 384, 3050 GIR_Done, 3051 // Label 232: @6421 3052 GIM_Try, /*On fail goto*//*Label 233*/ 6498, // Rule ID 386 // 3053 GIM_CheckFeatures, GIFBS_IsRV64, 3054 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3055 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3057 // MIs[0] Operand 1 3058 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3059 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3060 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3061 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3062 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3063 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3064 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3065 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3066 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3067 // MIs[2] Operand 1 3068 // No operand predicates 3069 GIM_CheckIsSafeToFold, /*InsnID*/1, 3070 GIM_CheckIsSafeToFold, /*InsnID*/2, 3071 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3072 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 3073 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3075 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3076 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3077 GIR_EraseFromParent, /*InsnID*/0, 3078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3079 // GIR_Coverage, 386, 3080 GIR_Done, 3081 // Label 233: @6498 3082 GIM_Try, /*On fail goto*//*Label 234*/ 6542, // Rule ID 198 // 3083 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3084 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3085 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3086 // MIs[0] rs1 3087 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3089 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3090 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 3091 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3092 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3093 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3094 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3095 GIR_EraseFromParent, /*InsnID*/0, 3096 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3097 // GIR_Coverage, 198, 3098 GIR_Done, 3099 // Label 234: @6542 3100 GIM_Try, /*On fail goto*//*Label 235*/ 6586, // Rule ID 200 // 3101 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3102 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3104 // MIs[0] rs1 3105 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3107 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3108 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 3109 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3110 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3111 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3112 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3113 GIR_EraseFromParent, /*InsnID*/0, 3114 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3115 // GIR_Coverage, 200, 3116 GIR_Done, 3117 // Label 235: @6586 3118 GIM_Try, /*On fail goto*//*Label 236*/ 6630, // Rule ID 228 // 3119 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3120 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3122 // MIs[0] rs1 3123 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3125 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3126 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 3127 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3129 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3130 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3131 GIR_EraseFromParent, /*InsnID*/0, 3132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3133 // GIR_Coverage, 228, 3134 GIR_Done, 3135 // Label 236: @6630 3136 GIM_Try, /*On fail goto*//*Label 237*/ 6674, // Rule ID 230 // 3137 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3138 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3140 // MIs[0] rs1 3141 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3143 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3144 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 3145 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3146 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3147 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3148 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3149 GIR_EraseFromParent, /*InsnID*/0, 3150 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3151 // GIR_Coverage, 230, 3152 GIR_Done, 3153 // Label 237: @6674 3154 GIM_Try, /*On fail goto*//*Label 238*/ 6720, // Rule ID 378 // 3155 GIM_CheckFeatures, GIFBS_IsRV64, 3156 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3157 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3159 // MIs[0] rs1 3160 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3162 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3163 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 3164 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3165 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3166 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3167 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3168 GIR_EraseFromParent, /*InsnID*/0, 3169 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3170 // GIR_Coverage, 378, 3171 GIR_Done, 3172 // Label 238: @6720 3173 GIM_Try, /*On fail goto*//*Label 239*/ 6766, // Rule ID 380 // 3174 GIM_CheckFeatures, GIFBS_IsRV64, 3175 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3176 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3178 // MIs[0] rs1 3179 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3181 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3182 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 3183 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3185 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3186 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3187 GIR_EraseFromParent, /*InsnID*/0, 3188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3189 // GIR_Coverage, 380, 3190 GIR_Done, 3191 // Label 239: @6766 3192 GIM_Reject, 3193 // Label 226: @6767 3194 GIM_Try, /*On fail goto*//*Label 240*/ 6842, // Rule ID 205 // 3195 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3196 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3197 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3198 // MIs[0] Operand 1 3199 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3200 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3201 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3202 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3203 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3204 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3205 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3206 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3207 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3208 // MIs[2] Operand 1 3209 // No operand predicates 3210 GIM_CheckIsSafeToFold, /*InsnID*/1, 3211 GIM_CheckIsSafeToFold, /*InsnID*/2, 3212 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 3213 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 3214 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3215 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3216 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3217 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3218 GIR_EraseFromParent, /*InsnID*/0, 3219 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3220 // GIR_Coverage, 205, 3221 GIR_Done, 3222 // Label 240: @6842 3223 GIM_Try, /*On fail goto*//*Label 241*/ 6917, // Rule ID 235 // 3224 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3225 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3227 // MIs[0] Operand 1 3228 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3229 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3230 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3231 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3232 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3233 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3234 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3235 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3236 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3237 // MIs[2] Operand 1 3238 // No operand predicates 3239 GIM_CheckIsSafeToFold, /*InsnID*/1, 3240 GIM_CheckIsSafeToFold, /*InsnID*/2, 3241 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 3242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 3243 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3244 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3245 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3246 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3247 GIR_EraseFromParent, /*InsnID*/0, 3248 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3249 // GIR_Coverage, 235, 3250 GIR_Done, 3251 // Label 241: @6917 3252 GIM_Try, /*On fail goto*//*Label 242*/ 6994, // Rule ID 385 // 3253 GIM_CheckFeatures, GIFBS_IsRV64, 3254 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3255 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3256 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3257 // MIs[0] Operand 1 3258 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3259 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3260 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3261 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3262 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3263 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3264 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3265 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3266 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3267 // MIs[2] Operand 1 3268 // No operand predicates 3269 GIM_CheckIsSafeToFold, /*InsnID*/1, 3270 GIM_CheckIsSafeToFold, /*InsnID*/2, 3271 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 3272 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 3273 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3275 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3276 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3277 GIR_EraseFromParent, /*InsnID*/0, 3278 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3279 // GIR_Coverage, 385, 3280 GIR_Done, 3281 // Label 242: @6994 3282 GIM_Try, /*On fail goto*//*Label 243*/ 7038, // Rule ID 199 // 3283 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3284 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3286 // MIs[0] rs1 3287 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3289 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (LB:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 3290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LB, 3291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3293 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3294 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3295 GIR_EraseFromParent, /*InsnID*/0, 3296 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3297 // GIR_Coverage, 199, 3298 GIR_Done, 3299 // Label 243: @7038 3300 GIM_Try, /*On fail goto*//*Label 244*/ 7082, // Rule ID 229 // 3301 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3302 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3304 // MIs[0] rs1 3305 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3307 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (LH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 3308 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LH, 3309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3310 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3311 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3312 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3313 GIR_EraseFromParent, /*InsnID*/0, 3314 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3315 // GIR_Coverage, 229, 3316 GIR_Done, 3317 // Label 244: @7082 3318 GIM_Try, /*On fail goto*//*Label 245*/ 7128, // Rule ID 379 // 3319 GIM_CheckFeatures, GIFBS_IsRV64, 3320 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3321 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3323 // MIs[0] rs1 3324 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3326 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi32>> => (LW:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 3327 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LW, 3328 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3330 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3331 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3332 GIR_EraseFromParent, /*InsnID*/0, 3333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3334 // GIR_Coverage, 379, 3335 GIR_Done, 3336 // Label 245: @7128 3337 GIM_Reject, 3338 // Label 227: @7129 3339 GIM_Reject, 3340 // Label 14: @7130 3341 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 248*/ 8223, 3342 /*GILLT_s32*//*Label 246*/ 7138, 3343 /*GILLT_s64*//*Label 247*/ 7861, 3344 // Label 246: @7138 3345 GIM_Try, /*On fail goto*//*Label 249*/ 7213, // Rule ID 279 // 3346 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3347 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3348 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3349 // MIs[0] Operand 1 3350 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3351 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3352 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3353 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3354 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3355 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3356 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3357 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3358 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3359 // MIs[2] Operand 1 3360 // No operand predicates 3361 GIM_CheckIsSafeToFold, /*InsnID*/1, 3362 GIM_CheckIsSafeToFold, /*InsnID*/2, 3363 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3364 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU, 3365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3366 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3367 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3368 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3369 GIR_EraseFromParent, /*InsnID*/0, 3370 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3371 // GIR_Coverage, 279, 3372 GIR_Done, 3373 // Label 249: @7213 3374 GIM_Try, /*On fail goto*//*Label 250*/ 7288, // Rule ID 281 // 3375 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3376 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3378 // MIs[0] Operand 1 3379 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3380 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3381 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3382 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3383 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3384 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3385 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3386 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3387 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3388 // MIs[2] Operand 1 3389 // No operand predicates 3390 GIM_CheckIsSafeToFold, /*InsnID*/1, 3391 GIM_CheckIsSafeToFold, /*InsnID*/2, 3392 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3393 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU, 3394 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3396 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3397 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3398 GIR_EraseFromParent, /*InsnID*/0, 3399 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3400 // GIR_Coverage, 281, 3401 GIR_Done, 3402 // Label 250: @7288 3403 GIM_Try, /*On fail goto*//*Label 251*/ 7363, // Rule ID 294 // 3404 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3405 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3407 // MIs[0] Operand 1 3408 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3409 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3410 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3411 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3412 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3413 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3414 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3415 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3416 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3417 // MIs[2] Operand 1 3418 // No operand predicates 3419 GIM_CheckIsSafeToFold, /*InsnID*/1, 3420 GIM_CheckIsSafeToFold, /*InsnID*/2, 3421 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU, 3423 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3425 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3426 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3427 GIR_EraseFromParent, /*InsnID*/0, 3428 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3429 // GIR_Coverage, 294, 3430 GIR_Done, 3431 // Label 251: @7363 3432 GIM_Try, /*On fail goto*//*Label 252*/ 7438, // Rule ID 296 // 3433 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3434 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3436 // MIs[0] Operand 1 3437 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3438 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3439 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3440 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3441 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3442 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3443 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3444 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3445 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3446 // MIs[2] Operand 1 3447 // No operand predicates 3448 GIM_CheckIsSafeToFold, /*InsnID*/1, 3449 GIM_CheckIsSafeToFold, /*InsnID*/2, 3450 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3451 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU, 3452 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3453 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3454 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3455 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3456 GIR_EraseFromParent, /*InsnID*/0, 3457 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3458 // GIR_Coverage, 296, 3459 GIR_Done, 3460 // Label 252: @7438 3461 GIM_Try, /*On fail goto*//*Label 253*/ 7515, // Rule ID 414 // 3462 GIM_CheckFeatures, GIFBS_IsRV64, 3463 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3464 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3466 // MIs[0] Operand 1 3467 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3468 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3469 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3470 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3471 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3472 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3473 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3474 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3475 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3476 // MIs[2] Operand 1 3477 // No operand predicates 3478 GIM_CheckIsSafeToFold, /*InsnID*/1, 3479 GIM_CheckIsSafeToFold, /*InsnID*/2, 3480 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3481 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU, 3482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3483 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3484 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3485 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3486 GIR_EraseFromParent, /*InsnID*/0, 3487 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3488 // GIR_Coverage, 414, 3489 GIR_Done, 3490 // Label 253: @7515 3491 GIM_Try, /*On fail goto*//*Label 254*/ 7592, // Rule ID 416 // 3492 GIM_CheckFeatures, GIFBS_IsRV64, 3493 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3494 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3496 // MIs[0] Operand 1 3497 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3498 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3499 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3500 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3501 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3502 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3503 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3504 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3505 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3506 // MIs[2] Operand 1 3507 // No operand predicates 3508 GIM_CheckIsSafeToFold, /*InsnID*/1, 3509 GIM_CheckIsSafeToFold, /*InsnID*/2, 3510 // (ld:{ *:[i32] } (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3511 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU, 3512 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3513 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3514 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3515 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3516 GIR_EraseFromParent, /*InsnID*/0, 3517 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3518 // GIR_Coverage, 416, 3519 GIR_Done, 3520 // Label 254: @7592 3521 GIM_Try, /*On fail goto*//*Label 255*/ 7636, // Rule ID 273 // 3522 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3523 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3525 // MIs[0] rs1 3526 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3527 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3528 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU, 3530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3531 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3532 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3533 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3534 GIR_EraseFromParent, /*InsnID*/0, 3535 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3536 // GIR_Coverage, 273, 3537 GIR_Done, 3538 // Label 255: @7636 3539 GIM_Try, /*On fail goto*//*Label 256*/ 7680, // Rule ID 275 // 3540 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3541 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3543 // MIs[0] rs1 3544 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3546 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3547 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU, 3548 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3549 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3550 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3551 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3552 GIR_EraseFromParent, /*InsnID*/0, 3553 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3554 // GIR_Coverage, 275, 3555 GIR_Done, 3556 // Label 256: @7680 3557 GIM_Try, /*On fail goto*//*Label 257*/ 7724, // Rule ID 288 // 3558 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3559 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3561 // MIs[0] rs1 3562 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3564 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3565 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU, 3566 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3567 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3568 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3569 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3570 GIR_EraseFromParent, /*InsnID*/0, 3571 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3572 // GIR_Coverage, 288, 3573 GIR_Done, 3574 // Label 257: @7724 3575 GIM_Try, /*On fail goto*//*Label 258*/ 7768, // Rule ID 290 // 3576 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3577 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3579 // MIs[0] rs1 3580 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3582 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3583 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU, 3584 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3586 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3587 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3588 GIR_EraseFromParent, /*InsnID*/0, 3589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3590 // GIR_Coverage, 290, 3591 GIR_Done, 3592 // Label 258: @7768 3593 GIM_Try, /*On fail goto*//*Label 259*/ 7814, // Rule ID 408 // 3594 GIM_CheckFeatures, GIFBS_IsRV64, 3595 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3596 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3598 // MIs[0] rs1 3599 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3601 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3602 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU, 3603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3605 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3606 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3607 GIR_EraseFromParent, /*InsnID*/0, 3608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3609 // GIR_Coverage, 408, 3610 GIR_Done, 3611 // Label 259: @7814 3612 GIM_Try, /*On fail goto*//*Label 260*/ 7860, // Rule ID 410 // 3613 GIM_CheckFeatures, GIFBS_IsRV64, 3614 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3615 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3617 // MIs[0] rs1 3618 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3620 // (ld:{ *:[i32] } GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3621 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU, 3622 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3624 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3625 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3626 GIR_EraseFromParent, /*InsnID*/0, 3627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3628 // GIR_Coverage, 410, 3629 GIR_Done, 3630 // Label 260: @7860 3631 GIM_Reject, 3632 // Label 247: @7861 3633 GIM_Try, /*On fail goto*//*Label 261*/ 7936, // Rule ID 280 // 3634 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3635 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3636 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3637 // MIs[0] Operand 1 3638 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3639 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3640 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3641 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3642 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3643 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3644 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3645 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3646 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3647 // MIs[2] Operand 1 3648 // No operand predicates 3649 GIM_CheckIsSafeToFold, /*InsnID*/1, 3650 GIM_CheckIsSafeToFold, /*InsnID*/2, 3651 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 3652 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU, 3653 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3654 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3655 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3656 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3657 GIR_EraseFromParent, /*InsnID*/0, 3658 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3659 // GIR_Coverage, 280, 3660 GIR_Done, 3661 // Label 261: @7936 3662 GIM_Try, /*On fail goto*//*Label 262*/ 8011, // Rule ID 295 // 3663 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3664 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3665 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3666 // MIs[0] Operand 1 3667 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3668 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3669 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3670 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3671 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3672 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3673 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3674 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3675 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3676 // MIs[2] Operand 1 3677 // No operand predicates 3678 GIM_CheckIsSafeToFold, /*InsnID*/1, 3679 GIM_CheckIsSafeToFold, /*InsnID*/2, 3680 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 3681 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU, 3682 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3683 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3684 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3685 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3686 GIR_EraseFromParent, /*InsnID*/0, 3687 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3688 // GIR_Coverage, 295, 3689 GIR_Done, 3690 // Label 262: @8011 3691 GIM_Try, /*On fail goto*//*Label 263*/ 8088, // Rule ID 415 // 3692 GIM_CheckFeatures, GIFBS_IsRV64, 3693 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3694 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3695 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3696 // MIs[0] Operand 1 3697 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3698 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3699 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3700 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3701 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3702 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3703 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3704 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3705 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3706 // MIs[2] Operand 1 3707 // No operand predicates 3708 GIM_CheckIsSafeToFold, /*InsnID*/1, 3709 GIM_CheckIsSafeToFold, /*InsnID*/2, 3710 // (ld:{ *:[i64] } (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 3711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU, 3712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3714 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3715 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3716 GIR_EraseFromParent, /*InsnID*/0, 3717 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3718 // GIR_Coverage, 415, 3719 GIR_Done, 3720 // Label 263: @8088 3721 GIM_Try, /*On fail goto*//*Label 264*/ 8132, // Rule ID 274 // 3722 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/1, 3723 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3724 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3725 // MIs[0] rs1 3726 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3727 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3728 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>> => (LBU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 3729 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LBU, 3730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3732 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3733 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3734 GIR_EraseFromParent, /*InsnID*/0, 3735 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3736 // GIR_Coverage, 274, 3737 GIR_Done, 3738 // Label 264: @8132 3739 GIM_Try, /*On fail goto*//*Label 265*/ 8176, // Rule ID 289 // 3740 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/2, 3741 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3743 // MIs[0] rs1 3744 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3746 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>> => (LHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 3747 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LHU, 3748 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3749 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3750 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3751 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3752 GIR_EraseFromParent, /*InsnID*/0, 3753 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3754 // GIR_Coverage, 289, 3755 GIR_Done, 3756 // Label 265: @8176 3757 GIM_Try, /*On fail goto*//*Label 266*/ 8222, // Rule ID 409 // 3758 GIM_CheckFeatures, GIFBS_IsRV64, 3759 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 3760 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3762 // MIs[0] rs1 3763 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3765 // (ld:{ *:[i64] } GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi32>> => (LWU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 3766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::LWU, 3767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 3768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3769 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3770 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3771 GIR_EraseFromParent, /*InsnID*/0, 3772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3773 // GIR_Coverage, 409, 3774 GIR_Done, 3775 // Label 266: @8222 3776 GIM_Reject, 3777 // Label 248: @8223 3778 GIM_Reject, 3779 // Label 15: @8224 3780 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 269*/ 9562, 3781 /*GILLT_s32*//*Label 267*/ 8232, 3782 /*GILLT_s64*//*Label 268*/ 9006, 3783 // Label 267: @8232 3784 GIM_Try, /*On fail goto*//*Label 270*/ 9005, 3785 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 3786 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 3787 GIM_Try, /*On fail goto*//*Label 271*/ 8311, // Rule ID 339 // 3788 GIM_CheckFeatures, GIFBS_IsRV32, 3789 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3790 // MIs[0] Operand 1 3791 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3792 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3793 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3794 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3795 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3796 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3797 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3798 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3799 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3800 // MIs[2] Operand 1 3801 // No operand predicates 3802 GIM_CheckIsSafeToFold, /*InsnID*/1, 3803 GIM_CheckIsSafeToFold, /*InsnID*/2, 3804 // (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3805 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW, 3806 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 3807 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3808 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3809 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3810 GIR_EraseFromParent, /*InsnID*/0, 3811 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3812 // GIR_Coverage, 339, 3813 GIR_Done, 3814 // Label 271: @8311 3815 GIM_Try, /*On fail goto*//*Label 272*/ 8381, // Rule ID 341 // 3816 GIM_CheckFeatures, GIFBS_IsRV32, 3817 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3818 // MIs[0] Operand 1 3819 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3820 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3821 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3822 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3823 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3824 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3825 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3826 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3827 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3828 // MIs[2] Operand 1 3829 // No operand predicates 3830 GIM_CheckIsSafeToFold, /*InsnID*/1, 3831 GIM_CheckIsSafeToFold, /*InsnID*/2, 3832 // (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3833 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW, 3834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 3835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3836 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3837 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3838 GIR_EraseFromParent, /*InsnID*/0, 3839 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3840 // GIR_Coverage, 341, 3841 GIR_Done, 3842 // Label 272: @8381 3843 GIM_Try, /*On fail goto*//*Label 273*/ 8451, // Rule ID 459 // 3844 GIM_CheckFeatures, GIFBS_IsRV64, 3845 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3846 // MIs[0] Operand 1 3847 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3848 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3849 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3850 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3851 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3852 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3853 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3854 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3855 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3856 // MIs[2] Operand 1 3857 // No operand predicates 3858 GIM_CheckIsSafeToFold, /*InsnID*/1, 3859 GIM_CheckIsSafeToFold, /*InsnID*/2, 3860 // (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3861 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD, 3862 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 3863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3864 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3865 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3866 GIR_EraseFromParent, /*InsnID*/0, 3867 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3868 // GIR_Coverage, 459, 3869 GIR_Done, 3870 // Label 273: @8451 3871 GIM_Try, /*On fail goto*//*Label 274*/ 8521, // Rule ID 461 // 3872 GIM_CheckFeatures, GIFBS_IsRV64, 3873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3874 // MIs[0] Operand 1 3875 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3876 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3877 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3878 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3879 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3880 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3881 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3882 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3883 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3884 // MIs[2] Operand 1 3885 // No operand predicates 3886 GIM_CheckIsSafeToFold, /*InsnID*/1, 3887 GIM_CheckIsSafeToFold, /*InsnID*/2, 3888 // (st GPR:{ *:[i32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3889 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD, 3890 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 3891 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3892 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3893 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3894 GIR_EraseFromParent, /*InsnID*/0, 3895 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3896 // GIR_Coverage, 461, 3897 GIR_Done, 3898 // Label 274: @8521 3899 GIM_Try, /*On fail goto*//*Label 275*/ 8591, // Rule ID 1151 // 3900 GIM_CheckFeatures, GIFBS_HasStdExtF, 3901 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 3902 // MIs[0] Operand 1 3903 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3904 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3905 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3906 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3907 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3908 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3909 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3910 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3911 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3912 // MIs[2] Operand 1 3913 // No operand predicates 3914 GIM_CheckIsSafeToFold, /*InsnID*/1, 3915 GIM_CheckIsSafeToFold, /*InsnID*/2, 3916 // (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3917 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW, 3918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 3919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3920 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3921 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3922 GIR_EraseFromParent, /*InsnID*/0, 3923 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3924 // GIR_Coverage, 1151, 3925 GIR_Done, 3926 // Label 275: @8591 3927 GIM_Try, /*On fail goto*//*Label 276*/ 8661, // Rule ID 1152 // 3928 GIM_CheckFeatures, GIFBS_HasStdExtF, 3929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 3930 // MIs[0] Operand 1 3931 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 3932 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3933 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3934 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 3935 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 3936 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3937 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3938 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3939 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3940 // MIs[2] Operand 1 3941 // No operand predicates 3942 GIM_CheckIsSafeToFold, /*InsnID*/1, 3943 GIM_CheckIsSafeToFold, /*InsnID*/2, 3944 // (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 3945 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW, 3946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 3947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3948 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3949 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3950 GIR_EraseFromParent, /*InsnID*/0, 3951 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3952 // GIR_Coverage, 1152, 3953 GIR_Done, 3954 // Label 276: @8661 3955 GIM_Try, /*On fail goto*//*Label 277*/ 8731, // Rule ID 1153 // 3956 GIM_CheckFeatures, GIFBS_HasStdExtF, 3957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 3958 // MIs[0] Operand 1 3959 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3960 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 3961 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 3962 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 3963 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 3964 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3965 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 3966 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 3967 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 3968 // MIs[2] Operand 1 3969 // No operand predicates 3970 GIM_CheckIsSafeToFold, /*InsnID*/1, 3971 GIM_CheckIsSafeToFold, /*InsnID*/2, 3972 // (st FPR32:{ *:[f32] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 3973 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW, 3974 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 3975 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 3976 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 3977 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 3978 GIR_EraseFromParent, /*InsnID*/0, 3979 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3980 // GIR_Coverage, 1153, 3981 GIR_Done, 3982 // Label 277: @8731 3983 GIM_Try, /*On fail goto*//*Label 278*/ 8770, // Rule ID 333 // 3984 GIM_CheckFeatures, GIFBS_IsRV32, 3985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 3986 // MIs[0] rs1 3987 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 3988 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 3989 // (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 3990 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW, 3991 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 3992 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 3993 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 3994 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 3995 GIR_EraseFromParent, /*InsnID*/0, 3996 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 3997 // GIR_Coverage, 333, 3998 GIR_Done, 3999 // Label 278: @8770 4000 GIM_Try, /*On fail goto*//*Label 279*/ 8809, // Rule ID 335 // 4001 GIM_CheckFeatures, GIFBS_IsRV32, 4002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4003 // MIs[0] rs1 4004 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4006 // (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 4007 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW, 4008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4009 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4010 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4011 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4012 GIR_EraseFromParent, /*InsnID*/0, 4013 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4014 // GIR_Coverage, 335, 4015 GIR_Done, 4016 // Label 279: @8809 4017 GIM_Try, /*On fail goto*//*Label 280*/ 8848, // Rule ID 453 // 4018 GIM_CheckFeatures, GIFBS_IsRV64, 4019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4020 // MIs[0] rs1 4021 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4022 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4023 // (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 4024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD, 4025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4027 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4028 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4029 GIR_EraseFromParent, /*InsnID*/0, 4030 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4031 // GIR_Coverage, 453, 4032 GIR_Done, 4033 // Label 280: @8848 4034 GIM_Try, /*On fail goto*//*Label 281*/ 8887, // Rule ID 455 // 4035 GIM_CheckFeatures, GIFBS_IsRV64, 4036 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4037 // MIs[0] rs1 4038 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4040 // (st GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 4041 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD, 4042 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4044 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4045 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4046 GIR_EraseFromParent, /*InsnID*/0, 4047 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4048 // GIR_Coverage, 455, 4049 GIR_Done, 4050 // Label 281: @8887 4051 GIM_Try, /*On fail goto*//*Label 282*/ 8926, // Rule ID 1145 // 4052 GIM_CheckFeatures, GIFBS_HasStdExtF, 4053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 4054 // MIs[0] rs1 4055 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4056 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4057 // (st FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 4058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW, 4059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4061 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4062 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4063 GIR_EraseFromParent, /*InsnID*/0, 4064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4065 // GIR_Coverage, 1145, 4066 GIR_Done, 4067 // Label 282: @8926 4068 GIM_Try, /*On fail goto*//*Label 283*/ 8965, // Rule ID 1146 // 4069 GIM_CheckFeatures, GIFBS_HasStdExtF, 4070 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 4071 // MIs[0] rs1 4072 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4074 // (st FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 4075 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW, 4076 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4077 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4078 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4079 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4080 GIR_EraseFromParent, /*InsnID*/0, 4081 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4082 // GIR_Coverage, 1146, 4083 GIR_Done, 4084 // Label 283: @8965 4085 GIM_Try, /*On fail goto*//*Label 284*/ 9004, // Rule ID 1147 // 4086 GIM_CheckFeatures, GIFBS_HasStdExtF, 4087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 4088 // MIs[0] rs1 4089 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4091 // (st FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSW FPR32:{ *:[f32] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 4092 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSW, 4093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4095 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4096 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4097 GIR_EraseFromParent, /*InsnID*/0, 4098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4099 // GIR_Coverage, 1147, 4100 GIR_Done, 4101 // Label 284: @9004 4102 GIM_Reject, 4103 // Label 270: @9005 4104 GIM_Reject, 4105 // Label 268: @9006 4106 GIM_Try, /*On fail goto*//*Label 285*/ 9561, 4107 GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, 4108 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::NotAtomic, 4109 GIM_Try, /*On fail goto*//*Label 286*/ 9085, // Rule ID 340 // 4110 GIM_CheckFeatures, GIFBS_IsRV32, 4111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4112 // MIs[0] Operand 1 4113 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4114 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4115 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4116 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4117 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4118 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4119 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4120 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 4121 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 4122 // MIs[2] Operand 1 4123 // No operand predicates 4124 GIM_CheckIsSafeToFold, /*InsnID*/1, 4125 GIM_CheckIsSafeToFold, /*InsnID*/2, 4126 // (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 4127 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW, 4128 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4129 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 4130 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 4131 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 4132 GIR_EraseFromParent, /*InsnID*/0, 4133 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4134 // GIR_Coverage, 340, 4135 GIR_Done, 4136 // Label 286: @9085 4137 GIM_Try, /*On fail goto*//*Label 287*/ 9155, // Rule ID 460 // 4138 GIM_CheckFeatures, GIFBS_IsRV64, 4139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4140 // MIs[0] Operand 1 4141 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4142 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4143 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4144 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4145 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4146 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4147 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4148 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 4149 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 4150 // MIs[2] Operand 1 4151 // No operand predicates 4152 GIM_CheckIsSafeToFold, /*InsnID*/1, 4153 GIM_CheckIsSafeToFold, /*InsnID*/2, 4154 // (st GPR:{ *:[i64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 4155 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD, 4156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4157 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 4158 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 4159 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 4160 GIR_EraseFromParent, /*InsnID*/0, 4161 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4162 // GIR_Coverage, 460, 4163 GIR_Done, 4164 // Label 287: @9155 4165 GIM_Try, /*On fail goto*//*Label 288*/ 9225, // Rule ID 1294 // 4166 GIM_CheckFeatures, GIFBS_HasStdExtD, 4167 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 4168 // MIs[0] Operand 1 4169 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4170 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4171 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4172 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4173 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4174 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4175 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4176 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 4177 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 4178 // MIs[2] Operand 1 4179 // No operand predicates 4180 GIM_CheckIsSafeToFold, /*InsnID*/1, 4181 GIM_CheckIsSafeToFold, /*InsnID*/2, 4182 // (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 4183 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD, 4184 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4185 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 4186 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 4187 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 4188 GIR_EraseFromParent, /*InsnID*/0, 4189 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4190 // GIR_Coverage, 1294, 4191 GIR_Done, 4192 // Label 288: @9225 4193 GIM_Try, /*On fail goto*//*Label 289*/ 9295, // Rule ID 1295 // 4194 GIM_CheckFeatures, GIFBS_HasStdExtD, 4195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 4196 // MIs[0] Operand 1 4197 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4198 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4199 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4200 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 4201 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 4202 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4203 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4204 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 4205 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 4206 // MIs[2] Operand 1 4207 // No operand predicates 4208 GIM_CheckIsSafeToFold, /*InsnID*/1, 4209 GIM_CheckIsSafeToFold, /*InsnID*/2, 4210 // (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 4211 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD, 4212 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4213 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 4214 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 4215 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 4216 GIR_EraseFromParent, /*InsnID*/0, 4217 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4218 // GIR_Coverage, 1295, 4219 GIR_Done, 4220 // Label 289: @9295 4221 GIM_Try, /*On fail goto*//*Label 290*/ 9365, // Rule ID 1296 // 4222 GIM_CheckFeatures, GIFBS_HasStdExtD, 4223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 4224 // MIs[0] Operand 1 4225 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4226 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 4227 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD, 4228 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 4229 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 4230 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4231 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 4232 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 4233 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_simm12, 4234 // MIs[2] Operand 1 4235 // No operand predicates 4236 GIM_CheckIsSafeToFold, /*InsnID*/1, 4237 GIM_CheckIsSafeToFold, /*InsnID*/2, 4238 // (st FPR64:{ *:[f64] }:$rs2, (add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12))<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 4239 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD, 4240 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4241 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 4242 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm12 4243 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, 1, 2, GIU_MergeMemOperands_EndOfList, 4244 GIR_EraseFromParent, /*InsnID*/0, 4245 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4246 // GIR_Coverage, 1296, 4247 GIR_Done, 4248 // Label 290: @9365 4249 GIM_Try, /*On fail goto*//*Label 291*/ 9404, // Rule ID 334 // 4250 GIM_CheckFeatures, GIFBS_IsRV32, 4251 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4252 // MIs[0] rs1 4253 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4254 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4255 // (st GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SW GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 4256 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SW, 4257 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4258 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4259 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4260 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4261 GIR_EraseFromParent, /*InsnID*/0, 4262 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4263 // GIR_Coverage, 334, 4264 GIR_Done, 4265 // Label 291: @9404 4266 GIM_Try, /*On fail goto*//*Label 292*/ 9443, // Rule ID 454 // 4267 GIM_CheckFeatures, GIFBS_IsRV64, 4268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4269 // MIs[0] rs1 4270 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4271 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4272 // (st GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (SD GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 4273 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SD, 4274 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4275 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4276 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4277 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4278 GIR_EraseFromParent, /*InsnID*/0, 4279 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4280 // GIR_Coverage, 454, 4281 GIR_Done, 4282 // Label 292: @9443 4283 GIM_Try, /*On fail goto*//*Label 293*/ 9482, // Rule ID 1288 // 4284 GIM_CheckFeatures, GIFBS_HasStdExtD, 4285 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 4286 // MIs[0] rs1 4287 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4289 // (st FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 4290 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD, 4291 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4292 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4293 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4294 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4295 GIR_EraseFromParent, /*InsnID*/0, 4296 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4297 // GIR_Coverage, 1288, 4298 GIR_Done, 4299 // Label 293: @9482 4300 GIM_Try, /*On fail goto*//*Label 294*/ 9521, // Rule ID 1289 // 4301 GIM_CheckFeatures, GIFBS_HasStdExtD, 4302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 4303 // MIs[0] rs1 4304 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4306 // (st FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }) 4307 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD, 4308 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4309 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4310 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4311 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4312 GIR_EraseFromParent, /*InsnID*/0, 4313 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4314 // GIR_Coverage, 1289, 4315 GIR_Done, 4316 // Label 294: @9521 4317 GIM_Try, /*On fail goto*//*Label 295*/ 9560, // Rule ID 1290 // 4318 GIM_CheckFeatures, GIFBS_HasStdExtD, 4319 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 4320 // MIs[0] rs1 4321 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4323 // (st FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1)<<P:Predicate_unindexedstore>><<P:Predicate_store>> => (FSD FPR64:{ *:[f64] }:$rs2, GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }) 4324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSD, 4325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rs2 4326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 4327 GIR_AddImm, /*InsnID*/0, /*Imm*/0, 4328 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 4329 GIR_EraseFromParent, /*InsnID*/0, 4330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4331 // GIR_Coverage, 1290, 4332 GIR_Done, 4333 // Label 295: @9560 4334 GIM_Reject, 4335 // Label 285: @9561 4336 GIM_Reject, 4337 // Label 269: @9562 4338 GIM_Reject, 4339 // Label 16: @9563 4340 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 298*/ 10607, 4341 /*GILLT_s32*//*Label 296*/ 9571, 4342 /*GILLT_s64*//*Label 297*/ 10259, 4343 // Label 296: @9571 4344 GIM_Try, /*On fail goto*//*Label 299*/ 10258, 4345 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4346 GIM_Try, /*On fail goto*//*Label 300*/ 9611, // Rule ID 650 // 4347 GIM_CheckFeatures, GIFBS_HasStdExtA, 4348 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4349 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4350 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4351 // MIs[0] rs1 4352 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4353 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4355 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4356 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W, 4357 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4358 // GIR_Coverage, 650, 4359 GIR_Done, 4360 // Label 300: @9611 4361 GIM_Try, /*On fail goto*//*Label 301*/ 9645, // Rule ID 652 // 4362 GIM_CheckFeatures, GIFBS_HasStdExtA, 4363 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4364 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4365 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4366 // MIs[0] rs1 4367 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4370 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> => (AMOSWAP_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4371 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W, 4372 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4373 // GIR_Coverage, 652, 4374 GIR_Done, 4375 // Label 301: @9645 4376 GIM_Try, /*On fail goto*//*Label 302*/ 9679, // Rule ID 653 // 4377 GIM_CheckFeatures, GIFBS_HasStdExtA, 4378 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4379 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 4380 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4381 // MIs[0] rs1 4382 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4383 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4384 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4385 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> => (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4386 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ, 4387 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4388 // GIR_Coverage, 653, 4389 GIR_Done, 4390 // Label 302: @9679 4391 GIM_Try, /*On fail goto*//*Label 303*/ 9713, // Rule ID 655 // 4392 GIM_CheckFeatures, GIFBS_HasStdExtA, 4393 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4394 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 4395 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4396 // MIs[0] rs1 4397 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4398 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4399 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4400 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> => (AMOSWAP_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4401 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ, 4402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4403 // GIR_Coverage, 655, 4404 GIR_Done, 4405 // Label 303: @9713 4406 GIM_Try, /*On fail goto*//*Label 304*/ 9747, // Rule ID 656 // 4407 GIM_CheckFeatures, GIFBS_HasStdExtA, 4408 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4409 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 4410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4411 // MIs[0] rs1 4412 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4413 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4414 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4415 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> => (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4416 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_RL, 4417 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4418 // GIR_Coverage, 656, 4419 GIR_Done, 4420 // Label 304: @9747 4421 GIM_Try, /*On fail goto*//*Label 305*/ 9781, // Rule ID 658 // 4422 GIM_CheckFeatures, GIFBS_HasStdExtA, 4423 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4424 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 4425 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4426 // MIs[0] rs1 4427 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4429 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4430 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> => (AMOSWAP_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4431 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_RL, 4432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4433 // GIR_Coverage, 658, 4434 GIR_Done, 4435 // Label 305: @9781 4436 GIM_Try, /*On fail goto*//*Label 306*/ 9815, // Rule ID 659 // 4437 GIM_CheckFeatures, GIFBS_HasStdExtA, 4438 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4439 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 4440 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4441 // MIs[0] rs1 4442 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4444 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4445 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4446 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL, 4447 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4448 // GIR_Coverage, 659, 4449 GIR_Done, 4450 // Label 306: @9815 4451 GIM_Try, /*On fail goto*//*Label 307*/ 9849, // Rule ID 661 // 4452 GIM_CheckFeatures, GIFBS_HasStdExtA, 4453 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4454 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 4455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4456 // MIs[0] rs1 4457 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4459 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4460 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4461 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL, 4462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4463 // GIR_Coverage, 661, 4464 GIR_Done, 4465 // Label 307: @9849 4466 GIM_Try, /*On fail goto*//*Label 308*/ 9883, // Rule ID 662 // 4467 GIM_CheckFeatures, GIFBS_HasStdExtA, 4468 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4469 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 4470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4471 // MIs[0] rs1 4472 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4474 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4475 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4476 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL, 4477 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4478 // GIR_Coverage, 662, 4479 GIR_Done, 4480 // Label 308: @9883 4481 GIM_Try, /*On fail goto*//*Label 309*/ 9917, // Rule ID 664 // 4482 GIM_CheckFeatures, GIFBS_HasStdExtA, 4483 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4484 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 4485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4486 // MIs[0] rs1 4487 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4490 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4491 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL, 4492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4493 // GIR_Coverage, 664, 4494 GIR_Done, 4495 // Label 309: @9917 4496 GIM_Try, /*On fail goto*//*Label 310*/ 9951, // Rule ID 878 // 4497 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4498 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4499 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4501 // MIs[0] rs1 4502 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4504 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4505 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> => (AMOSWAP_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4506 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D, 4507 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4508 // GIR_Coverage, 878, 4509 GIR_Done, 4510 // Label 310: @9951 4511 GIM_Try, /*On fail goto*//*Label 311*/ 9985, // Rule ID 880 // 4512 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4513 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4514 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4516 // MIs[0] rs1 4517 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4519 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4520 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> => (AMOSWAP_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4521 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D, 4522 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4523 // GIR_Coverage, 880, 4524 GIR_Done, 4525 // Label 311: @9985 4526 GIM_Try, /*On fail goto*//*Label 312*/ 10019, // Rule ID 881 // 4527 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4528 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4529 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 4530 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4531 // MIs[0] rs1 4532 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4534 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4535 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> => (AMOSWAP_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4536 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ, 4537 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4538 // GIR_Coverage, 881, 4539 GIR_Done, 4540 // Label 312: @10019 4541 GIM_Try, /*On fail goto*//*Label 313*/ 10053, // Rule ID 883 // 4542 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4543 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4544 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 4545 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4546 // MIs[0] rs1 4547 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4550 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> => (AMOSWAP_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4551 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ, 4552 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4553 // GIR_Coverage, 883, 4554 GIR_Done, 4555 // Label 313: @10053 4556 GIM_Try, /*On fail goto*//*Label 314*/ 10087, // Rule ID 884 // 4557 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4558 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4559 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 4560 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4561 // MIs[0] rs1 4562 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4564 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4565 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> => (AMOSWAP_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4566 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_RL, 4567 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4568 // GIR_Coverage, 884, 4569 GIR_Done, 4570 // Label 314: @10087 4571 GIM_Try, /*On fail goto*//*Label 315*/ 10121, // Rule ID 886 // 4572 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4573 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4574 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 4575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4576 // MIs[0] rs1 4577 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4579 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4580 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> => (AMOSWAP_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4581 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_RL, 4582 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4583 // GIR_Coverage, 886, 4584 GIR_Done, 4585 // Label 315: @10121 4586 GIM_Try, /*On fail goto*//*Label 316*/ 10155, // Rule ID 887 // 4587 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4588 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4589 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 4590 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4591 // MIs[0] rs1 4592 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4594 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4595 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> => (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4596 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL, 4597 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4598 // GIR_Coverage, 887, 4599 GIR_Done, 4600 // Label 316: @10155 4601 GIM_Try, /*On fail goto*//*Label 317*/ 10189, // Rule ID 889 // 4602 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4603 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4604 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 4605 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4606 // MIs[0] rs1 4607 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4609 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4610 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> => (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4611 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL, 4612 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4613 // GIR_Coverage, 889, 4614 GIR_Done, 4615 // Label 317: @10189 4616 GIM_Try, /*On fail goto*//*Label 318*/ 10223, // Rule ID 890 // 4617 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4618 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4619 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 4620 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4621 // MIs[0] rs1 4622 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4625 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> => (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4626 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL, 4627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4628 // GIR_Coverage, 890, 4629 GIR_Done, 4630 // Label 318: @10223 4631 GIM_Try, /*On fail goto*//*Label 319*/ 10257, // Rule ID 892 // 4632 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4633 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4634 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 4635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4636 // MIs[0] rs1 4637 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4640 // (atomic_swap:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> => (AMOSWAP_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4641 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL, 4642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4643 // GIR_Coverage, 892, 4644 GIR_Done, 4645 // Label 319: @10257 4646 GIM_Reject, 4647 // Label 299: @10258 4648 GIM_Reject, 4649 // Label 297: @10259 4650 GIM_Try, /*On fail goto*//*Label 320*/ 10606, 4651 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 4652 GIM_Try, /*On fail goto*//*Label 321*/ 10299, // Rule ID 651 // 4653 GIM_CheckFeatures, GIFBS_HasStdExtA, 4654 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4655 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4657 // MIs[0] rs1 4658 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4659 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4661 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_monotonic>> => (AMOSWAP_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4662 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W, 4663 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4664 // GIR_Coverage, 651, 4665 GIR_Done, 4666 // Label 321: @10299 4667 GIM_Try, /*On fail goto*//*Label 322*/ 10333, // Rule ID 654 // 4668 GIM_CheckFeatures, GIFBS_HasStdExtA, 4669 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4670 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 4671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4672 // MIs[0] rs1 4673 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4674 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4676 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acquire>> => (AMOSWAP_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4677 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ, 4678 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4679 // GIR_Coverage, 654, 4680 GIR_Done, 4681 // Label 322: @10333 4682 GIM_Try, /*On fail goto*//*Label 323*/ 10367, // Rule ID 657 // 4683 GIM_CheckFeatures, GIFBS_HasStdExtA, 4684 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4685 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 4686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4687 // MIs[0] rs1 4688 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4689 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4691 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_release>> => (AMOSWAP_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4692 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_RL, 4693 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4694 // GIR_Coverage, 657, 4695 GIR_Done, 4696 // Label 323: @10367 4697 GIM_Try, /*On fail goto*//*Label 324*/ 10401, // Rule ID 660 // 4698 GIM_CheckFeatures, GIFBS_HasStdExtA, 4699 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4700 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 4701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4702 // MIs[0] rs1 4703 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4704 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4706 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_acq_rel>> => (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4707 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL, 4708 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4709 // GIR_Coverage, 660, 4710 GIR_Done, 4711 // Label 324: @10401 4712 GIM_Try, /*On fail goto*//*Label 325*/ 10435, // Rule ID 663 // 4713 GIM_CheckFeatures, GIFBS_HasStdExtA, 4714 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4715 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 4716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4717 // MIs[0] rs1 4718 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4721 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_32>><<P:Predicate_atomic_swap_32_seq_cst>> => (AMOSWAP_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4722 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_W_AQ_RL, 4723 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4724 // GIR_Coverage, 663, 4725 GIR_Done, 4726 // Label 325: @10435 4727 GIM_Try, /*On fail goto*//*Label 326*/ 10469, // Rule ID 879 // 4728 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4729 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4730 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4732 // MIs[0] rs1 4733 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4736 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_monotonic>> => (AMOSWAP_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4737 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D, 4738 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4739 // GIR_Coverage, 879, 4740 GIR_Done, 4741 // Label 326: @10469 4742 GIM_Try, /*On fail goto*//*Label 327*/ 10503, // Rule ID 882 // 4743 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4744 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4745 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 4746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4747 // MIs[0] rs1 4748 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4751 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acquire>> => (AMOSWAP_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4752 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ, 4753 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4754 // GIR_Coverage, 882, 4755 GIR_Done, 4756 // Label 327: @10503 4757 GIM_Try, /*On fail goto*//*Label 328*/ 10537, // Rule ID 885 // 4758 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4759 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4760 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 4761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4762 // MIs[0] rs1 4763 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4766 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_release>> => (AMOSWAP_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4767 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_RL, 4768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4769 // GIR_Coverage, 885, 4770 GIR_Done, 4771 // Label 328: @10537 4772 GIM_Try, /*On fail goto*//*Label 329*/ 10571, // Rule ID 888 // 4773 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4774 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4775 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 4776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4777 // MIs[0] rs1 4778 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4781 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_acq_rel>> => (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4782 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL, 4783 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4784 // GIR_Coverage, 888, 4785 GIR_Done, 4786 // Label 329: @10571 4787 GIM_Try, /*On fail goto*//*Label 330*/ 10605, // Rule ID 891 // 4788 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4789 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4790 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 4791 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4792 // MIs[0] rs1 4793 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 4794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4796 // (atomic_swap:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_swap_64>><<P:Predicate_atomic_swap_64_seq_cst>> => (AMOSWAP_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 4797 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOSWAP_D_AQ_RL, 4798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4799 // GIR_Coverage, 891, 4800 GIR_Done, 4801 // Label 330: @10605 4802 GIM_Reject, 4803 // Label 320: @10606 4804 GIM_Reject, 4805 // Label 298: @10607 4806 GIM_Reject, 4807 // Label 17: @10608 4808 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 333*/ 11652, 4809 /*GILLT_s32*//*Label 331*/ 10616, 4810 /*GILLT_s64*//*Label 332*/ 11304, 4811 // Label 331: @10616 4812 GIM_Try, /*On fail goto*//*Label 334*/ 11303, 4813 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 4814 GIM_Try, /*On fail goto*//*Label 335*/ 10656, // Rule ID 665 // 4815 GIM_CheckFeatures, GIFBS_HasStdExtA, 4816 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4817 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4818 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4819 // MIs[0] rs1 4820 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4821 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4823 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4824 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W, 4825 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4826 // GIR_Coverage, 665, 4827 GIR_Done, 4828 // Label 335: @10656 4829 GIM_Try, /*On fail goto*//*Label 336*/ 10690, // Rule ID 667 // 4830 GIM_CheckFeatures, GIFBS_HasStdExtA, 4831 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4832 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4833 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4834 // MIs[0] rs1 4835 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4836 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4838 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4839 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W, 4840 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4841 // GIR_Coverage, 667, 4842 GIR_Done, 4843 // Label 336: @10690 4844 GIM_Try, /*On fail goto*//*Label 337*/ 10724, // Rule ID 668 // 4845 GIM_CheckFeatures, GIFBS_HasStdExtA, 4846 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4847 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 4848 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4849 // MIs[0] rs1 4850 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4851 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4852 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4853 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4854 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ, 4855 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4856 // GIR_Coverage, 668, 4857 GIR_Done, 4858 // Label 337: @10724 4859 GIM_Try, /*On fail goto*//*Label 338*/ 10758, // Rule ID 670 // 4860 GIM_CheckFeatures, GIFBS_HasStdExtA, 4861 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4862 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 4863 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4864 // MIs[0] rs1 4865 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4866 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4868 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4869 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ, 4870 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4871 // GIR_Coverage, 670, 4872 GIR_Done, 4873 // Label 338: @10758 4874 GIM_Try, /*On fail goto*//*Label 339*/ 10792, // Rule ID 671 // 4875 GIM_CheckFeatures, GIFBS_HasStdExtA, 4876 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4877 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 4878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4879 // MIs[0] rs1 4880 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4881 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4882 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4883 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4884 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL, 4885 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4886 // GIR_Coverage, 671, 4887 GIR_Done, 4888 // Label 339: @10792 4889 GIM_Try, /*On fail goto*//*Label 340*/ 10826, // Rule ID 673 // 4890 GIM_CheckFeatures, GIFBS_HasStdExtA, 4891 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4892 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 4893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4894 // MIs[0] rs1 4895 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4897 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4898 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4899 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL, 4900 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4901 // GIR_Coverage, 673, 4902 GIR_Done, 4903 // Label 340: @10826 4904 GIM_Try, /*On fail goto*//*Label 341*/ 10860, // Rule ID 674 // 4905 GIM_CheckFeatures, GIFBS_HasStdExtA, 4906 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4907 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 4908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4909 // MIs[0] rs1 4910 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4912 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4913 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4914 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 4915 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4916 // GIR_Coverage, 674, 4917 GIR_Done, 4918 // Label 341: @10860 4919 GIM_Try, /*On fail goto*//*Label 342*/ 10894, // Rule ID 676 // 4920 GIM_CheckFeatures, GIFBS_HasStdExtA, 4921 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4922 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 4923 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4924 // MIs[0] rs1 4925 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4927 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4928 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4929 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 4930 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4931 // GIR_Coverage, 676, 4932 GIR_Done, 4933 // Label 342: @10894 4934 GIM_Try, /*On fail goto*//*Label 343*/ 10928, // Rule ID 677 // 4935 GIM_CheckFeatures, GIFBS_HasStdExtA, 4936 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4937 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 4938 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4939 // MIs[0] rs1 4940 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4943 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4944 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 4945 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4946 // GIR_Coverage, 677, 4947 GIR_Done, 4948 // Label 343: @10928 4949 GIM_Try, /*On fail goto*//*Label 344*/ 10962, // Rule ID 679 // 4950 GIM_CheckFeatures, GIFBS_HasStdExtA, 4951 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 4952 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 4953 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4954 // MIs[0] rs1 4955 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4958 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4959 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 4960 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4961 // GIR_Coverage, 679, 4962 GIR_Done, 4963 // Label 344: @10962 4964 GIM_Try, /*On fail goto*//*Label 345*/ 10996, // Rule ID 893 // 4965 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4966 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4967 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4969 // MIs[0] rs1 4970 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4973 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> => (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4974 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D, 4975 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4976 // GIR_Coverage, 893, 4977 GIR_Done, 4978 // Label 345: @10996 4979 GIM_Try, /*On fail goto*//*Label 346*/ 11030, // Rule ID 895 // 4980 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4981 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4982 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 4983 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4984 // MIs[0] rs1 4985 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 4986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 4987 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 4988 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> => (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 4989 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D, 4990 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 4991 // GIR_Coverage, 895, 4992 GIR_Done, 4993 // Label 346: @11030 4994 GIM_Try, /*On fail goto*//*Label 347*/ 11064, // Rule ID 896 // 4995 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 4996 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 4997 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 4998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 4999 // MIs[0] rs1 5000 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5002 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5003 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> => (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 5004 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ, 5005 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5006 // GIR_Coverage, 896, 5007 GIR_Done, 5008 // Label 347: @11064 5009 GIM_Try, /*On fail goto*//*Label 348*/ 11098, // Rule ID 898 // 5010 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5011 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5012 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 5013 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5014 // MIs[0] rs1 5015 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5017 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5018 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> => (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 5019 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ, 5020 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5021 // GIR_Coverage, 898, 5022 GIR_Done, 5023 // Label 348: @11098 5024 GIM_Try, /*On fail goto*//*Label 349*/ 11132, // Rule ID 899 // 5025 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5026 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5027 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5029 // MIs[0] rs1 5030 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5032 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5033 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> => (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 5034 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL, 5035 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5036 // GIR_Coverage, 899, 5037 GIR_Done, 5038 // Label 349: @11132 5039 GIM_Try, /*On fail goto*//*Label 350*/ 11166, // Rule ID 901 // 5040 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5041 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5042 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5043 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5044 // MIs[0] rs1 5045 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5047 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5048 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> => (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 5049 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL, 5050 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5051 // GIR_Coverage, 901, 5052 GIR_Done, 5053 // Label 350: @11166 5054 GIM_Try, /*On fail goto*//*Label 351*/ 11200, // Rule ID 902 // 5055 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5056 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5057 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 5058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5059 // MIs[0] rs1 5060 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5062 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5063 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 5064 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5066 // GIR_Coverage, 902, 5067 GIR_Done, 5068 // Label 351: @11200 5069 GIM_Try, /*On fail goto*//*Label 352*/ 11234, // Rule ID 904 // 5070 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5071 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5072 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 5073 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5074 // MIs[0] rs1 5075 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5078 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 5079 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5080 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5081 // GIR_Coverage, 904, 5082 GIR_Done, 5083 // Label 352: @11234 5084 GIM_Try, /*On fail goto*//*Label 353*/ 11268, // Rule ID 905 // 5085 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5086 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5087 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 5088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5089 // MIs[0] rs1 5090 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5092 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5093 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 5094 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5095 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5096 // GIR_Coverage, 905, 5097 GIR_Done, 5098 // Label 353: @11268 5099 GIM_Try, /*On fail goto*//*Label 354*/ 11302, // Rule ID 907 // 5100 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5101 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5102 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 5103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5104 // MIs[0] rs1 5105 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5107 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5108 // (atomic_load_add:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 5109 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5110 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5111 // GIR_Coverage, 907, 5112 GIR_Done, 5113 // Label 354: @11302 5114 GIM_Reject, 5115 // Label 334: @11303 5116 GIM_Reject, 5117 // Label 332: @11304 5118 GIM_Try, /*On fail goto*//*Label 355*/ 11651, 5119 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5120 GIM_Try, /*On fail goto*//*Label 356*/ 11344, // Rule ID 666 // 5121 GIM_CheckFeatures, GIFBS_HasStdExtA, 5122 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5123 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 5124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5125 // MIs[0] rs1 5126 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5129 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_monotonic>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5130 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W, 5131 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5132 // GIR_Coverage, 666, 5133 GIR_Done, 5134 // Label 356: @11344 5135 GIM_Try, /*On fail goto*//*Label 357*/ 11378, // Rule ID 669 // 5136 GIM_CheckFeatures, GIFBS_HasStdExtA, 5137 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5138 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 5139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5140 // MIs[0] rs1 5141 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5142 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5144 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acquire>> => (AMOADD_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5145 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ, 5146 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5147 // GIR_Coverage, 669, 5148 GIR_Done, 5149 // Label 357: @11378 5150 GIM_Try, /*On fail goto*//*Label 358*/ 11412, // Rule ID 672 // 5151 GIM_CheckFeatures, GIFBS_HasStdExtA, 5152 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5153 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5155 // MIs[0] rs1 5156 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5157 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5159 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_release>> => (AMOADD_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5160 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL, 5161 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5162 // GIR_Coverage, 672, 5163 GIR_Done, 5164 // Label 358: @11412 5165 GIM_Try, /*On fail goto*//*Label 359*/ 11446, // Rule ID 675 // 5166 GIM_CheckFeatures, GIFBS_HasStdExtA, 5167 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5168 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 5169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5170 // MIs[0] rs1 5171 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5172 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5174 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5175 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 5176 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5177 // GIR_Coverage, 675, 5178 GIR_Done, 5179 // Label 359: @11446 5180 GIM_Try, /*On fail goto*//*Label 360*/ 11480, // Rule ID 678 // 5181 GIM_CheckFeatures, GIFBS_HasStdExtA, 5182 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5183 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 5184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5185 // MIs[0] rs1 5186 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5187 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5189 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_32>><<P:Predicate_atomic_load_add_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5190 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 5191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5192 // GIR_Coverage, 678, 5193 GIR_Done, 5194 // Label 360: @11480 5195 GIM_Try, /*On fail goto*//*Label 361*/ 11514, // Rule ID 894 // 5196 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5197 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5198 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 5199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5200 // MIs[0] rs1 5201 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5204 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_monotonic>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5205 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D, 5206 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5207 // GIR_Coverage, 894, 5208 GIR_Done, 5209 // Label 361: @11514 5210 GIM_Try, /*On fail goto*//*Label 362*/ 11548, // Rule ID 897 // 5211 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5212 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5213 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 5214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5215 // MIs[0] rs1 5216 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5219 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acquire>> => (AMOADD_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5220 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ, 5221 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5222 // GIR_Coverage, 897, 5223 GIR_Done, 5224 // Label 362: @11548 5225 GIM_Try, /*On fail goto*//*Label 363*/ 11582, // Rule ID 900 // 5226 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5227 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5228 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5230 // MIs[0] rs1 5231 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5234 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_release>> => (AMOADD_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5235 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL, 5236 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5237 // GIR_Coverage, 900, 5238 GIR_Done, 5239 // Label 363: @11582 5240 GIM_Try, /*On fail goto*//*Label 364*/ 11616, // Rule ID 903 // 5241 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5242 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5243 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 5244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5245 // MIs[0] rs1 5246 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5249 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5250 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5252 // GIR_Coverage, 903, 5253 GIR_Done, 5254 // Label 364: @11616 5255 GIM_Try, /*On fail goto*//*Label 365*/ 11650, // Rule ID 906 // 5256 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5257 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5258 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 5259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5260 // MIs[0] rs1 5261 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5264 // (atomic_load_add:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_add_64>><<P:Predicate_atomic_load_add_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 5265 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5267 // GIR_Coverage, 906, 5268 GIR_Done, 5269 // Label 365: @11650 5270 GIM_Reject, 5271 // Label 355: @11651 5272 GIM_Reject, 5273 // Label 333: @11652 5274 GIM_Reject, 5275 // Label 18: @11653 5276 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 368*/ 13807, 5277 /*GILLT_s32*//*Label 366*/ 11661, 5278 /*GILLT_s64*//*Label 367*/ 13089, 5279 // Label 366: @11661 5280 GIM_Try, /*On fail goto*//*Label 369*/ 13088, 5281 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 5282 GIM_Try, /*On fail goto*//*Label 370*/ 11738, // Rule ID 785 // 5283 GIM_CheckFeatures, GIFBS_HasStdExtA, 5284 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5285 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 5286 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5287 // MIs[0] addr 5288 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5289 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5291 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5292 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5293 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5294 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5295 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5296 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5297 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5298 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W, 5299 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5300 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5301 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5302 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5303 GIR_EraseFromParent, /*InsnID*/0, 5304 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5305 // GIR_Coverage, 785, 5306 GIR_Done, 5307 // Label 370: @11738 5308 GIM_Try, /*On fail goto*//*Label 371*/ 11809, // Rule ID 787 // 5309 GIM_CheckFeatures, GIFBS_HasStdExtA, 5310 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5311 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 5312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5313 // MIs[0] addr 5314 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5315 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5316 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5317 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> => (AMOADD_W:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5318 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5319 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5320 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5321 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5322 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5323 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5324 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W, 5325 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5326 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5327 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5328 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5329 GIR_EraseFromParent, /*InsnID*/0, 5330 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5331 // GIR_Coverage, 787, 5332 GIR_Done, 5333 // Label 371: @11809 5334 GIM_Try, /*On fail goto*//*Label 372*/ 11880, // Rule ID 788 // 5335 GIM_CheckFeatures, GIFBS_HasStdExtA, 5336 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5337 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 5338 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5339 // MIs[0] addr 5340 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5343 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5344 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5345 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5346 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5347 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5348 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5349 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5350 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ, 5351 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5352 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5353 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5354 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5355 GIR_EraseFromParent, /*InsnID*/0, 5356 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5357 // GIR_Coverage, 788, 5358 GIR_Done, 5359 // Label 372: @11880 5360 GIM_Try, /*On fail goto*//*Label 373*/ 11951, // Rule ID 790 // 5361 GIM_CheckFeatures, GIFBS_HasStdExtA, 5362 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5363 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 5364 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5365 // MIs[0] addr 5366 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5368 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5369 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> => (AMOADD_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5370 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5371 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5372 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5373 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5374 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5375 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5376 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ, 5377 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5378 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5379 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5380 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5381 GIR_EraseFromParent, /*InsnID*/0, 5382 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5383 // GIR_Coverage, 790, 5384 GIR_Done, 5385 // Label 373: @11951 5386 GIM_Try, /*On fail goto*//*Label 374*/ 12022, // Rule ID 791 // 5387 GIM_CheckFeatures, GIFBS_HasStdExtA, 5388 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5389 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5391 // MIs[0] addr 5392 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5395 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5396 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5397 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5398 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5399 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5400 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5401 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5402 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL, 5403 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5404 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5405 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5406 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5407 GIR_EraseFromParent, /*InsnID*/0, 5408 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5409 // GIR_Coverage, 791, 5410 GIR_Done, 5411 // Label 374: @12022 5412 GIM_Try, /*On fail goto*//*Label 375*/ 12093, // Rule ID 793 // 5413 GIM_CheckFeatures, GIFBS_HasStdExtA, 5414 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5415 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5417 // MIs[0] addr 5418 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5421 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> => (AMOADD_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5422 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5423 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5424 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5425 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5426 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5427 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5428 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL, 5429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5430 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5431 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5432 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5433 GIR_EraseFromParent, /*InsnID*/0, 5434 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5435 // GIR_Coverage, 793, 5436 GIR_Done, 5437 // Label 375: @12093 5438 GIM_Try, /*On fail goto*//*Label 376*/ 12164, // Rule ID 794 // 5439 GIM_CheckFeatures, GIFBS_HasStdExtA, 5440 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5441 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 5442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5443 // MIs[0] addr 5444 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5445 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5447 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5448 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5449 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5450 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5451 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5452 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5453 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5454 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 5455 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5456 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5457 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5458 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5459 GIR_EraseFromParent, /*InsnID*/0, 5460 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5461 // GIR_Coverage, 794, 5462 GIR_Done, 5463 // Label 376: @12164 5464 GIM_Try, /*On fail goto*//*Label 377*/ 12235, // Rule ID 796 // 5465 GIM_CheckFeatures, GIFBS_HasStdExtA, 5466 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5467 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 5468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5469 // MIs[0] addr 5470 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5471 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5473 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5474 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5475 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5476 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5477 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5478 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5479 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5480 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 5481 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5482 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5483 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5484 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5485 GIR_EraseFromParent, /*InsnID*/0, 5486 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5487 // GIR_Coverage, 796, 5488 GIR_Done, 5489 // Label 377: @12235 5490 GIM_Try, /*On fail goto*//*Label 378*/ 12306, // Rule ID 797 // 5491 GIM_CheckFeatures, GIFBS_HasStdExtA, 5492 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5493 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 5494 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5495 // MIs[0] addr 5496 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5497 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5499 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5500 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5501 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5502 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5503 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5504 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5505 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5506 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 5507 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5508 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5509 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5510 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5511 GIR_EraseFromParent, /*InsnID*/0, 5512 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5513 // GIR_Coverage, 797, 5514 GIR_Done, 5515 // Label 378: @12306 5516 GIM_Try, /*On fail goto*//*Label 379*/ 12377, // Rule ID 799 // 5517 GIM_CheckFeatures, GIFBS_HasStdExtA, 5518 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5519 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 5520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5521 // MIs[0] addr 5522 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5523 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5524 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5525 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5526 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5527 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5528 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5529 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5530 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5531 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5532 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 5533 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5534 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5535 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5536 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5537 GIR_EraseFromParent, /*InsnID*/0, 5538 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5539 // GIR_Coverage, 799, 5540 GIR_Done, 5541 // Label 379: @12377 5542 GIM_Try, /*On fail goto*//*Label 380*/ 12448, // Rule ID 1013 // 5543 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5544 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5545 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 5546 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5547 // MIs[0] addr 5548 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5550 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5551 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> => (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5552 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5553 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5554 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5555 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5556 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5557 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5558 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D, 5559 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5560 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5561 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5562 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5563 GIR_EraseFromParent, /*InsnID*/0, 5564 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5565 // GIR_Coverage, 1013, 5566 GIR_Done, 5567 // Label 380: @12448 5568 GIM_Try, /*On fail goto*//*Label 381*/ 12519, // Rule ID 1015 // 5569 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5570 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5571 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 5572 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5573 // MIs[0] addr 5574 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5575 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5576 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5577 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> => (AMOADD_D:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5578 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5579 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5580 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5581 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5582 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5583 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5584 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D, 5585 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5586 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5587 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5588 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5589 GIR_EraseFromParent, /*InsnID*/0, 5590 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5591 // GIR_Coverage, 1015, 5592 GIR_Done, 5593 // Label 381: @12519 5594 GIM_Try, /*On fail goto*//*Label 382*/ 12590, // Rule ID 1016 // 5595 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5596 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5597 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 5598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5599 // MIs[0] addr 5600 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5602 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5603 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> => (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5604 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5605 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5606 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5607 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5608 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5609 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5610 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ, 5611 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5612 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5613 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5614 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5615 GIR_EraseFromParent, /*InsnID*/0, 5616 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5617 // GIR_Coverage, 1016, 5618 GIR_Done, 5619 // Label 382: @12590 5620 GIM_Try, /*On fail goto*//*Label 383*/ 12661, // Rule ID 1018 // 5621 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5622 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5623 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 5624 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5625 // MIs[0] addr 5626 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5628 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5629 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> => (AMOADD_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5630 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5631 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5632 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5633 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5634 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5635 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5636 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ, 5637 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5638 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5639 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5640 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5641 GIR_EraseFromParent, /*InsnID*/0, 5642 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5643 // GIR_Coverage, 1018, 5644 GIR_Done, 5645 // Label 383: @12661 5646 GIM_Try, /*On fail goto*//*Label 384*/ 12732, // Rule ID 1019 // 5647 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5648 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5649 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5650 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5651 // MIs[0] addr 5652 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5654 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5655 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> => (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5656 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5657 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5658 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5659 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5660 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5661 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5662 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL, 5663 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5664 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5665 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5666 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5667 GIR_EraseFromParent, /*InsnID*/0, 5668 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5669 // GIR_Coverage, 1019, 5670 GIR_Done, 5671 // Label 384: @12732 5672 GIM_Try, /*On fail goto*//*Label 385*/ 12803, // Rule ID 1021 // 5673 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5674 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5675 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5677 // MIs[0] addr 5678 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5680 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5681 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> => (AMOADD_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5682 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5683 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5684 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5685 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5686 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5687 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5688 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL, 5689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5690 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5691 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5692 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5693 GIR_EraseFromParent, /*InsnID*/0, 5694 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5695 // GIR_Coverage, 1021, 5696 GIR_Done, 5697 // Label 385: @12803 5698 GIM_Try, /*On fail goto*//*Label 386*/ 12874, // Rule ID 1022 // 5699 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5700 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5701 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 5702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5703 // MIs[0] addr 5704 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5707 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5708 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5709 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5710 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5711 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5712 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5713 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5714 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5715 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5716 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5717 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5718 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5719 GIR_EraseFromParent, /*InsnID*/0, 5720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5721 // GIR_Coverage, 1022, 5722 GIR_Done, 5723 // Label 386: @12874 5724 GIM_Try, /*On fail goto*//*Label 387*/ 12945, // Rule ID 1024 // 5725 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5726 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5727 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 5728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5729 // MIs[0] addr 5730 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5733 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5734 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5735 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5736 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5737 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5738 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5739 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5740 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5741 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5742 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5743 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5744 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5745 GIR_EraseFromParent, /*InsnID*/0, 5746 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5747 // GIR_Coverage, 1024, 5748 GIR_Done, 5749 // Label 387: @12945 5750 GIM_Try, /*On fail goto*//*Label 388*/ 13016, // Rule ID 1025 // 5751 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5752 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5753 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 5754 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5755 // MIs[0] addr 5756 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5757 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5759 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5760 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5761 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5762 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5763 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5764 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5765 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5766 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5767 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5768 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5769 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5770 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5771 GIR_EraseFromParent, /*InsnID*/0, 5772 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5773 // GIR_Coverage, 1025, 5774 GIR_Done, 5775 // Label 388: @13016 5776 GIM_Try, /*On fail goto*//*Label 389*/ 13087, // Rule ID 1027 // 5777 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5778 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5779 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 5780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5781 // MIs[0] addr 5782 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 5783 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5784 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5785 // (atomic_load_sub:{ *:[i32] } GPR:{ *:[i32] }:$addr, GPR:{ *:[i32] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$addr, (SUB:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$incr)) 5786 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 5787 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5788 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5789 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5790 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5791 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5792 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 5793 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5794 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5795 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5796 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5797 GIR_EraseFromParent, /*InsnID*/0, 5798 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5799 // GIR_Coverage, 1027, 5800 GIR_Done, 5801 // Label 389: @13087 5802 GIM_Reject, 5803 // Label 369: @13088 5804 GIM_Reject, 5805 // Label 367: @13089 5806 GIM_Try, /*On fail goto*//*Label 390*/ 13806, 5807 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 5808 GIM_Try, /*On fail goto*//*Label 391*/ 13166, // Rule ID 786 // 5809 GIM_CheckFeatures, GIFBS_HasStdExtA, 5810 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5811 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 5812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5813 // MIs[0] addr 5814 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5815 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5816 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5817 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_monotonic>> => (AMOADD_W:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 5818 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5819 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5820 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5821 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5822 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5823 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5824 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W, 5825 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5826 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5827 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5828 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5829 GIR_EraseFromParent, /*InsnID*/0, 5830 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5831 // GIR_Coverage, 786, 5832 GIR_Done, 5833 // Label 391: @13166 5834 GIM_Try, /*On fail goto*//*Label 392*/ 13237, // Rule ID 789 // 5835 GIM_CheckFeatures, GIFBS_HasStdExtA, 5836 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5837 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 5838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5839 // MIs[0] addr 5840 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5843 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acquire>> => (AMOADD_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 5844 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5845 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5846 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5847 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5848 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5849 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5850 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ, 5851 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5852 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5853 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5854 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5855 GIR_EraseFromParent, /*InsnID*/0, 5856 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5857 // GIR_Coverage, 789, 5858 GIR_Done, 5859 // Label 392: @13237 5860 GIM_Try, /*On fail goto*//*Label 393*/ 13308, // Rule ID 792 // 5861 GIM_CheckFeatures, GIFBS_HasStdExtA, 5862 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5863 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5864 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5865 // MIs[0] addr 5866 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5867 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5869 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_release>> => (AMOADD_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 5870 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5871 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5872 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5873 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5874 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5875 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5876 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_RL, 5877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5879 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5880 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5881 GIR_EraseFromParent, /*InsnID*/0, 5882 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5883 // GIR_Coverage, 792, 5884 GIR_Done, 5885 // Label 393: @13308 5886 GIM_Try, /*On fail goto*//*Label 394*/ 13379, // Rule ID 795 // 5887 GIM_CheckFeatures, GIFBS_HasStdExtA, 5888 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5889 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 5890 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5891 // MIs[0] addr 5892 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5893 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5894 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5895 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_acq_rel>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 5896 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5897 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5898 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5899 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5900 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5901 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 5903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5905 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5906 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5907 GIR_EraseFromParent, /*InsnID*/0, 5908 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5909 // GIR_Coverage, 795, 5910 GIR_Done, 5911 // Label 394: @13379 5912 GIM_Try, /*On fail goto*//*Label 395*/ 13450, // Rule ID 798 // 5913 GIM_CheckFeatures, GIFBS_HasStdExtA, 5914 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 5915 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 5916 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5917 // MIs[0] addr 5918 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5919 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5920 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5921 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_32>><<P:Predicate_atomic_load_sub_32_seq_cst>> => (AMOADD_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 5922 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5923 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5924 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5925 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5926 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5927 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5928 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_W_AQ_RL, 5929 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5930 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5931 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5932 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5933 GIR_EraseFromParent, /*InsnID*/0, 5934 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5935 // GIR_Coverage, 798, 5936 GIR_Done, 5937 // Label 395: @13450 5938 GIM_Try, /*On fail goto*//*Label 396*/ 13521, // Rule ID 1014 // 5939 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5940 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5941 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 5942 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5943 // MIs[0] addr 5944 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5945 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5946 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5947 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_monotonic>> => (AMOADD_D:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 5948 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5949 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5950 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5951 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5952 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5953 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5954 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D, 5955 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5956 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5957 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5958 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5959 GIR_EraseFromParent, /*InsnID*/0, 5960 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5961 // GIR_Coverage, 1014, 5962 GIR_Done, 5963 // Label 396: @13521 5964 GIM_Try, /*On fail goto*//*Label 397*/ 13592, // Rule ID 1017 // 5965 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5966 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5967 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 5968 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5969 // MIs[0] addr 5970 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5973 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acquire>> => (AMOADD_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 5974 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 5975 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 5976 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 5977 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 5978 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 5979 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 5980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ, 5981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 5982 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 5983 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 5984 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 5985 GIR_EraseFromParent, /*InsnID*/0, 5986 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 5987 // GIR_Coverage, 1017, 5988 GIR_Done, 5989 // Label 397: @13592 5990 GIM_Try, /*On fail goto*//*Label 398*/ 13663, // Rule ID 1020 // 5991 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 5992 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 5993 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 5994 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 5995 // MIs[0] addr 5996 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 5997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 5998 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 5999 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_release>> => (AMOADD_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 6000 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 6001 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 6002 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6003 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 6004 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 6005 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6006 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_RL, 6007 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6008 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 6009 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6010 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 6011 GIR_EraseFromParent, /*InsnID*/0, 6012 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6013 // GIR_Coverage, 1020, 6014 GIR_Done, 6015 // Label 398: @13663 6016 GIM_Try, /*On fail goto*//*Label 399*/ 13734, // Rule ID 1023 // 6017 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6018 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6019 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6021 // MIs[0] addr 6022 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6025 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_acq_rel>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 6026 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 6027 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 6028 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6029 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 6030 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 6031 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6032 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 6033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6034 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 6035 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6036 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 6037 GIR_EraseFromParent, /*InsnID*/0, 6038 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6039 // GIR_Coverage, 1023, 6040 GIR_Done, 6041 // Label 399: @13734 6042 GIM_Try, /*On fail goto*//*Label 400*/ 13805, // Rule ID 1026 // 6043 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6044 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6045 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6047 // MIs[0] addr 6048 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6051 // (atomic_load_sub:{ *:[i64] } GPR:{ *:[i64] }:$addr, GPR:{ *:[i64] }:$incr)<<P:Predicate_atomic_load_sub_64>><<P:Predicate_atomic_load_sub_64_seq_cst>> => (AMOADD_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$addr, (SUB:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$incr)) 6052 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 6053 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SUB, 6054 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 6055 GIR_AddRegister, /*InsnID*/1, RISCV::X0, /*AddRegisterRegFlags*/0, 6056 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // incr 6057 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 6058 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AMOADD_D_AQ_RL, 6059 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 6060 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // addr 6061 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 6062 GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList, 6063 GIR_EraseFromParent, /*InsnID*/0, 6064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6065 // GIR_Coverage, 1026, 6066 GIR_Done, 6067 // Label 400: @13805 6068 GIM_Reject, 6069 // Label 390: @13806 6070 GIM_Reject, 6071 // Label 368: @13807 6072 GIM_Reject, 6073 // Label 19: @13808 6074 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 403*/ 14852, 6075 /*GILLT_s32*//*Label 401*/ 13816, 6076 /*GILLT_s64*//*Label 402*/ 14504, 6077 // Label 401: @13816 6078 GIM_Try, /*On fail goto*//*Label 404*/ 14503, 6079 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6080 GIM_Try, /*On fail goto*//*Label 405*/ 13856, // Rule ID 680 // 6081 GIM_CheckFeatures, GIFBS_HasStdExtA, 6082 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6083 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6085 // MIs[0] rs1 6086 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6088 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6089 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6090 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W, 6091 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6092 // GIR_Coverage, 680, 6093 GIR_Done, 6094 // Label 405: @13856 6095 GIM_Try, /*On fail goto*//*Label 406*/ 13890, // Rule ID 682 // 6096 GIM_CheckFeatures, GIFBS_HasStdExtA, 6097 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6098 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6100 // MIs[0] rs1 6101 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6103 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6104 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> => (AMOAND_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6105 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W, 6106 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6107 // GIR_Coverage, 682, 6108 GIR_Done, 6109 // Label 406: @13890 6110 GIM_Try, /*On fail goto*//*Label 407*/ 13924, // Rule ID 683 // 6111 GIM_CheckFeatures, GIFBS_HasStdExtA, 6112 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6113 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6115 // MIs[0] rs1 6116 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6118 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6119 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> => (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6120 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ, 6121 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6122 // GIR_Coverage, 683, 6123 GIR_Done, 6124 // Label 407: @13924 6125 GIM_Try, /*On fail goto*//*Label 408*/ 13958, // Rule ID 685 // 6126 GIM_CheckFeatures, GIFBS_HasStdExtA, 6127 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6128 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6130 // MIs[0] rs1 6131 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6133 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6134 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> => (AMOAND_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6135 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ, 6136 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6137 // GIR_Coverage, 685, 6138 GIR_Done, 6139 // Label 408: @13958 6140 GIM_Try, /*On fail goto*//*Label 409*/ 13992, // Rule ID 686 // 6141 GIM_CheckFeatures, GIFBS_HasStdExtA, 6142 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6143 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6145 // MIs[0] rs1 6146 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6148 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6149 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> => (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6150 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_RL, 6151 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6152 // GIR_Coverage, 686, 6153 GIR_Done, 6154 // Label 409: @13992 6155 GIM_Try, /*On fail goto*//*Label 410*/ 14026, // Rule ID 688 // 6156 GIM_CheckFeatures, GIFBS_HasStdExtA, 6157 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6158 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6160 // MIs[0] rs1 6161 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6164 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> => (AMOAND_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6165 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_RL, 6166 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6167 // GIR_Coverage, 688, 6168 GIR_Done, 6169 // Label 410: @14026 6170 GIM_Try, /*On fail goto*//*Label 411*/ 14060, // Rule ID 689 // 6171 GIM_CheckFeatures, GIFBS_HasStdExtA, 6172 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6173 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6175 // MIs[0] rs1 6176 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6178 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6179 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6180 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL, 6181 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6182 // GIR_Coverage, 689, 6183 GIR_Done, 6184 // Label 411: @14060 6185 GIM_Try, /*On fail goto*//*Label 412*/ 14094, // Rule ID 691 // 6186 GIM_CheckFeatures, GIFBS_HasStdExtA, 6187 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6188 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6190 // MIs[0] rs1 6191 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6192 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6193 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6194 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6195 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL, 6196 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6197 // GIR_Coverage, 691, 6198 GIR_Done, 6199 // Label 412: @14094 6200 GIM_Try, /*On fail goto*//*Label 413*/ 14128, // Rule ID 692 // 6201 GIM_CheckFeatures, GIFBS_HasStdExtA, 6202 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6203 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6205 // MIs[0] rs1 6206 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6207 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6208 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6209 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6210 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL, 6211 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6212 // GIR_Coverage, 692, 6213 GIR_Done, 6214 // Label 413: @14128 6215 GIM_Try, /*On fail goto*//*Label 414*/ 14162, // Rule ID 694 // 6216 GIM_CheckFeatures, GIFBS_HasStdExtA, 6217 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6218 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6220 // MIs[0] rs1 6221 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6223 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6224 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6225 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL, 6226 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6227 // GIR_Coverage, 694, 6228 GIR_Done, 6229 // Label 414: @14162 6230 GIM_Try, /*On fail goto*//*Label 415*/ 14196, // Rule ID 908 // 6231 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6232 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6233 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6235 // MIs[0] rs1 6236 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6238 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6239 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> => (AMOAND_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6240 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D, 6241 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6242 // GIR_Coverage, 908, 6243 GIR_Done, 6244 // Label 415: @14196 6245 GIM_Try, /*On fail goto*//*Label 416*/ 14230, // Rule ID 910 // 6246 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6247 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6248 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6250 // MIs[0] rs1 6251 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6252 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6253 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6254 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> => (AMOAND_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6255 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D, 6256 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6257 // GIR_Coverage, 910, 6258 GIR_Done, 6259 // Label 416: @14230 6260 GIM_Try, /*On fail goto*//*Label 417*/ 14264, // Rule ID 911 // 6261 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6262 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6263 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6265 // MIs[0] rs1 6266 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6267 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6268 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6269 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> => (AMOAND_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6270 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ, 6271 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6272 // GIR_Coverage, 911, 6273 GIR_Done, 6274 // Label 417: @14264 6275 GIM_Try, /*On fail goto*//*Label 418*/ 14298, // Rule ID 913 // 6276 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6277 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6278 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6280 // MIs[0] rs1 6281 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6283 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6284 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> => (AMOAND_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6285 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ, 6286 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6287 // GIR_Coverage, 913, 6288 GIR_Done, 6289 // Label 418: @14298 6290 GIM_Try, /*On fail goto*//*Label 419*/ 14332, // Rule ID 914 // 6291 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6292 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6293 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6295 // MIs[0] rs1 6296 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6297 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6299 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> => (AMOAND_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6300 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_RL, 6301 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6302 // GIR_Coverage, 914, 6303 GIR_Done, 6304 // Label 419: @14332 6305 GIM_Try, /*On fail goto*//*Label 420*/ 14366, // Rule ID 916 // 6306 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6307 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6308 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6310 // MIs[0] rs1 6311 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6312 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6313 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6314 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> => (AMOAND_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6315 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_RL, 6316 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6317 // GIR_Coverage, 916, 6318 GIR_Done, 6319 // Label 420: @14366 6320 GIM_Try, /*On fail goto*//*Label 421*/ 14400, // Rule ID 917 // 6321 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6322 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6323 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6324 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6325 // MIs[0] rs1 6326 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6327 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6328 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6329 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> => (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6330 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL, 6331 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6332 // GIR_Coverage, 917, 6333 GIR_Done, 6334 // Label 421: @14400 6335 GIM_Try, /*On fail goto*//*Label 422*/ 14434, // Rule ID 919 // 6336 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6337 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6338 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6339 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6340 // MIs[0] rs1 6341 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6342 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6343 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6344 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> => (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6345 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL, 6346 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6347 // GIR_Coverage, 919, 6348 GIR_Done, 6349 // Label 422: @14434 6350 GIM_Try, /*On fail goto*//*Label 423*/ 14468, // Rule ID 920 // 6351 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6352 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6353 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6354 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6355 // MIs[0] rs1 6356 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6357 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6358 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6359 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> => (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6360 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL, 6361 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6362 // GIR_Coverage, 920, 6363 GIR_Done, 6364 // Label 423: @14468 6365 GIM_Try, /*On fail goto*//*Label 424*/ 14502, // Rule ID 922 // 6366 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6367 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6368 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6370 // MIs[0] rs1 6371 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6372 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6373 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6374 // (atomic_load_and:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> => (AMOAND_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6375 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL, 6376 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6377 // GIR_Coverage, 922, 6378 GIR_Done, 6379 // Label 424: @14502 6380 GIM_Reject, 6381 // Label 404: @14503 6382 GIM_Reject, 6383 // Label 402: @14504 6384 GIM_Try, /*On fail goto*//*Label 425*/ 14851, 6385 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6386 GIM_Try, /*On fail goto*//*Label 426*/ 14544, // Rule ID 681 // 6387 GIM_CheckFeatures, GIFBS_HasStdExtA, 6388 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6389 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6391 // MIs[0] rs1 6392 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6393 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6394 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6395 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_monotonic>> => (AMOAND_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6396 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W, 6397 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6398 // GIR_Coverage, 681, 6399 GIR_Done, 6400 // Label 426: @14544 6401 GIM_Try, /*On fail goto*//*Label 427*/ 14578, // Rule ID 684 // 6402 GIM_CheckFeatures, GIFBS_HasStdExtA, 6403 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6404 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6406 // MIs[0] rs1 6407 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6408 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6409 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6410 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acquire>> => (AMOAND_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6411 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ, 6412 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6413 // GIR_Coverage, 684, 6414 GIR_Done, 6415 // Label 427: @14578 6416 GIM_Try, /*On fail goto*//*Label 428*/ 14612, // Rule ID 687 // 6417 GIM_CheckFeatures, GIFBS_HasStdExtA, 6418 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6419 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6421 // MIs[0] rs1 6422 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6423 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6425 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_release>> => (AMOAND_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6426 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_RL, 6427 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6428 // GIR_Coverage, 687, 6429 GIR_Done, 6430 // Label 428: @14612 6431 GIM_Try, /*On fail goto*//*Label 429*/ 14646, // Rule ID 690 // 6432 GIM_CheckFeatures, GIFBS_HasStdExtA, 6433 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6434 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6436 // MIs[0] rs1 6437 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6438 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6440 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_acq_rel>> => (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6441 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL, 6442 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6443 // GIR_Coverage, 690, 6444 GIR_Done, 6445 // Label 429: @14646 6446 GIM_Try, /*On fail goto*//*Label 430*/ 14680, // Rule ID 693 // 6447 GIM_CheckFeatures, GIFBS_HasStdExtA, 6448 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6449 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6451 // MIs[0] rs1 6452 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6453 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6455 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_32>><<P:Predicate_atomic_load_and_32_seq_cst>> => (AMOAND_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6456 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_W_AQ_RL, 6457 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6458 // GIR_Coverage, 693, 6459 GIR_Done, 6460 // Label 430: @14680 6461 GIM_Try, /*On fail goto*//*Label 431*/ 14714, // Rule ID 909 // 6462 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6463 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6464 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6466 // MIs[0] rs1 6467 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6470 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_monotonic>> => (AMOAND_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6471 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D, 6472 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6473 // GIR_Coverage, 909, 6474 GIR_Done, 6475 // Label 431: @14714 6476 GIM_Try, /*On fail goto*//*Label 432*/ 14748, // Rule ID 912 // 6477 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6478 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6479 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6480 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6481 // MIs[0] rs1 6482 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6483 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6485 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acquire>> => (AMOAND_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6486 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ, 6487 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6488 // GIR_Coverage, 912, 6489 GIR_Done, 6490 // Label 432: @14748 6491 GIM_Try, /*On fail goto*//*Label 433*/ 14782, // Rule ID 915 // 6492 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6493 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6494 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6495 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6496 // MIs[0] rs1 6497 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6498 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6500 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_release>> => (AMOAND_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6501 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_RL, 6502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6503 // GIR_Coverage, 915, 6504 GIR_Done, 6505 // Label 433: @14782 6506 GIM_Try, /*On fail goto*//*Label 434*/ 14816, // Rule ID 918 // 6507 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6508 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6509 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6510 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6511 // MIs[0] rs1 6512 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6513 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6515 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_acq_rel>> => (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6516 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL, 6517 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6518 // GIR_Coverage, 918, 6519 GIR_Done, 6520 // Label 434: @14816 6521 GIM_Try, /*On fail goto*//*Label 435*/ 14850, // Rule ID 921 // 6522 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6523 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6524 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6525 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6526 // MIs[0] rs1 6527 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6528 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6530 // (atomic_load_and:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_and_64>><<P:Predicate_atomic_load_and_64_seq_cst>> => (AMOAND_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6531 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOAND_D_AQ_RL, 6532 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6533 // GIR_Coverage, 921, 6534 GIR_Done, 6535 // Label 435: @14850 6536 GIM_Reject, 6537 // Label 425: @14851 6538 GIM_Reject, 6539 // Label 403: @14852 6540 GIM_Reject, 6541 // Label 20: @14853 6542 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 438*/ 15897, 6543 /*GILLT_s32*//*Label 436*/ 14861, 6544 /*GILLT_s64*//*Label 437*/ 15549, 6545 // Label 436: @14861 6546 GIM_Try, /*On fail goto*//*Label 439*/ 15548, 6547 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 6548 GIM_Try, /*On fail goto*//*Label 440*/ 14901, // Rule ID 695 // 6549 GIM_CheckFeatures, GIFBS_HasStdExtA, 6550 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6551 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6553 // MIs[0] rs1 6554 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6555 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6556 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6557 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6558 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W, 6559 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6560 // GIR_Coverage, 695, 6561 GIR_Done, 6562 // Label 440: @14901 6563 GIM_Try, /*On fail goto*//*Label 441*/ 14935, // Rule ID 697 // 6564 GIM_CheckFeatures, GIFBS_HasStdExtA, 6565 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6566 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6568 // MIs[0] rs1 6569 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6570 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6571 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6572 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> => (AMOOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6573 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W, 6574 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6575 // GIR_Coverage, 697, 6576 GIR_Done, 6577 // Label 441: @14935 6578 GIM_Try, /*On fail goto*//*Label 442*/ 14969, // Rule ID 698 // 6579 GIM_CheckFeatures, GIFBS_HasStdExtA, 6580 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6581 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6583 // MIs[0] rs1 6584 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6585 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6586 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6587 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> => (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6588 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ, 6589 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6590 // GIR_Coverage, 698, 6591 GIR_Done, 6592 // Label 442: @14969 6593 GIM_Try, /*On fail goto*//*Label 443*/ 15003, // Rule ID 700 // 6594 GIM_CheckFeatures, GIFBS_HasStdExtA, 6595 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6596 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6598 // MIs[0] rs1 6599 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6600 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6601 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6602 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> => (AMOOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6603 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ, 6604 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6605 // GIR_Coverage, 700, 6606 GIR_Done, 6607 // Label 443: @15003 6608 GIM_Try, /*On fail goto*//*Label 444*/ 15037, // Rule ID 701 // 6609 GIM_CheckFeatures, GIFBS_HasStdExtA, 6610 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6611 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6613 // MIs[0] rs1 6614 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6615 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6616 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6617 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> => (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6618 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_RL, 6619 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6620 // GIR_Coverage, 701, 6621 GIR_Done, 6622 // Label 444: @15037 6623 GIM_Try, /*On fail goto*//*Label 445*/ 15071, // Rule ID 703 // 6624 GIM_CheckFeatures, GIFBS_HasStdExtA, 6625 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6626 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6628 // MIs[0] rs1 6629 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6630 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6631 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6632 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> => (AMOOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6633 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_RL, 6634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6635 // GIR_Coverage, 703, 6636 GIR_Done, 6637 // Label 445: @15071 6638 GIM_Try, /*On fail goto*//*Label 446*/ 15105, // Rule ID 704 // 6639 GIM_CheckFeatures, GIFBS_HasStdExtA, 6640 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6641 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6643 // MIs[0] rs1 6644 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6645 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6646 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6647 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6648 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL, 6649 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6650 // GIR_Coverage, 704, 6651 GIR_Done, 6652 // Label 446: @15105 6653 GIM_Try, /*On fail goto*//*Label 447*/ 15139, // Rule ID 706 // 6654 GIM_CheckFeatures, GIFBS_HasStdExtA, 6655 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6656 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6658 // MIs[0] rs1 6659 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6662 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6663 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL, 6664 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6665 // GIR_Coverage, 706, 6666 GIR_Done, 6667 // Label 447: @15139 6668 GIM_Try, /*On fail goto*//*Label 448*/ 15173, // Rule ID 707 // 6669 GIM_CheckFeatures, GIFBS_HasStdExtA, 6670 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6671 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6673 // MIs[0] rs1 6674 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6675 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6677 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6678 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL, 6679 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6680 // GIR_Coverage, 707, 6681 GIR_Done, 6682 // Label 448: @15173 6683 GIM_Try, /*On fail goto*//*Label 449*/ 15207, // Rule ID 709 // 6684 GIM_CheckFeatures, GIFBS_HasStdExtA, 6685 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6686 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6688 // MIs[0] rs1 6689 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6690 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6691 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6692 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6693 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL, 6694 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6695 // GIR_Coverage, 709, 6696 GIR_Done, 6697 // Label 449: @15207 6698 GIM_Try, /*On fail goto*//*Label 450*/ 15241, // Rule ID 923 // 6699 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6700 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6701 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6703 // MIs[0] rs1 6704 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6706 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6707 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> => (AMOOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6708 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D, 6709 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6710 // GIR_Coverage, 923, 6711 GIR_Done, 6712 // Label 450: @15241 6713 GIM_Try, /*On fail goto*//*Label 451*/ 15275, // Rule ID 925 // 6714 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6715 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6716 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6718 // MIs[0] rs1 6719 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6722 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> => (AMOOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6723 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D, 6724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6725 // GIR_Coverage, 925, 6726 GIR_Done, 6727 // Label 451: @15275 6728 GIM_Try, /*On fail goto*//*Label 452*/ 15309, // Rule ID 926 // 6729 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6730 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6731 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6733 // MIs[0] rs1 6734 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6736 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6737 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> => (AMOOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6738 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ, 6739 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6740 // GIR_Coverage, 926, 6741 GIR_Done, 6742 // Label 452: @15309 6743 GIM_Try, /*On fail goto*//*Label 453*/ 15343, // Rule ID 928 // 6744 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6745 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6746 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6748 // MIs[0] rs1 6749 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6750 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6751 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6752 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> => (AMOOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6753 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ, 6754 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6755 // GIR_Coverage, 928, 6756 GIR_Done, 6757 // Label 453: @15343 6758 GIM_Try, /*On fail goto*//*Label 454*/ 15377, // Rule ID 929 // 6759 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6760 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6761 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6763 // MIs[0] rs1 6764 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6765 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6766 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6767 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> => (AMOOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6768 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_RL, 6769 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6770 // GIR_Coverage, 929, 6771 GIR_Done, 6772 // Label 454: @15377 6773 GIM_Try, /*On fail goto*//*Label 455*/ 15411, // Rule ID 931 // 6774 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6775 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6776 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6778 // MIs[0] rs1 6779 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6780 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6781 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6782 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> => (AMOOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6783 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_RL, 6784 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6785 // GIR_Coverage, 931, 6786 GIR_Done, 6787 // Label 455: @15411 6788 GIM_Try, /*On fail goto*//*Label 456*/ 15445, // Rule ID 932 // 6789 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6790 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6791 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6792 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6793 // MIs[0] rs1 6794 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6795 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6796 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6797 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> => (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6798 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL, 6799 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6800 // GIR_Coverage, 932, 6801 GIR_Done, 6802 // Label 456: @15445 6803 GIM_Try, /*On fail goto*//*Label 457*/ 15479, // Rule ID 934 // 6804 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6805 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6806 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6807 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6808 // MIs[0] rs1 6809 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6810 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6811 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6812 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> => (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6813 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL, 6814 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6815 // GIR_Coverage, 934, 6816 GIR_Done, 6817 // Label 457: @15479 6818 GIM_Try, /*On fail goto*//*Label 458*/ 15513, // Rule ID 935 // 6819 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6820 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6821 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6822 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6823 // MIs[0] rs1 6824 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6825 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6826 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6827 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> => (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6828 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL, 6829 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6830 // GIR_Coverage, 935, 6831 GIR_Done, 6832 // Label 458: @15513 6833 GIM_Try, /*On fail goto*//*Label 459*/ 15547, // Rule ID 937 // 6834 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6835 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6836 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6837 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6838 // MIs[0] rs1 6839 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 6840 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6841 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6842 // (atomic_load_or:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> => (AMOOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 6843 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL, 6844 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6845 // GIR_Coverage, 937, 6846 GIR_Done, 6847 // Label 459: @15547 6848 GIM_Reject, 6849 // Label 439: @15548 6850 GIM_Reject, 6851 // Label 437: @15549 6852 GIM_Try, /*On fail goto*//*Label 460*/ 15896, 6853 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 6854 GIM_Try, /*On fail goto*//*Label 461*/ 15589, // Rule ID 696 // 6855 GIM_CheckFeatures, GIFBS_HasStdExtA, 6856 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6857 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6859 // MIs[0] rs1 6860 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6861 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6862 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6863 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_monotonic>> => (AMOOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6864 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W, 6865 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6866 // GIR_Coverage, 696, 6867 GIR_Done, 6868 // Label 461: @15589 6869 GIM_Try, /*On fail goto*//*Label 462*/ 15623, // Rule ID 699 // 6870 GIM_CheckFeatures, GIFBS_HasStdExtA, 6871 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6872 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6874 // MIs[0] rs1 6875 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6876 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6877 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6878 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acquire>> => (AMOOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6879 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ, 6880 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6881 // GIR_Coverage, 699, 6882 GIR_Done, 6883 // Label 462: @15623 6884 GIM_Try, /*On fail goto*//*Label 463*/ 15657, // Rule ID 702 // 6885 GIM_CheckFeatures, GIFBS_HasStdExtA, 6886 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6887 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6889 // MIs[0] rs1 6890 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6891 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6893 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_release>> => (AMOOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6894 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_RL, 6895 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6896 // GIR_Coverage, 702, 6897 GIR_Done, 6898 // Label 463: @15657 6899 GIM_Try, /*On fail goto*//*Label 464*/ 15691, // Rule ID 705 // 6900 GIM_CheckFeatures, GIFBS_HasStdExtA, 6901 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6902 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6904 // MIs[0] rs1 6905 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6906 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6908 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_acq_rel>> => (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6909 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL, 6910 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6911 // GIR_Coverage, 705, 6912 GIR_Done, 6913 // Label 464: @15691 6914 GIM_Try, /*On fail goto*//*Label 465*/ 15725, // Rule ID 708 // 6915 GIM_CheckFeatures, GIFBS_HasStdExtA, 6916 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 6917 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6919 // MIs[0] rs1 6920 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6921 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6923 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_32>><<P:Predicate_atomic_load_or_32_seq_cst>> => (AMOOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6924 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_W_AQ_RL, 6925 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6926 // GIR_Coverage, 708, 6927 GIR_Done, 6928 // Label 465: @15725 6929 GIM_Try, /*On fail goto*//*Label 466*/ 15759, // Rule ID 924 // 6930 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6931 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6932 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 6933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6934 // MIs[0] rs1 6935 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6938 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_monotonic>> => (AMOOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6939 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D, 6940 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6941 // GIR_Coverage, 924, 6942 GIR_Done, 6943 // Label 466: @15759 6944 GIM_Try, /*On fail goto*//*Label 467*/ 15793, // Rule ID 927 // 6945 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6946 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6947 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 6948 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6949 // MIs[0] rs1 6950 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6951 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6953 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acquire>> => (AMOOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6954 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ, 6955 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6956 // GIR_Coverage, 927, 6957 GIR_Done, 6958 // Label 467: @15793 6959 GIM_Try, /*On fail goto*//*Label 468*/ 15827, // Rule ID 930 // 6960 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6961 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6962 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 6963 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6964 // MIs[0] rs1 6965 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6966 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6968 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_release>> => (AMOOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6969 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_RL, 6970 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6971 // GIR_Coverage, 930, 6972 GIR_Done, 6973 // Label 468: @15827 6974 GIM_Try, /*On fail goto*//*Label 469*/ 15861, // Rule ID 933 // 6975 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6976 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6977 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 6978 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6979 // MIs[0] rs1 6980 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6981 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6983 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_acq_rel>> => (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6984 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL, 6985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 6986 // GIR_Coverage, 933, 6987 GIR_Done, 6988 // Label 469: @15861 6989 GIM_Try, /*On fail goto*//*Label 470*/ 15895, // Rule ID 936 // 6990 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 6991 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 6992 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 6993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 6994 // MIs[0] rs1 6995 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 6996 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 6997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 6998 // (atomic_load_or:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_or_64>><<P:Predicate_atomic_load_or_64_seq_cst>> => (AMOOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 6999 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOOR_D_AQ_RL, 7000 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7001 // GIR_Coverage, 936, 7002 GIR_Done, 7003 // Label 470: @15895 7004 GIM_Reject, 7005 // Label 460: @15896 7006 GIM_Reject, 7007 // Label 438: @15897 7008 GIM_Reject, 7009 // Label 21: @15898 7010 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 473*/ 16942, 7011 /*GILLT_s32*//*Label 471*/ 15906, 7012 /*GILLT_s64*//*Label 472*/ 16594, 7013 // Label 471: @15906 7014 GIM_Try, /*On fail goto*//*Label 474*/ 16593, 7015 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7016 GIM_Try, /*On fail goto*//*Label 475*/ 15946, // Rule ID 710 // 7017 GIM_CheckFeatures, GIFBS_HasStdExtA, 7018 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7019 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7021 // MIs[0] rs1 7022 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7023 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7025 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7026 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W, 7027 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7028 // GIR_Coverage, 710, 7029 GIR_Done, 7030 // Label 475: @15946 7031 GIM_Try, /*On fail goto*//*Label 476*/ 15980, // Rule ID 712 // 7032 GIM_CheckFeatures, GIFBS_HasStdExtA, 7033 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7034 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7036 // MIs[0] rs1 7037 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7038 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7039 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7040 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> => (AMOXOR_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7041 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W, 7042 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7043 // GIR_Coverage, 712, 7044 GIR_Done, 7045 // Label 476: @15980 7046 GIM_Try, /*On fail goto*//*Label 477*/ 16014, // Rule ID 713 // 7047 GIM_CheckFeatures, GIFBS_HasStdExtA, 7048 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7049 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7051 // MIs[0] rs1 7052 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7053 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7054 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7055 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> => (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7056 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ, 7057 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7058 // GIR_Coverage, 713, 7059 GIR_Done, 7060 // Label 477: @16014 7061 GIM_Try, /*On fail goto*//*Label 478*/ 16048, // Rule ID 715 // 7062 GIM_CheckFeatures, GIFBS_HasStdExtA, 7063 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7064 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7066 // MIs[0] rs1 7067 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7068 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7069 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7070 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> => (AMOXOR_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7071 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ, 7072 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7073 // GIR_Coverage, 715, 7074 GIR_Done, 7075 // Label 478: @16048 7076 GIM_Try, /*On fail goto*//*Label 479*/ 16082, // Rule ID 716 // 7077 GIM_CheckFeatures, GIFBS_HasStdExtA, 7078 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7079 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7081 // MIs[0] rs1 7082 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7083 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7084 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7085 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> => (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7086 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_RL, 7087 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7088 // GIR_Coverage, 716, 7089 GIR_Done, 7090 // Label 479: @16082 7091 GIM_Try, /*On fail goto*//*Label 480*/ 16116, // Rule ID 718 // 7092 GIM_CheckFeatures, GIFBS_HasStdExtA, 7093 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7094 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7096 // MIs[0] rs1 7097 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7098 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7099 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7100 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> => (AMOXOR_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7101 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_RL, 7102 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7103 // GIR_Coverage, 718, 7104 GIR_Done, 7105 // Label 480: @16116 7106 GIM_Try, /*On fail goto*//*Label 481*/ 16150, // Rule ID 719 // 7107 GIM_CheckFeatures, GIFBS_HasStdExtA, 7108 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7109 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7111 // MIs[0] rs1 7112 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7115 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7116 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL, 7117 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7118 // GIR_Coverage, 719, 7119 GIR_Done, 7120 // Label 481: @16150 7121 GIM_Try, /*On fail goto*//*Label 482*/ 16184, // Rule ID 721 // 7122 GIM_CheckFeatures, GIFBS_HasStdExtA, 7123 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7124 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7126 // MIs[0] rs1 7127 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7128 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7129 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7130 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7131 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL, 7132 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7133 // GIR_Coverage, 721, 7134 GIR_Done, 7135 // Label 482: @16184 7136 GIM_Try, /*On fail goto*//*Label 483*/ 16218, // Rule ID 722 // 7137 GIM_CheckFeatures, GIFBS_HasStdExtA, 7138 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7139 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7141 // MIs[0] rs1 7142 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7143 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7144 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7145 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7146 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL, 7147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7148 // GIR_Coverage, 722, 7149 GIR_Done, 7150 // Label 483: @16218 7151 GIM_Try, /*On fail goto*//*Label 484*/ 16252, // Rule ID 724 // 7152 GIM_CheckFeatures, GIFBS_HasStdExtA, 7153 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7154 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7156 // MIs[0] rs1 7157 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7158 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7159 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7160 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7161 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL, 7162 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7163 // GIR_Coverage, 724, 7164 GIR_Done, 7165 // Label 484: @16252 7166 GIM_Try, /*On fail goto*//*Label 485*/ 16286, // Rule ID 938 // 7167 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7168 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7169 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7171 // MIs[0] rs1 7172 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7173 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7174 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7175 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> => (AMOXOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7176 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D, 7177 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7178 // GIR_Coverage, 938, 7179 GIR_Done, 7180 // Label 485: @16286 7181 GIM_Try, /*On fail goto*//*Label 486*/ 16320, // Rule ID 940 // 7182 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7183 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7184 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7186 // MIs[0] rs1 7187 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7188 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7189 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7190 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> => (AMOXOR_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7191 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D, 7192 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7193 // GIR_Coverage, 940, 7194 GIR_Done, 7195 // Label 486: @16320 7196 GIM_Try, /*On fail goto*//*Label 487*/ 16354, // Rule ID 941 // 7197 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7198 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7199 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7201 // MIs[0] rs1 7202 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7203 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7204 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7205 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> => (AMOXOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7206 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ, 7207 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7208 // GIR_Coverage, 941, 7209 GIR_Done, 7210 // Label 487: @16354 7211 GIM_Try, /*On fail goto*//*Label 488*/ 16388, // Rule ID 943 // 7212 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7213 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7214 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7216 // MIs[0] rs1 7217 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7218 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7219 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7220 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> => (AMOXOR_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7221 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ, 7222 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7223 // GIR_Coverage, 943, 7224 GIR_Done, 7225 // Label 488: @16388 7226 GIM_Try, /*On fail goto*//*Label 489*/ 16422, // Rule ID 944 // 7227 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7228 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7229 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7231 // MIs[0] rs1 7232 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7233 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7234 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7235 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> => (AMOXOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7236 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_RL, 7237 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7238 // GIR_Coverage, 944, 7239 GIR_Done, 7240 // Label 489: @16422 7241 GIM_Try, /*On fail goto*//*Label 490*/ 16456, // Rule ID 946 // 7242 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7243 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7244 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7246 // MIs[0] rs1 7247 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7248 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7249 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7250 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> => (AMOXOR_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7251 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_RL, 7252 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7253 // GIR_Coverage, 946, 7254 GIR_Done, 7255 // Label 490: @16456 7256 GIM_Try, /*On fail goto*//*Label 491*/ 16490, // Rule ID 947 // 7257 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7258 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7259 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7260 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7261 // MIs[0] rs1 7262 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7265 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> => (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7266 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL, 7267 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7268 // GIR_Coverage, 947, 7269 GIR_Done, 7270 // Label 491: @16490 7271 GIM_Try, /*On fail goto*//*Label 492*/ 16524, // Rule ID 949 // 7272 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7273 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7274 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7275 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7276 // MIs[0] rs1 7277 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7278 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7279 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7280 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> => (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7281 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL, 7282 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7283 // GIR_Coverage, 949, 7284 GIR_Done, 7285 // Label 492: @16524 7286 GIM_Try, /*On fail goto*//*Label 493*/ 16558, // Rule ID 950 // 7287 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7288 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7289 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7290 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7291 // MIs[0] rs1 7292 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7293 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7294 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7295 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> => (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7296 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL, 7297 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7298 // GIR_Coverage, 950, 7299 GIR_Done, 7300 // Label 493: @16558 7301 GIM_Try, /*On fail goto*//*Label 494*/ 16592, // Rule ID 952 // 7302 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7303 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7304 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7306 // MIs[0] rs1 7307 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7308 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7309 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7310 // (atomic_load_xor:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> => (AMOXOR_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7311 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL, 7312 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7313 // GIR_Coverage, 952, 7314 GIR_Done, 7315 // Label 494: @16592 7316 GIM_Reject, 7317 // Label 474: @16593 7318 GIM_Reject, 7319 // Label 472: @16594 7320 GIM_Try, /*On fail goto*//*Label 495*/ 16941, 7321 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7322 GIM_Try, /*On fail goto*//*Label 496*/ 16634, // Rule ID 711 // 7323 GIM_CheckFeatures, GIFBS_HasStdExtA, 7324 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7325 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7327 // MIs[0] rs1 7328 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7330 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7331 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_monotonic>> => (AMOXOR_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7332 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W, 7333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7334 // GIR_Coverage, 711, 7335 GIR_Done, 7336 // Label 496: @16634 7337 GIM_Try, /*On fail goto*//*Label 497*/ 16668, // Rule ID 714 // 7338 GIM_CheckFeatures, GIFBS_HasStdExtA, 7339 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7340 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7342 // MIs[0] rs1 7343 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7344 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7345 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7346 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acquire>> => (AMOXOR_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7347 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ, 7348 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7349 // GIR_Coverage, 714, 7350 GIR_Done, 7351 // Label 497: @16668 7352 GIM_Try, /*On fail goto*//*Label 498*/ 16702, // Rule ID 717 // 7353 GIM_CheckFeatures, GIFBS_HasStdExtA, 7354 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7355 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7357 // MIs[0] rs1 7358 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7359 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7361 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_release>> => (AMOXOR_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7362 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_RL, 7363 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7364 // GIR_Coverage, 717, 7365 GIR_Done, 7366 // Label 498: @16702 7367 GIM_Try, /*On fail goto*//*Label 499*/ 16736, // Rule ID 720 // 7368 GIM_CheckFeatures, GIFBS_HasStdExtA, 7369 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7370 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7372 // MIs[0] rs1 7373 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7374 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7375 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7376 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_acq_rel>> => (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7377 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL, 7378 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7379 // GIR_Coverage, 720, 7380 GIR_Done, 7381 // Label 499: @16736 7382 GIM_Try, /*On fail goto*//*Label 500*/ 16770, // Rule ID 723 // 7383 GIM_CheckFeatures, GIFBS_HasStdExtA, 7384 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7385 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7387 // MIs[0] rs1 7388 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7389 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7390 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7391 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_32>><<P:Predicate_atomic_load_xor_32_seq_cst>> => (AMOXOR_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7392 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_W_AQ_RL, 7393 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7394 // GIR_Coverage, 723, 7395 GIR_Done, 7396 // Label 500: @16770 7397 GIM_Try, /*On fail goto*//*Label 501*/ 16804, // Rule ID 939 // 7398 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7399 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7400 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7402 // MIs[0] rs1 7403 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7404 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7405 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7406 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_monotonic>> => (AMOXOR_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7407 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D, 7408 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7409 // GIR_Coverage, 939, 7410 GIR_Done, 7411 // Label 501: @16804 7412 GIM_Try, /*On fail goto*//*Label 502*/ 16838, // Rule ID 942 // 7413 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7414 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7415 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7416 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7417 // MIs[0] rs1 7418 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7419 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7420 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7421 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acquire>> => (AMOXOR_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7422 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ, 7423 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7424 // GIR_Coverage, 942, 7425 GIR_Done, 7426 // Label 502: @16838 7427 GIM_Try, /*On fail goto*//*Label 503*/ 16872, // Rule ID 945 // 7428 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7429 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7430 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7431 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7432 // MIs[0] rs1 7433 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7434 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7435 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7436 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_release>> => (AMOXOR_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7437 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_RL, 7438 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7439 // GIR_Coverage, 945, 7440 GIR_Done, 7441 // Label 503: @16872 7442 GIM_Try, /*On fail goto*//*Label 504*/ 16906, // Rule ID 948 // 7443 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7444 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7445 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7446 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7447 // MIs[0] rs1 7448 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7450 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7451 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_acq_rel>> => (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7452 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL, 7453 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7454 // GIR_Coverage, 948, 7455 GIR_Done, 7456 // Label 504: @16906 7457 GIM_Try, /*On fail goto*//*Label 505*/ 16940, // Rule ID 951 // 7458 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7459 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7460 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7461 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7462 // MIs[0] rs1 7463 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7464 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7465 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7466 // (atomic_load_xor:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_xor_64>><<P:Predicate_atomic_load_xor_64_seq_cst>> => (AMOXOR_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7467 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOXOR_D_AQ_RL, 7468 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7469 // GIR_Coverage, 951, 7470 GIR_Done, 7471 // Label 505: @16940 7472 GIM_Reject, 7473 // Label 495: @16941 7474 GIM_Reject, 7475 // Label 473: @16942 7476 GIM_Reject, 7477 // Label 22: @16943 7478 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 508*/ 17987, 7479 /*GILLT_s32*//*Label 506*/ 16951, 7480 /*GILLT_s64*//*Label 507*/ 17639, 7481 // Label 506: @16951 7482 GIM_Try, /*On fail goto*//*Label 509*/ 17638, 7483 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7484 GIM_Try, /*On fail goto*//*Label 510*/ 16991, // Rule ID 725 // 7485 GIM_CheckFeatures, GIFBS_HasStdExtA, 7486 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7487 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7489 // MIs[0] rs1 7490 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7491 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7492 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7493 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7494 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W, 7495 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7496 // GIR_Coverage, 725, 7497 GIR_Done, 7498 // Label 510: @16991 7499 GIM_Try, /*On fail goto*//*Label 511*/ 17025, // Rule ID 727 // 7500 GIM_CheckFeatures, GIFBS_HasStdExtA, 7501 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7502 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7504 // MIs[0] rs1 7505 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7506 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7507 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7508 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> => (AMOMAX_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7509 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W, 7510 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7511 // GIR_Coverage, 727, 7512 GIR_Done, 7513 // Label 511: @17025 7514 GIM_Try, /*On fail goto*//*Label 512*/ 17059, // Rule ID 728 // 7515 GIM_CheckFeatures, GIFBS_HasStdExtA, 7516 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7517 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7519 // MIs[0] rs1 7520 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7522 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7523 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> => (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7524 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ, 7525 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7526 // GIR_Coverage, 728, 7527 GIR_Done, 7528 // Label 512: @17059 7529 GIM_Try, /*On fail goto*//*Label 513*/ 17093, // Rule ID 730 // 7530 GIM_CheckFeatures, GIFBS_HasStdExtA, 7531 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7532 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7534 // MIs[0] rs1 7535 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7537 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7538 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> => (AMOMAX_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7539 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ, 7540 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7541 // GIR_Coverage, 730, 7542 GIR_Done, 7543 // Label 513: @17093 7544 GIM_Try, /*On fail goto*//*Label 514*/ 17127, // Rule ID 731 // 7545 GIM_CheckFeatures, GIFBS_HasStdExtA, 7546 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7547 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7549 // MIs[0] rs1 7550 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7551 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7552 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7553 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> => (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7554 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_RL, 7555 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7556 // GIR_Coverage, 731, 7557 GIR_Done, 7558 // Label 514: @17127 7559 GIM_Try, /*On fail goto*//*Label 515*/ 17161, // Rule ID 733 // 7560 GIM_CheckFeatures, GIFBS_HasStdExtA, 7561 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7562 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7564 // MIs[0] rs1 7565 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7566 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7567 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7568 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> => (AMOMAX_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7569 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_RL, 7570 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7571 // GIR_Coverage, 733, 7572 GIR_Done, 7573 // Label 515: @17161 7574 GIM_Try, /*On fail goto*//*Label 516*/ 17195, // Rule ID 734 // 7575 GIM_CheckFeatures, GIFBS_HasStdExtA, 7576 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7577 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7579 // MIs[0] rs1 7580 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7581 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7582 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7583 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7584 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL, 7585 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7586 // GIR_Coverage, 734, 7587 GIR_Done, 7588 // Label 516: @17195 7589 GIM_Try, /*On fail goto*//*Label 517*/ 17229, // Rule ID 736 // 7590 GIM_CheckFeatures, GIFBS_HasStdExtA, 7591 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7592 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7594 // MIs[0] rs1 7595 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7596 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7597 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7598 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7599 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL, 7600 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7601 // GIR_Coverage, 736, 7602 GIR_Done, 7603 // Label 517: @17229 7604 GIM_Try, /*On fail goto*//*Label 518*/ 17263, // Rule ID 737 // 7605 GIM_CheckFeatures, GIFBS_HasStdExtA, 7606 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7607 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7609 // MIs[0] rs1 7610 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7611 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7612 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7613 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7614 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL, 7615 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7616 // GIR_Coverage, 737, 7617 GIR_Done, 7618 // Label 518: @17263 7619 GIM_Try, /*On fail goto*//*Label 519*/ 17297, // Rule ID 739 // 7620 GIM_CheckFeatures, GIFBS_HasStdExtA, 7621 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7622 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7624 // MIs[0] rs1 7625 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7626 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7627 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7628 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7629 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL, 7630 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7631 // GIR_Coverage, 739, 7632 GIR_Done, 7633 // Label 519: @17297 7634 GIM_Try, /*On fail goto*//*Label 520*/ 17331, // Rule ID 953 // 7635 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7636 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7637 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7639 // MIs[0] rs1 7640 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7641 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7642 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7643 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> => (AMOMAX_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7644 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D, 7645 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7646 // GIR_Coverage, 953, 7647 GIR_Done, 7648 // Label 520: @17331 7649 GIM_Try, /*On fail goto*//*Label 521*/ 17365, // Rule ID 955 // 7650 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7651 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7652 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7654 // MIs[0] rs1 7655 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7657 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7658 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> => (AMOMAX_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7659 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D, 7660 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7661 // GIR_Coverage, 955, 7662 GIR_Done, 7663 // Label 521: @17365 7664 GIM_Try, /*On fail goto*//*Label 522*/ 17399, // Rule ID 956 // 7665 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7666 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7667 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7669 // MIs[0] rs1 7670 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7671 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7672 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7673 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> => (AMOMAX_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7674 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ, 7675 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7676 // GIR_Coverage, 956, 7677 GIR_Done, 7678 // Label 522: @17399 7679 GIM_Try, /*On fail goto*//*Label 523*/ 17433, // Rule ID 958 // 7680 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7681 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7682 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7684 // MIs[0] rs1 7685 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7686 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7687 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7688 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> => (AMOMAX_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7689 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ, 7690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7691 // GIR_Coverage, 958, 7692 GIR_Done, 7693 // Label 523: @17433 7694 GIM_Try, /*On fail goto*//*Label 524*/ 17467, // Rule ID 959 // 7695 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7696 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7697 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7699 // MIs[0] rs1 7700 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7702 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7703 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> => (AMOMAX_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7704 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_RL, 7705 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7706 // GIR_Coverage, 959, 7707 GIR_Done, 7708 // Label 524: @17467 7709 GIM_Try, /*On fail goto*//*Label 525*/ 17501, // Rule ID 961 // 7710 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7711 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7712 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7714 // MIs[0] rs1 7715 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7716 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7717 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7718 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> => (AMOMAX_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7719 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_RL, 7720 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7721 // GIR_Coverage, 961, 7722 GIR_Done, 7723 // Label 525: @17501 7724 GIM_Try, /*On fail goto*//*Label 526*/ 17535, // Rule ID 962 // 7725 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7726 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7727 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7728 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7729 // MIs[0] rs1 7730 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7731 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7732 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7733 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> => (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7734 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL, 7735 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7736 // GIR_Coverage, 962, 7737 GIR_Done, 7738 // Label 526: @17535 7739 GIM_Try, /*On fail goto*//*Label 527*/ 17569, // Rule ID 964 // 7740 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7741 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7742 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7743 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7744 // MIs[0] rs1 7745 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7747 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7748 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> => (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7749 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL, 7750 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7751 // GIR_Coverage, 964, 7752 GIR_Done, 7753 // Label 527: @17569 7754 GIM_Try, /*On fail goto*//*Label 528*/ 17603, // Rule ID 965 // 7755 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7756 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7757 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7758 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7759 // MIs[0] rs1 7760 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7761 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7762 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7763 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> => (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7764 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL, 7765 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7766 // GIR_Coverage, 965, 7767 GIR_Done, 7768 // Label 528: @17603 7769 GIM_Try, /*On fail goto*//*Label 529*/ 17637, // Rule ID 967 // 7770 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7771 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7772 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7773 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7774 // MIs[0] rs1 7775 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7776 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7777 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7778 // (atomic_load_max:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> => (AMOMAX_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7779 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL, 7780 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7781 // GIR_Coverage, 967, 7782 GIR_Done, 7783 // Label 529: @17637 7784 GIM_Reject, 7785 // Label 509: @17638 7786 GIM_Reject, 7787 // Label 507: @17639 7788 GIM_Try, /*On fail goto*//*Label 530*/ 17986, 7789 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 7790 GIM_Try, /*On fail goto*//*Label 531*/ 17679, // Rule ID 726 // 7791 GIM_CheckFeatures, GIFBS_HasStdExtA, 7792 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7793 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7795 // MIs[0] rs1 7796 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7797 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7798 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7799 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_monotonic>> => (AMOMAX_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7800 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W, 7801 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7802 // GIR_Coverage, 726, 7803 GIR_Done, 7804 // Label 531: @17679 7805 GIM_Try, /*On fail goto*//*Label 532*/ 17713, // Rule ID 729 // 7806 GIM_CheckFeatures, GIFBS_HasStdExtA, 7807 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7808 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7810 // MIs[0] rs1 7811 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7812 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7813 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7814 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acquire>> => (AMOMAX_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7815 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ, 7816 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7817 // GIR_Coverage, 729, 7818 GIR_Done, 7819 // Label 532: @17713 7820 GIM_Try, /*On fail goto*//*Label 533*/ 17747, // Rule ID 732 // 7821 GIM_CheckFeatures, GIFBS_HasStdExtA, 7822 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7823 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7825 // MIs[0] rs1 7826 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7829 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_release>> => (AMOMAX_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7830 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_RL, 7831 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7832 // GIR_Coverage, 732, 7833 GIR_Done, 7834 // Label 533: @17747 7835 GIM_Try, /*On fail goto*//*Label 534*/ 17781, // Rule ID 735 // 7836 GIM_CheckFeatures, GIFBS_HasStdExtA, 7837 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7838 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7840 // MIs[0] rs1 7841 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7844 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_acq_rel>> => (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7845 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL, 7846 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7847 // GIR_Coverage, 735, 7848 GIR_Done, 7849 // Label 534: @17781 7850 GIM_Try, /*On fail goto*//*Label 535*/ 17815, // Rule ID 738 // 7851 GIM_CheckFeatures, GIFBS_HasStdExtA, 7852 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7853 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7855 // MIs[0] rs1 7856 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7859 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_32>><<P:Predicate_atomic_load_max_32_seq_cst>> => (AMOMAX_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7860 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_W_AQ_RL, 7861 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7862 // GIR_Coverage, 738, 7863 GIR_Done, 7864 // Label 535: @17815 7865 GIM_Try, /*On fail goto*//*Label 536*/ 17849, // Rule ID 954 // 7866 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7867 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7868 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7870 // MIs[0] rs1 7871 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7872 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7873 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7874 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_monotonic>> => (AMOMAX_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7875 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D, 7876 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7877 // GIR_Coverage, 954, 7878 GIR_Done, 7879 // Label 536: @17849 7880 GIM_Try, /*On fail goto*//*Label 537*/ 17883, // Rule ID 957 // 7881 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7882 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7883 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7884 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7885 // MIs[0] rs1 7886 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7889 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acquire>> => (AMOMAX_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7890 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ, 7891 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7892 // GIR_Coverage, 957, 7893 GIR_Done, 7894 // Label 537: @17883 7895 GIM_Try, /*On fail goto*//*Label 538*/ 17917, // Rule ID 960 // 7896 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7897 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7898 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 7899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7900 // MIs[0] rs1 7901 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7902 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7903 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7904 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_release>> => (AMOMAX_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7905 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_RL, 7906 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7907 // GIR_Coverage, 960, 7908 GIR_Done, 7909 // Label 538: @17917 7910 GIM_Try, /*On fail goto*//*Label 539*/ 17951, // Rule ID 963 // 7911 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7912 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7913 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 7914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7915 // MIs[0] rs1 7916 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7917 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7918 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7919 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_acq_rel>> => (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7920 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL, 7921 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7922 // GIR_Coverage, 963, 7923 GIR_Done, 7924 // Label 539: @17951 7925 GIM_Try, /*On fail goto*//*Label 540*/ 17985, // Rule ID 966 // 7926 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 7927 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 7928 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 7929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7930 // MIs[0] rs1 7931 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 7932 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7933 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7934 // (atomic_load_max:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_max_64>><<P:Predicate_atomic_load_max_64_seq_cst>> => (AMOMAX_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 7935 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAX_D_AQ_RL, 7936 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7937 // GIR_Coverage, 966, 7938 GIR_Done, 7939 // Label 540: @17985 7940 GIM_Reject, 7941 // Label 530: @17986 7942 GIM_Reject, 7943 // Label 508: @17987 7944 GIM_Reject, 7945 // Label 23: @17988 7946 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 543*/ 19032, 7947 /*GILLT_s32*//*Label 541*/ 17996, 7948 /*GILLT_s64*//*Label 542*/ 18684, 7949 // Label 541: @17996 7950 GIM_Try, /*On fail goto*//*Label 544*/ 18683, 7951 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 7952 GIM_Try, /*On fail goto*//*Label 545*/ 18036, // Rule ID 740 // 7953 GIM_CheckFeatures, GIFBS_HasStdExtA, 7954 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7955 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7957 // MIs[0] rs1 7958 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7960 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7961 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7962 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W, 7963 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7964 // GIR_Coverage, 740, 7965 GIR_Done, 7966 // Label 545: @18036 7967 GIM_Try, /*On fail goto*//*Label 546*/ 18070, // Rule ID 742 // 7968 GIM_CheckFeatures, GIFBS_HasStdExtA, 7969 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7970 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 7971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7972 // MIs[0] rs1 7973 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7974 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7975 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7976 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> => (AMOMIN_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7977 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W, 7978 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7979 // GIR_Coverage, 742, 7980 GIR_Done, 7981 // Label 546: @18070 7982 GIM_Try, /*On fail goto*//*Label 547*/ 18104, // Rule ID 743 // 7983 GIM_CheckFeatures, GIFBS_HasStdExtA, 7984 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 7985 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 7986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 7987 // MIs[0] rs1 7988 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 7989 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 7990 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 7991 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> => (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 7992 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ, 7993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 7994 // GIR_Coverage, 743, 7995 GIR_Done, 7996 // Label 547: @18104 7997 GIM_Try, /*On fail goto*//*Label 548*/ 18138, // Rule ID 745 // 7998 GIM_CheckFeatures, GIFBS_HasStdExtA, 7999 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8000 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8002 // MIs[0] rs1 8003 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8004 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8005 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8006 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> => (AMOMIN_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8007 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ, 8008 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8009 // GIR_Coverage, 745, 8010 GIR_Done, 8011 // Label 548: @18138 8012 GIM_Try, /*On fail goto*//*Label 549*/ 18172, // Rule ID 746 // 8013 GIM_CheckFeatures, GIFBS_HasStdExtA, 8014 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8015 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8017 // MIs[0] rs1 8018 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8021 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> => (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8022 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_RL, 8023 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8024 // GIR_Coverage, 746, 8025 GIR_Done, 8026 // Label 549: @18172 8027 GIM_Try, /*On fail goto*//*Label 550*/ 18206, // Rule ID 748 // 8028 GIM_CheckFeatures, GIFBS_HasStdExtA, 8029 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8030 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8032 // MIs[0] rs1 8033 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8034 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8035 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8036 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> => (AMOMIN_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8037 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_RL, 8038 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8039 // GIR_Coverage, 748, 8040 GIR_Done, 8041 // Label 550: @18206 8042 GIM_Try, /*On fail goto*//*Label 551*/ 18240, // Rule ID 749 // 8043 GIM_CheckFeatures, GIFBS_HasStdExtA, 8044 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8045 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8047 // MIs[0] rs1 8048 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8049 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8050 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8051 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8052 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL, 8053 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8054 // GIR_Coverage, 749, 8055 GIR_Done, 8056 // Label 551: @18240 8057 GIM_Try, /*On fail goto*//*Label 552*/ 18274, // Rule ID 751 // 8058 GIM_CheckFeatures, GIFBS_HasStdExtA, 8059 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8060 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8062 // MIs[0] rs1 8063 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8064 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8065 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8066 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8067 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL, 8068 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8069 // GIR_Coverage, 751, 8070 GIR_Done, 8071 // Label 552: @18274 8072 GIM_Try, /*On fail goto*//*Label 553*/ 18308, // Rule ID 752 // 8073 GIM_CheckFeatures, GIFBS_HasStdExtA, 8074 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8075 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8077 // MIs[0] rs1 8078 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8079 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8080 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8081 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8082 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL, 8083 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8084 // GIR_Coverage, 752, 8085 GIR_Done, 8086 // Label 553: @18308 8087 GIM_Try, /*On fail goto*//*Label 554*/ 18342, // Rule ID 754 // 8088 GIM_CheckFeatures, GIFBS_HasStdExtA, 8089 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8090 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8092 // MIs[0] rs1 8093 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8094 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8095 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8096 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8097 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL, 8098 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8099 // GIR_Coverage, 754, 8100 GIR_Done, 8101 // Label 554: @18342 8102 GIM_Try, /*On fail goto*//*Label 555*/ 18376, // Rule ID 968 // 8103 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8104 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8105 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8107 // MIs[0] rs1 8108 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8109 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8110 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8111 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> => (AMOMIN_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8112 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D, 8113 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8114 // GIR_Coverage, 968, 8115 GIR_Done, 8116 // Label 555: @18376 8117 GIM_Try, /*On fail goto*//*Label 556*/ 18410, // Rule ID 970 // 8118 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8119 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8120 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8122 // MIs[0] rs1 8123 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8124 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8125 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8126 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> => (AMOMIN_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8127 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D, 8128 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8129 // GIR_Coverage, 970, 8130 GIR_Done, 8131 // Label 556: @18410 8132 GIM_Try, /*On fail goto*//*Label 557*/ 18444, // Rule ID 971 // 8133 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8134 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8135 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8137 // MIs[0] rs1 8138 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8139 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8140 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8141 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> => (AMOMIN_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8142 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ, 8143 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8144 // GIR_Coverage, 971, 8145 GIR_Done, 8146 // Label 557: @18444 8147 GIM_Try, /*On fail goto*//*Label 558*/ 18478, // Rule ID 973 // 8148 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8149 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8150 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8152 // MIs[0] rs1 8153 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8154 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8155 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8156 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> => (AMOMIN_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8157 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ, 8158 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8159 // GIR_Coverage, 973, 8160 GIR_Done, 8161 // Label 558: @18478 8162 GIM_Try, /*On fail goto*//*Label 559*/ 18512, // Rule ID 974 // 8163 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8164 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8165 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8167 // MIs[0] rs1 8168 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8171 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> => (AMOMIN_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8172 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_RL, 8173 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8174 // GIR_Coverage, 974, 8175 GIR_Done, 8176 // Label 559: @18512 8177 GIM_Try, /*On fail goto*//*Label 560*/ 18546, // Rule ID 976 // 8178 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8179 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8180 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8182 // MIs[0] rs1 8183 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8184 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8185 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8186 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> => (AMOMIN_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8187 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_RL, 8188 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8189 // GIR_Coverage, 976, 8190 GIR_Done, 8191 // Label 560: @18546 8192 GIM_Try, /*On fail goto*//*Label 561*/ 18580, // Rule ID 977 // 8193 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8194 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8195 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8196 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8197 // MIs[0] rs1 8198 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8199 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8200 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8201 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> => (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8202 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL, 8203 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8204 // GIR_Coverage, 977, 8205 GIR_Done, 8206 // Label 561: @18580 8207 GIM_Try, /*On fail goto*//*Label 562*/ 18614, // Rule ID 979 // 8208 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8209 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8210 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8211 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8212 // MIs[0] rs1 8213 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8214 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8215 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8216 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> => (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8217 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL, 8218 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8219 // GIR_Coverage, 979, 8220 GIR_Done, 8221 // Label 562: @18614 8222 GIM_Try, /*On fail goto*//*Label 563*/ 18648, // Rule ID 980 // 8223 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8224 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8225 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8227 // MIs[0] rs1 8228 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8229 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8230 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8231 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> => (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8232 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL, 8233 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8234 // GIR_Coverage, 980, 8235 GIR_Done, 8236 // Label 563: @18648 8237 GIM_Try, /*On fail goto*//*Label 564*/ 18682, // Rule ID 982 // 8238 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8239 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8240 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8241 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8242 // MIs[0] rs1 8243 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8244 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8245 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8246 // (atomic_load_min:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> => (AMOMIN_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8247 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL, 8248 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8249 // GIR_Coverage, 982, 8250 GIR_Done, 8251 // Label 564: @18682 8252 GIM_Reject, 8253 // Label 544: @18683 8254 GIM_Reject, 8255 // Label 542: @18684 8256 GIM_Try, /*On fail goto*//*Label 565*/ 19031, 8257 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 8258 GIM_Try, /*On fail goto*//*Label 566*/ 18724, // Rule ID 741 // 8259 GIM_CheckFeatures, GIFBS_HasStdExtA, 8260 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8261 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8263 // MIs[0] rs1 8264 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8266 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8267 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_monotonic>> => (AMOMIN_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8268 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W, 8269 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8270 // GIR_Coverage, 741, 8271 GIR_Done, 8272 // Label 566: @18724 8273 GIM_Try, /*On fail goto*//*Label 567*/ 18758, // Rule ID 744 // 8274 GIM_CheckFeatures, GIFBS_HasStdExtA, 8275 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8276 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8278 // MIs[0] rs1 8279 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8280 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8282 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acquire>> => (AMOMIN_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8283 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ, 8284 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8285 // GIR_Coverage, 744, 8286 GIR_Done, 8287 // Label 567: @18758 8288 GIM_Try, /*On fail goto*//*Label 568*/ 18792, // Rule ID 747 // 8289 GIM_CheckFeatures, GIFBS_HasStdExtA, 8290 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8291 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8293 // MIs[0] rs1 8294 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8295 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8296 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8297 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_release>> => (AMOMIN_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8298 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_RL, 8299 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8300 // GIR_Coverage, 747, 8301 GIR_Done, 8302 // Label 568: @18792 8303 GIM_Try, /*On fail goto*//*Label 569*/ 18826, // Rule ID 750 // 8304 GIM_CheckFeatures, GIFBS_HasStdExtA, 8305 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8306 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8308 // MIs[0] rs1 8309 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8310 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8311 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8312 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_acq_rel>> => (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8313 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL, 8314 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8315 // GIR_Coverage, 750, 8316 GIR_Done, 8317 // Label 569: @18826 8318 GIM_Try, /*On fail goto*//*Label 570*/ 18860, // Rule ID 753 // 8319 GIM_CheckFeatures, GIFBS_HasStdExtA, 8320 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8321 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8323 // MIs[0] rs1 8324 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8327 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_32>><<P:Predicate_atomic_load_min_32_seq_cst>> => (AMOMIN_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8328 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_W_AQ_RL, 8329 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8330 // GIR_Coverage, 753, 8331 GIR_Done, 8332 // Label 570: @18860 8333 GIM_Try, /*On fail goto*//*Label 571*/ 18894, // Rule ID 969 // 8334 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8335 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8336 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8338 // MIs[0] rs1 8339 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8342 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_monotonic>> => (AMOMIN_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8343 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D, 8344 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8345 // GIR_Coverage, 969, 8346 GIR_Done, 8347 // Label 571: @18894 8348 GIM_Try, /*On fail goto*//*Label 572*/ 18928, // Rule ID 972 // 8349 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8350 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8351 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8352 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8353 // MIs[0] rs1 8354 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8357 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acquire>> => (AMOMIN_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8358 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ, 8359 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8360 // GIR_Coverage, 972, 8361 GIR_Done, 8362 // Label 572: @18928 8363 GIM_Try, /*On fail goto*//*Label 573*/ 18962, // Rule ID 975 // 8364 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8365 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8366 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8367 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8368 // MIs[0] rs1 8369 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8372 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_release>> => (AMOMIN_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8373 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_RL, 8374 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8375 // GIR_Coverage, 975, 8376 GIR_Done, 8377 // Label 573: @18962 8378 GIM_Try, /*On fail goto*//*Label 574*/ 18996, // Rule ID 978 // 8379 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8380 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8381 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8382 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8383 // MIs[0] rs1 8384 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8387 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_acq_rel>> => (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8388 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL, 8389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8390 // GIR_Coverage, 978, 8391 GIR_Done, 8392 // Label 574: @18996 8393 GIM_Try, /*On fail goto*//*Label 575*/ 19030, // Rule ID 981 // 8394 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8395 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8396 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8398 // MIs[0] rs1 8399 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8402 // (atomic_load_min:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_min_64>><<P:Predicate_atomic_load_min_64_seq_cst>> => (AMOMIN_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8403 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMIN_D_AQ_RL, 8404 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8405 // GIR_Coverage, 981, 8406 GIR_Done, 8407 // Label 575: @19030 8408 GIM_Reject, 8409 // Label 565: @19031 8410 GIM_Reject, 8411 // Label 543: @19032 8412 GIM_Reject, 8413 // Label 24: @19033 8414 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 578*/ 20077, 8415 /*GILLT_s32*//*Label 576*/ 19041, 8416 /*GILLT_s64*//*Label 577*/ 19729, 8417 // Label 576: @19041 8418 GIM_Try, /*On fail goto*//*Label 579*/ 19728, 8419 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8420 GIM_Try, /*On fail goto*//*Label 580*/ 19081, // Rule ID 755 // 8421 GIM_CheckFeatures, GIFBS_HasStdExtA, 8422 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8423 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8424 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8425 // MIs[0] rs1 8426 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8429 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8430 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W, 8431 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8432 // GIR_Coverage, 755, 8433 GIR_Done, 8434 // Label 580: @19081 8435 GIM_Try, /*On fail goto*//*Label 581*/ 19115, // Rule ID 757 // 8436 GIM_CheckFeatures, GIFBS_HasStdExtA, 8437 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8438 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8439 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8440 // MIs[0] rs1 8441 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8444 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> => (AMOMAXU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8445 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W, 8446 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8447 // GIR_Coverage, 757, 8448 GIR_Done, 8449 // Label 581: @19115 8450 GIM_Try, /*On fail goto*//*Label 582*/ 19149, // Rule ID 758 // 8451 GIM_CheckFeatures, GIFBS_HasStdExtA, 8452 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8453 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8455 // MIs[0] rs1 8456 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8457 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8458 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8459 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> => (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8460 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ, 8461 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8462 // GIR_Coverage, 758, 8463 GIR_Done, 8464 // Label 582: @19149 8465 GIM_Try, /*On fail goto*//*Label 583*/ 19183, // Rule ID 760 // 8466 GIM_CheckFeatures, GIFBS_HasStdExtA, 8467 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8468 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8470 // MIs[0] rs1 8471 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8472 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8473 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8474 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> => (AMOMAXU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8475 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ, 8476 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8477 // GIR_Coverage, 760, 8478 GIR_Done, 8479 // Label 583: @19183 8480 GIM_Try, /*On fail goto*//*Label 584*/ 19217, // Rule ID 761 // 8481 GIM_CheckFeatures, GIFBS_HasStdExtA, 8482 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8483 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8485 // MIs[0] rs1 8486 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8487 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8489 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> => (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8490 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_RL, 8491 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8492 // GIR_Coverage, 761, 8493 GIR_Done, 8494 // Label 584: @19217 8495 GIM_Try, /*On fail goto*//*Label 585*/ 19251, // Rule ID 763 // 8496 GIM_CheckFeatures, GIFBS_HasStdExtA, 8497 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8498 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8500 // MIs[0] rs1 8501 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8502 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8503 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8504 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> => (AMOMAXU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8505 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_RL, 8506 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8507 // GIR_Coverage, 763, 8508 GIR_Done, 8509 // Label 585: @19251 8510 GIM_Try, /*On fail goto*//*Label 586*/ 19285, // Rule ID 764 // 8511 GIM_CheckFeatures, GIFBS_HasStdExtA, 8512 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8513 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8514 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8515 // MIs[0] rs1 8516 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8518 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8519 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8520 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL, 8521 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8522 // GIR_Coverage, 764, 8523 GIR_Done, 8524 // Label 586: @19285 8525 GIM_Try, /*On fail goto*//*Label 587*/ 19319, // Rule ID 766 // 8526 GIM_CheckFeatures, GIFBS_HasStdExtA, 8527 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8528 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8529 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8530 // MIs[0] rs1 8531 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8532 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8533 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8534 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8535 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL, 8536 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8537 // GIR_Coverage, 766, 8538 GIR_Done, 8539 // Label 587: @19319 8540 GIM_Try, /*On fail goto*//*Label 588*/ 19353, // Rule ID 767 // 8541 GIM_CheckFeatures, GIFBS_HasStdExtA, 8542 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8543 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8544 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8545 // MIs[0] rs1 8546 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8547 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8548 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8549 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8550 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL, 8551 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8552 // GIR_Coverage, 767, 8553 GIR_Done, 8554 // Label 588: @19353 8555 GIM_Try, /*On fail goto*//*Label 589*/ 19387, // Rule ID 769 // 8556 GIM_CheckFeatures, GIFBS_HasStdExtA, 8557 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8558 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8559 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8560 // MIs[0] rs1 8561 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8564 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8565 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL, 8566 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8567 // GIR_Coverage, 769, 8568 GIR_Done, 8569 // Label 589: @19387 8570 GIM_Try, /*On fail goto*//*Label 590*/ 19421, // Rule ID 983 // 8571 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8572 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8573 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8575 // MIs[0] rs1 8576 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8577 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8578 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8579 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> => (AMOMAXU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8580 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D, 8581 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8582 // GIR_Coverage, 983, 8583 GIR_Done, 8584 // Label 590: @19421 8585 GIM_Try, /*On fail goto*//*Label 591*/ 19455, // Rule ID 985 // 8586 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8587 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8588 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8589 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8590 // MIs[0] rs1 8591 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8592 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8594 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> => (AMOMAXU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8595 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D, 8596 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8597 // GIR_Coverage, 985, 8598 GIR_Done, 8599 // Label 591: @19455 8600 GIM_Try, /*On fail goto*//*Label 592*/ 19489, // Rule ID 986 // 8601 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8602 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8603 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8604 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8605 // MIs[0] rs1 8606 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8607 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8608 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8609 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> => (AMOMAXU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8610 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ, 8611 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8612 // GIR_Coverage, 986, 8613 GIR_Done, 8614 // Label 592: @19489 8615 GIM_Try, /*On fail goto*//*Label 593*/ 19523, // Rule ID 988 // 8616 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8617 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8618 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8620 // MIs[0] rs1 8621 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8622 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8623 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8624 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> => (AMOMAXU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8625 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ, 8626 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8627 // GIR_Coverage, 988, 8628 GIR_Done, 8629 // Label 593: @19523 8630 GIM_Try, /*On fail goto*//*Label 594*/ 19557, // Rule ID 989 // 8631 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8632 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8633 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8635 // MIs[0] rs1 8636 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8637 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8638 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8639 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> => (AMOMAXU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8640 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_RL, 8641 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8642 // GIR_Coverage, 989, 8643 GIR_Done, 8644 // Label 594: @19557 8645 GIM_Try, /*On fail goto*//*Label 595*/ 19591, // Rule ID 991 // 8646 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8647 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8648 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8649 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8650 // MIs[0] rs1 8651 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8652 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8653 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8654 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> => (AMOMAXU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8655 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_RL, 8656 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8657 // GIR_Coverage, 991, 8658 GIR_Done, 8659 // Label 595: @19591 8660 GIM_Try, /*On fail goto*//*Label 596*/ 19625, // Rule ID 992 // 8661 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8662 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8663 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8665 // MIs[0] rs1 8666 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8667 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8668 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8669 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> => (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8670 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL, 8671 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8672 // GIR_Coverage, 992, 8673 GIR_Done, 8674 // Label 596: @19625 8675 GIM_Try, /*On fail goto*//*Label 597*/ 19659, // Rule ID 994 // 8676 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8677 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8678 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8680 // MIs[0] rs1 8681 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8682 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8683 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8684 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> => (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8685 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL, 8686 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8687 // GIR_Coverage, 994, 8688 GIR_Done, 8689 // Label 597: @19659 8690 GIM_Try, /*On fail goto*//*Label 598*/ 19693, // Rule ID 995 // 8691 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8692 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8693 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8694 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8695 // MIs[0] rs1 8696 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8697 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8699 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> => (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8700 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL, 8701 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8702 // GIR_Coverage, 995, 8703 GIR_Done, 8704 // Label 598: @19693 8705 GIM_Try, /*On fail goto*//*Label 599*/ 19727, // Rule ID 997 // 8706 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8707 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8708 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8709 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8710 // MIs[0] rs1 8711 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8712 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8713 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8714 // (atomic_load_umax:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> => (AMOMAXU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8715 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL, 8716 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8717 // GIR_Coverage, 997, 8718 GIR_Done, 8719 // Label 599: @19727 8720 GIM_Reject, 8721 // Label 579: @19728 8722 GIM_Reject, 8723 // Label 577: @19729 8724 GIM_Try, /*On fail goto*//*Label 600*/ 20076, 8725 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 8726 GIM_Try, /*On fail goto*//*Label 601*/ 19769, // Rule ID 756 // 8727 GIM_CheckFeatures, GIFBS_HasStdExtA, 8728 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8729 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8730 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8731 // MIs[0] rs1 8732 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8733 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8734 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8735 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_monotonic>> => (AMOMAXU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8736 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W, 8737 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8738 // GIR_Coverage, 756, 8739 GIR_Done, 8740 // Label 601: @19769 8741 GIM_Try, /*On fail goto*//*Label 602*/ 19803, // Rule ID 759 // 8742 GIM_CheckFeatures, GIFBS_HasStdExtA, 8743 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8744 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8745 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8746 // MIs[0] rs1 8747 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8748 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8749 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8750 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acquire>> => (AMOMAXU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8751 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ, 8752 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8753 // GIR_Coverage, 759, 8754 GIR_Done, 8755 // Label 602: @19803 8756 GIM_Try, /*On fail goto*//*Label 603*/ 19837, // Rule ID 762 // 8757 GIM_CheckFeatures, GIFBS_HasStdExtA, 8758 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8759 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8760 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8761 // MIs[0] rs1 8762 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8763 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8764 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8765 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_release>> => (AMOMAXU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8766 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_RL, 8767 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8768 // GIR_Coverage, 762, 8769 GIR_Done, 8770 // Label 603: @19837 8771 GIM_Try, /*On fail goto*//*Label 604*/ 19871, // Rule ID 765 // 8772 GIM_CheckFeatures, GIFBS_HasStdExtA, 8773 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8774 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8776 // MIs[0] rs1 8777 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8779 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8780 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_acq_rel>> => (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8781 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL, 8782 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8783 // GIR_Coverage, 765, 8784 GIR_Done, 8785 // Label 604: @19871 8786 GIM_Try, /*On fail goto*//*Label 605*/ 19905, // Rule ID 768 // 8787 GIM_CheckFeatures, GIFBS_HasStdExtA, 8788 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8789 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8790 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8791 // MIs[0] rs1 8792 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8793 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8794 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8795 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_32>><<P:Predicate_atomic_load_umax_32_seq_cst>> => (AMOMAXU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8796 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_W_AQ_RL, 8797 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8798 // GIR_Coverage, 768, 8799 GIR_Done, 8800 // Label 605: @19905 8801 GIM_Try, /*On fail goto*//*Label 606*/ 19939, // Rule ID 984 // 8802 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8803 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8804 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8805 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8806 // MIs[0] rs1 8807 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8808 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8809 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8810 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_monotonic>> => (AMOMAXU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8811 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D, 8812 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8813 // GIR_Coverage, 984, 8814 GIR_Done, 8815 // Label 606: @19939 8816 GIM_Try, /*On fail goto*//*Label 607*/ 19973, // Rule ID 987 // 8817 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8818 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8819 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8820 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8821 // MIs[0] rs1 8822 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8823 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8825 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acquire>> => (AMOMAXU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8826 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ, 8827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8828 // GIR_Coverage, 987, 8829 GIR_Done, 8830 // Label 607: @19973 8831 GIM_Try, /*On fail goto*//*Label 608*/ 20007, // Rule ID 990 // 8832 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8833 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8834 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8835 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8836 // MIs[0] rs1 8837 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8838 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8839 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8840 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_release>> => (AMOMAXU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8841 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_RL, 8842 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8843 // GIR_Coverage, 990, 8844 GIR_Done, 8845 // Label 608: @20007 8846 GIM_Try, /*On fail goto*//*Label 609*/ 20041, // Rule ID 993 // 8847 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8848 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8849 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8851 // MIs[0] rs1 8852 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8853 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8854 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8855 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_acq_rel>> => (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8856 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL, 8857 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8858 // GIR_Coverage, 993, 8859 GIR_Done, 8860 // Label 609: @20041 8861 GIM_Try, /*On fail goto*//*Label 610*/ 20075, // Rule ID 996 // 8862 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 8863 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 8864 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 8865 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8866 // MIs[0] rs1 8867 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 8868 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8869 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8870 // (atomic_load_umax:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umax_64>><<P:Predicate_atomic_load_umax_64_seq_cst>> => (AMOMAXU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 8871 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMAXU_D_AQ_RL, 8872 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8873 // GIR_Coverage, 996, 8874 GIR_Done, 8875 // Label 610: @20075 8876 GIM_Reject, 8877 // Label 600: @20076 8878 GIM_Reject, 8879 // Label 578: @20077 8880 GIM_Reject, 8881 // Label 25: @20078 8882 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 613*/ 21122, 8883 /*GILLT_s32*//*Label 611*/ 20086, 8884 /*GILLT_s64*//*Label 612*/ 20774, 8885 // Label 611: @20086 8886 GIM_Try, /*On fail goto*//*Label 614*/ 20773, 8887 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 8888 GIM_Try, /*On fail goto*//*Label 615*/ 20126, // Rule ID 770 // 8889 GIM_CheckFeatures, GIFBS_HasStdExtA, 8890 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8891 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8892 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8893 // MIs[0] rs1 8894 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8895 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8896 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8897 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8898 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W, 8899 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8900 // GIR_Coverage, 770, 8901 GIR_Done, 8902 // Label 615: @20126 8903 GIM_Try, /*On fail goto*//*Label 616*/ 20160, // Rule ID 772 // 8904 GIM_CheckFeatures, GIFBS_HasStdExtA, 8905 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8906 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 8907 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8908 // MIs[0] rs1 8909 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8911 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8912 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> => (AMOMINU_W:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8913 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W, 8914 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8915 // GIR_Coverage, 772, 8916 GIR_Done, 8917 // Label 616: @20160 8918 GIM_Try, /*On fail goto*//*Label 617*/ 20194, // Rule ID 773 // 8919 GIM_CheckFeatures, GIFBS_HasStdExtA, 8920 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8921 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8922 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8923 // MIs[0] rs1 8924 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8925 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8926 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8927 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> => (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8928 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ, 8929 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8930 // GIR_Coverage, 773, 8931 GIR_Done, 8932 // Label 617: @20194 8933 GIM_Try, /*On fail goto*//*Label 618*/ 20228, // Rule ID 775 // 8934 GIM_CheckFeatures, GIFBS_HasStdExtA, 8935 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8936 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 8937 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8938 // MIs[0] rs1 8939 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8940 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8941 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8942 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> => (AMOMINU_W_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8943 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ, 8944 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8945 // GIR_Coverage, 775, 8946 GIR_Done, 8947 // Label 618: @20228 8948 GIM_Try, /*On fail goto*//*Label 619*/ 20262, // Rule ID 776 // 8949 GIM_CheckFeatures, GIFBS_HasStdExtA, 8950 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8951 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8952 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8953 // MIs[0] rs1 8954 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8955 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8957 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> => (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8958 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_RL, 8959 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8960 // GIR_Coverage, 776, 8961 GIR_Done, 8962 // Label 619: @20262 8963 GIM_Try, /*On fail goto*//*Label 620*/ 20296, // Rule ID 778 // 8964 GIM_CheckFeatures, GIFBS_HasStdExtA, 8965 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8966 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 8967 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8968 // MIs[0] rs1 8969 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8970 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8972 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> => (AMOMINU_W_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8973 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_RL, 8974 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8975 // GIR_Coverage, 778, 8976 GIR_Done, 8977 // Label 620: @20296 8978 GIM_Try, /*On fail goto*//*Label 621*/ 20330, // Rule ID 779 // 8979 GIM_CheckFeatures, GIFBS_HasStdExtA, 8980 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8981 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8982 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8983 // MIs[0] rs1 8984 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 8985 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 8986 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 8987 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 8988 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL, 8989 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 8990 // GIR_Coverage, 779, 8991 GIR_Done, 8992 // Label 621: @20330 8993 GIM_Try, /*On fail goto*//*Label 622*/ 20364, // Rule ID 781 // 8994 GIM_CheckFeatures, GIFBS_HasStdExtA, 8995 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 8996 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 8997 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 8998 // MIs[0] rs1 8999 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9001 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9002 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9003 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL, 9004 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9005 // GIR_Coverage, 781, 9006 GIR_Done, 9007 // Label 622: @20364 9008 GIM_Try, /*On fail goto*//*Label 623*/ 20398, // Rule ID 782 // 9009 GIM_CheckFeatures, GIFBS_HasStdExtA, 9010 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 9011 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 9012 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9013 // MIs[0] rs1 9014 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9016 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9017 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9018 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL, 9019 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9020 // GIR_Coverage, 782, 9021 GIR_Done, 9022 // Label 623: @20398 9023 GIM_Try, /*On fail goto*//*Label 624*/ 20432, // Rule ID 784 // 9024 GIM_CheckFeatures, GIFBS_HasStdExtA, 9025 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 9026 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 9027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9028 // MIs[0] rs1 9029 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9030 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9031 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9032 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9033 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL, 9034 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9035 // GIR_Coverage, 784, 9036 GIR_Done, 9037 // Label 624: @20432 9038 GIM_Try, /*On fail goto*//*Label 625*/ 20466, // Rule ID 998 // 9039 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9040 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9041 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 9042 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9043 // MIs[0] rs1 9044 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9045 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9046 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9047 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> => (AMOMINU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9048 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D, 9049 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9050 // GIR_Coverage, 998, 9051 GIR_Done, 9052 // Label 625: @20466 9053 GIM_Try, /*On fail goto*//*Label 626*/ 20500, // Rule ID 1000 // 9054 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9055 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9056 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 9057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9058 // MIs[0] rs1 9059 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9060 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9061 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9062 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> => (AMOMINU_D:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9063 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D, 9064 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9065 // GIR_Coverage, 1000, 9066 GIR_Done, 9067 // Label 626: @20500 9068 GIM_Try, /*On fail goto*//*Label 627*/ 20534, // Rule ID 1001 // 9069 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9070 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9071 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 9072 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9073 // MIs[0] rs1 9074 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9077 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> => (AMOMINU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9078 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ, 9079 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9080 // GIR_Coverage, 1001, 9081 GIR_Done, 9082 // Label 627: @20534 9083 GIM_Try, /*On fail goto*//*Label 628*/ 20568, // Rule ID 1003 // 9084 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9085 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9086 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 9087 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9088 // MIs[0] rs1 9089 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9091 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9092 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> => (AMOMINU_D_AQ:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9093 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ, 9094 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9095 // GIR_Coverage, 1003, 9096 GIR_Done, 9097 // Label 628: @20568 9098 GIM_Try, /*On fail goto*//*Label 629*/ 20602, // Rule ID 1004 // 9099 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9100 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9101 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 9102 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9103 // MIs[0] rs1 9104 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9105 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9106 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9107 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> => (AMOMINU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9108 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_RL, 9109 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9110 // GIR_Coverage, 1004, 9111 GIR_Done, 9112 // Label 629: @20602 9113 GIM_Try, /*On fail goto*//*Label 630*/ 20636, // Rule ID 1006 // 9114 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9115 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9116 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 9117 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9118 // MIs[0] rs1 9119 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9120 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9121 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9122 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> => (AMOMINU_D_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9123 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_RL, 9124 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9125 // GIR_Coverage, 1006, 9126 GIR_Done, 9127 // Label 630: @20636 9128 GIM_Try, /*On fail goto*//*Label 631*/ 20670, // Rule ID 1007 // 9129 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9130 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9131 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 9132 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9133 // MIs[0] rs1 9134 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9135 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9136 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9137 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> => (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9138 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL, 9139 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9140 // GIR_Coverage, 1007, 9141 GIR_Done, 9142 // Label 631: @20670 9143 GIM_Try, /*On fail goto*//*Label 632*/ 20704, // Rule ID 1009 // 9144 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9145 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9146 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 9147 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9148 // MIs[0] rs1 9149 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9150 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9151 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9152 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> => (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9153 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL, 9154 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9155 // GIR_Coverage, 1009, 9156 GIR_Done, 9157 // Label 632: @20704 9158 GIM_Try, /*On fail goto*//*Label 633*/ 20738, // Rule ID 1010 // 9159 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9160 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9161 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 9162 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9163 // MIs[0] rs1 9164 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9165 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9166 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9167 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> => (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9168 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL, 9169 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9170 // GIR_Coverage, 1010, 9171 GIR_Done, 9172 // Label 633: @20738 9173 GIM_Try, /*On fail goto*//*Label 634*/ 20772, // Rule ID 1012 // 9174 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9175 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9176 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 9177 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9178 // MIs[0] rs1 9179 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, 9180 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9182 // (atomic_load_umin:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> => (AMOMINU_D_AQ_RL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9183 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL, 9184 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9185 // GIR_Coverage, 1012, 9186 GIR_Done, 9187 // Label 634: @20772 9188 GIM_Reject, 9189 // Label 614: @20773 9190 GIM_Reject, 9191 // Label 612: @20774 9192 GIM_Try, /*On fail goto*//*Label 635*/ 21121, 9193 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 9194 GIM_Try, /*On fail goto*//*Label 636*/ 20814, // Rule ID 771 // 9195 GIM_CheckFeatures, GIFBS_HasStdExtA, 9196 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 9197 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 9198 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9199 // MIs[0] rs1 9200 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9202 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9203 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_monotonic>> => (AMOMINU_W:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9204 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W, 9205 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9206 // GIR_Coverage, 771, 9207 GIR_Done, 9208 // Label 636: @20814 9209 GIM_Try, /*On fail goto*//*Label 637*/ 20848, // Rule ID 774 // 9210 GIM_CheckFeatures, GIFBS_HasStdExtA, 9211 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 9212 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 9213 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9214 // MIs[0] rs1 9215 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9216 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9217 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9218 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acquire>> => (AMOMINU_W_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9219 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ, 9220 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9221 // GIR_Coverage, 774, 9222 GIR_Done, 9223 // Label 637: @20848 9224 GIM_Try, /*On fail goto*//*Label 638*/ 20882, // Rule ID 777 // 9225 GIM_CheckFeatures, GIFBS_HasStdExtA, 9226 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 9227 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 9228 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9229 // MIs[0] rs1 9230 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9231 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9232 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9233 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_release>> => (AMOMINU_W_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9234 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_RL, 9235 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9236 // GIR_Coverage, 777, 9237 GIR_Done, 9238 // Label 638: @20882 9239 GIM_Try, /*On fail goto*//*Label 639*/ 20916, // Rule ID 780 // 9240 GIM_CheckFeatures, GIFBS_HasStdExtA, 9241 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 9242 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 9243 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9244 // MIs[0] rs1 9245 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9246 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9248 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_acq_rel>> => (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9249 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL, 9250 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9251 // GIR_Coverage, 780, 9252 GIR_Done, 9253 // Label 639: @20916 9254 GIM_Try, /*On fail goto*//*Label 640*/ 20950, // Rule ID 783 // 9255 GIM_CheckFeatures, GIFBS_HasStdExtA, 9256 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4, 9257 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 9258 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9259 // MIs[0] rs1 9260 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9261 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9263 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_32>><<P:Predicate_atomic_load_umin_32_seq_cst>> => (AMOMINU_W_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9264 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_W_AQ_RL, 9265 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9266 // GIR_Coverage, 783, 9267 GIR_Done, 9268 // Label 640: @20950 9269 GIM_Try, /*On fail goto*//*Label 641*/ 20984, // Rule ID 999 // 9270 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9271 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9272 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Monotonic, 9273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9274 // MIs[0] rs1 9275 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9276 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9277 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9278 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_monotonic>> => (AMOMINU_D:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9279 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D, 9280 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9281 // GIR_Coverage, 999, 9282 GIR_Done, 9283 // Label 641: @20984 9284 GIM_Try, /*On fail goto*//*Label 642*/ 21018, // Rule ID 1002 // 9285 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9286 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9287 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Acquire, 9288 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9289 // MIs[0] rs1 9290 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9291 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9292 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9293 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acquire>> => (AMOMINU_D_AQ:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9294 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ, 9295 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9296 // GIR_Coverage, 1002, 9297 GIR_Done, 9298 // Label 642: @21018 9299 GIM_Try, /*On fail goto*//*Label 643*/ 21052, // Rule ID 1005 // 9300 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9301 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9302 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::Release, 9303 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9304 // MIs[0] rs1 9305 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9307 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9308 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_release>> => (AMOMINU_D_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9309 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_RL, 9310 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9311 // GIR_Coverage, 1005, 9312 GIR_Done, 9313 // Label 643: @21052 9314 GIM_Try, /*On fail goto*//*Label 644*/ 21086, // Rule ID 1008 // 9315 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9316 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9317 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::AcquireRelease, 9318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9319 // MIs[0] rs1 9320 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9321 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9322 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9323 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_acq_rel>> => (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9324 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL, 9325 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9326 // GIR_Coverage, 1008, 9327 GIR_Done, 9328 // Label 644: @21086 9329 GIM_Try, /*On fail goto*//*Label 645*/ 21120, // Rule ID 1011 // 9330 GIM_CheckFeatures, GIFBS_HasStdExtA_IsRV64, 9331 GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/8, 9332 GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(int64_t)AtomicOrdering::SequentiallyConsistent, 9333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9334 // MIs[0] rs1 9335 GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, 9336 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9337 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9338 // (atomic_load_umin:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)<<P:Predicate_atomic_load_umin_64>><<P:Predicate_atomic_load_umin_64_seq_cst>> => (AMOMINU_D_AQ_RL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9339 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::AMOMINU_D_AQ_RL, 9340 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9341 // GIR_Coverage, 1011, 9342 GIR_Done, 9343 // Label 645: @21120 9344 GIM_Reject, 9345 // Label 635: @21121 9346 GIM_Reject, 9347 // Label 613: @21122 9348 GIM_Reject, 9349 // Label 26: @21123 9350 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 648*/ 21391, 9351 /*GILLT_s32*//*Label 646*/ 21131, 9352 /*GILLT_s64*//*Label 647*/ 21304, 9353 // Label 646: @21131 9354 GIM_Try, /*On fail goto*//*Label 649*/ 21154, // Rule ID 348 // 9355 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4, 9356 // MIs[0] Operand 1 9357 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9358 // (atomic_fence 4:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 2:{ *:[i32] }, 3:{ *:[i32] }) 9359 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE, 9360 GIR_AddImm, /*InsnID*/0, /*Imm*/2, 9361 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9362 GIR_EraseFromParent, /*InsnID*/0, 9363 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9364 // GIR_Coverage, 348, 9365 GIR_Done, 9366 // Label 649: @21154 9367 GIM_Try, /*On fail goto*//*Label 650*/ 21177, // Rule ID 350 // 9368 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4, 9369 // MIs[0] Operand 1 9370 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9371 // (atomic_fence 4:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 2:{ *:[i32] }, 3:{ *:[i32] }) 9372 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE, 9373 GIR_AddImm, /*InsnID*/0, /*Imm*/2, 9374 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9375 GIR_EraseFromParent, /*InsnID*/0, 9376 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9377 // GIR_Coverage, 350, 9378 GIR_Done, 9379 // Label 650: @21177 9380 GIM_Try, /*On fail goto*//*Label 651*/ 21200, // Rule ID 351 // 9381 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 5, 9382 // MIs[0] Operand 1 9383 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9384 // (atomic_fence 5:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 1:{ *:[i32] }) 9385 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE, 9386 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9387 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 9388 GIR_EraseFromParent, /*InsnID*/0, 9389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9390 // GIR_Coverage, 351, 9391 GIR_Done, 9392 // Label 651: @21200 9393 GIM_Try, /*On fail goto*//*Label 652*/ 21223, // Rule ID 353 // 9394 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 5, 9395 // MIs[0] Operand 1 9396 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9397 // (atomic_fence 5:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 1:{ *:[i32] }) 9398 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE, 9399 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9400 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 9401 GIR_EraseFromParent, /*InsnID*/0, 9402 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9403 // GIR_Coverage, 353, 9404 GIR_Done, 9405 // Label 652: @21223 9406 GIM_Try, /*On fail goto*//*Label 653*/ 21240, // Rule ID 354 // 9407 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 6, 9408 // MIs[0] Operand 1 9409 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9410 // (atomic_fence 6:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE_TSO) 9411 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO, 9412 GIR_EraseFromParent, /*InsnID*/0, 9413 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9414 // GIR_Coverage, 354, 9415 GIR_Done, 9416 // Label 653: @21240 9417 GIM_Try, /*On fail goto*//*Label 654*/ 21257, // Rule ID 356 // 9418 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 6, 9419 // MIs[0] Operand 1 9420 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9421 // (atomic_fence 6:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE_TSO) 9422 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO, 9423 GIR_EraseFromParent, /*InsnID*/0, 9424 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9425 // GIR_Coverage, 356, 9426 GIR_Done, 9427 // Label 654: @21257 9428 GIM_Try, /*On fail goto*//*Label 655*/ 21280, // Rule ID 357 // 9429 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7, 9430 // MIs[0] Operand 1 9431 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9432 // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 3:{ *:[i32] }) 9433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE, 9434 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9435 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9436 GIR_EraseFromParent, /*InsnID*/0, 9437 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9438 // GIR_Coverage, 357, 9439 GIR_Done, 9440 // Label 655: @21280 9441 GIM_Try, /*On fail goto*//*Label 656*/ 21303, // Rule ID 359 // 9442 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7, 9443 // MIs[0] Operand 1 9444 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9445 // (atomic_fence 7:{ *:[i32] }, (timm:{ *:[i32] })) => (FENCE 3:{ *:[i32] }, 3:{ *:[i32] }) 9446 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE, 9447 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9448 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9449 GIR_EraseFromParent, /*InsnID*/0, 9450 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9451 // GIR_Coverage, 359, 9452 GIR_Done, 9453 // Label 656: @21303 9454 GIM_Reject, 9455 // Label 647: @21304 9456 GIM_Try, /*On fail goto*//*Label 657*/ 21327, // Rule ID 349 // 9457 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 4, 9458 // MIs[0] Operand 1 9459 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9460 // (atomic_fence 4:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE 2:{ *:[i64] }, 3:{ *:[i64] }) 9461 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE, 9462 GIR_AddImm, /*InsnID*/0, /*Imm*/2, 9463 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9464 GIR_EraseFromParent, /*InsnID*/0, 9465 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9466 // GIR_Coverage, 349, 9467 GIR_Done, 9468 // Label 657: @21327 9469 GIM_Try, /*On fail goto*//*Label 658*/ 21350, // Rule ID 352 // 9470 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 5, 9471 // MIs[0] Operand 1 9472 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9473 // (atomic_fence 5:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE 3:{ *:[i64] }, 1:{ *:[i64] }) 9474 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE, 9475 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9476 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 9477 GIR_EraseFromParent, /*InsnID*/0, 9478 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9479 // GIR_Coverage, 352, 9480 GIR_Done, 9481 // Label 658: @21350 9482 GIM_Try, /*On fail goto*//*Label 659*/ 21367, // Rule ID 355 // 9483 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 6, 9484 // MIs[0] Operand 1 9485 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9486 // (atomic_fence 6:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE_TSO) 9487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE_TSO, 9488 GIR_EraseFromParent, /*InsnID*/0, 9489 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9490 // GIR_Coverage, 355, 9491 GIR_Done, 9492 // Label 659: @21367 9493 GIM_Try, /*On fail goto*//*Label 660*/ 21390, // Rule ID 358 // 9494 GIM_CheckConstantInt, /*MI*/0, /*Op*/0, 7, 9495 // MIs[0] Operand 1 9496 GIM_CheckIsImm, /*MI*/0, /*Op*/1, 9497 // (atomic_fence 7:{ *:[i64] }, (timm:{ *:[i64] })) => (FENCE 3:{ *:[i64] }, 3:{ *:[i64] }) 9498 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FENCE, 9499 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9500 GIR_AddImm, /*InsnID*/0, /*Imm*/3, 9501 GIR_EraseFromParent, /*InsnID*/0, 9502 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9503 // GIR_Coverage, 358, 9504 GIR_Done, 9505 // Label 660: @21390 9506 GIM_Reject, 9507 // Label 648: @21391 9508 GIM_Reject, 9509 // Label 27: @21392 9510 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 663*/ 21482, 9511 /*GILLT_s32*//*Label 661*/ 21400, 9512 /*GILLT_s64*//*Label 662*/ 21453, 9513 // Label 661: @21400 9514 GIM_Try, /*On fail goto*//*Label 664*/ 21452, 9515 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_simm12, 9516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9517 GIM_Try, /*On fail goto*//*Label 665*/ 21430, // Rule ID 23 // 9518 // MIs[0] Operand 1 9519 // No operand predicates 9520 // (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm => (ADDI:{ *:[i32] } X0:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) 9521 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI, 9522 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9523 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 9524 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm 9525 GIR_EraseFromParent, /*InsnID*/0, 9526 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9527 // GIR_Coverage, 23, 9528 GIR_Done, 9529 // Label 665: @21430 9530 GIM_Try, /*On fail goto*//*Label 666*/ 21451, // Rule ID 25 // 9531 // MIs[0] Operand 1 9532 // No operand predicates 9533 // (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm => (ADDI:{ *:[i32] } X0:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm) 9534 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI, 9535 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9536 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 9537 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm 9538 GIR_EraseFromParent, /*InsnID*/0, 9539 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9540 // GIR_Coverage, 25, 9541 GIR_Done, 9542 // Label 666: @21451 9543 GIM_Reject, 9544 // Label 664: @21452 9545 GIM_Reject, 9546 // Label 662: @21453 9547 GIM_Try, /*On fail goto*//*Label 667*/ 21481, // Rule ID 24 // 9548 GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_simm12, 9549 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9550 // MIs[0] Operand 1 9551 // No operand predicates 9552 // (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm => (ADDI:{ *:[i64] } X0:{ *:[i64] }, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm) 9553 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::ADDI, 9554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9555 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 9556 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm 9557 GIR_EraseFromParent, /*InsnID*/0, 9558 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9559 // GIR_Coverage, 24, 9560 GIR_Done, 9561 // Label 667: @21481 9562 GIM_Reject, 9563 // Label 663: @21482 9564 GIM_Reject, 9565 // Label 28: @21483 9566 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 670*/ 21834, 9567 /*GILLT_s32*//*Label 668*/ 21491, 9568 /*GILLT_s64*//*Label 669*/ 21713, 9569 // Label 668: @21491 9570 GIM_Try, /*On fail goto*//*Label 671*/ 21712, 9571 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9572 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9573 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9574 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9575 GIM_Try, /*On fail goto*//*Label 672*/ 21564, // Rule ID 71 // 9576 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9577 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 9578 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 9579 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9580 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9581 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9582 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 9583 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset, 9584 // MIs[2] Operand 1 9585 // No operand predicates 9586 GIM_CheckIsSafeToFold, /*InsnID*/1, 9587 GIM_CheckIsSafeToFold, /*InsnID*/2, 9588 // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9589 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLL, 9590 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9591 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9592 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 9593 GIR_EraseFromParent, /*InsnID*/0, 9594 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9595 // GIR_Coverage, 71, 9596 GIR_Done, 9597 // Label 672: @21564 9598 GIM_Try, /*On fail goto*//*Label 673*/ 21619, // Rule ID 73 // 9599 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9600 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 9601 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 9602 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9603 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9604 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9605 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 9606 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset, 9607 // MIs[2] Operand 1 9608 // No operand predicates 9609 GIM_CheckIsSafeToFold, /*InsnID*/1, 9610 GIM_CheckIsSafeToFold, /*InsnID*/2, 9611 // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9612 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLL, 9613 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9614 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9615 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 9616 GIR_EraseFromParent, /*InsnID*/0, 9617 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9618 // GIR_Coverage, 73, 9619 GIR_Done, 9620 // Label 673: @21619 9621 GIM_Try, /*On fail goto*//*Label 674*/ 21652, // Rule ID 59 // 9622 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9623 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9624 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen, 9625 // MIs[1] Operand 1 9626 // No operand predicates 9627 GIM_CheckIsSafeToFold, /*InsnID*/1, 9628 // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) 9629 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI, 9630 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9631 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9632 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 9633 GIR_EraseFromParent, /*InsnID*/0, 9634 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9635 // GIR_Coverage, 59, 9636 GIR_Done, 9637 // Label 674: @21652 9638 GIM_Try, /*On fail goto*//*Label 675*/ 21685, // Rule ID 61 // 9639 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9640 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9641 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen, 9642 // MIs[1] Operand 1 9643 // No operand predicates 9644 GIM_CheckIsSafeToFold, /*InsnID*/1, 9645 // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SLLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) 9646 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI, 9647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9648 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9649 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 9650 GIR_EraseFromParent, /*InsnID*/0, 9651 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9652 // GIR_Coverage, 61, 9653 GIR_Done, 9654 // Label 675: @21685 9655 GIM_Try, /*On fail goto*//*Label 676*/ 21698, // Rule ID 68 // 9656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9657 // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9658 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SLL, 9659 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9660 // GIR_Coverage, 68, 9661 GIR_Done, 9662 // Label 676: @21698 9663 GIM_Try, /*On fail goto*//*Label 677*/ 21711, // Rule ID 70 // 9664 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9665 // (shl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SLL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9666 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SLL, 9667 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9668 // GIR_Coverage, 70, 9669 GIR_Done, 9670 // Label 677: @21711 9671 GIM_Reject, 9672 // Label 671: @21712 9673 GIM_Reject, 9674 // Label 669: @21713 9675 GIM_Try, /*On fail goto*//*Label 678*/ 21833, 9676 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9677 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 9678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9679 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9680 GIM_Try, /*On fail goto*//*Label 679*/ 21786, // Rule ID 72 // 9681 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9682 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 9683 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 9684 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 9685 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9686 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9687 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 9688 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset, 9689 // MIs[2] Operand 1 9690 // No operand predicates 9691 GIM_CheckIsSafeToFold, /*InsnID*/1, 9692 GIM_CheckIsSafeToFold, /*InsnID*/2, 9693 // (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_immbottomxlenset>>)) => (SLL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9694 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLL, 9695 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9696 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9697 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 9698 GIR_EraseFromParent, /*InsnID*/0, 9699 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9700 // GIR_Coverage, 72, 9701 GIR_Done, 9702 // Label 679: @21786 9703 GIM_Try, /*On fail goto*//*Label 680*/ 21819, // Rule ID 60 // 9704 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9705 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9706 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen, 9707 // MIs[1] Operand 1 9708 // No operand predicates 9709 GIM_CheckIsSafeToFold, /*InsnID*/1, 9710 // (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SLLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) 9711 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLLI, 9712 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9713 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9714 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 9715 GIR_EraseFromParent, /*InsnID*/0, 9716 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9717 // GIR_Coverage, 60, 9718 GIR_Done, 9719 // Label 680: @21819 9720 GIM_Try, /*On fail goto*//*Label 681*/ 21832, // Rule ID 69 // 9721 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9722 // (shl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SLL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9723 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SLL, 9724 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9725 // GIR_Coverage, 69, 9726 GIR_Done, 9727 // Label 681: @21832 9728 GIM_Reject, 9729 // Label 678: @21833 9730 GIM_Reject, 9731 // Label 670: @21834 9732 GIM_Reject, 9733 // Label 29: @21835 9734 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 684*/ 22186, 9735 /*GILLT_s32*//*Label 682*/ 21843, 9736 /*GILLT_s64*//*Label 683*/ 22065, 9737 // Label 682: @21843 9738 GIM_Try, /*On fail goto*//*Label 685*/ 22064, 9739 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9740 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9741 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9742 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9743 GIM_Try, /*On fail goto*//*Label 686*/ 21916, // Rule ID 77 // 9744 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9745 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 9746 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 9747 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9748 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9749 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9750 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 9751 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset, 9752 // MIs[2] Operand 1 9753 // No operand predicates 9754 GIM_CheckIsSafeToFold, /*InsnID*/1, 9755 GIM_CheckIsSafeToFold, /*InsnID*/2, 9756 // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9757 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRL, 9758 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 9761 GIR_EraseFromParent, /*InsnID*/0, 9762 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9763 // GIR_Coverage, 77, 9764 GIR_Done, 9765 // Label 686: @21916 9766 GIM_Try, /*On fail goto*//*Label 687*/ 21971, // Rule ID 79 // 9767 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9768 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 9769 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 9770 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9771 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9772 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9773 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 9774 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset, 9775 // MIs[2] Operand 1 9776 // No operand predicates 9777 GIM_CheckIsSafeToFold, /*InsnID*/1, 9778 GIM_CheckIsSafeToFold, /*InsnID*/2, 9779 // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9780 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRL, 9781 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9782 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9783 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 9784 GIR_EraseFromParent, /*InsnID*/0, 9785 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9786 // GIR_Coverage, 79, 9787 GIR_Done, 9788 // Label 687: @21971 9789 GIM_Try, /*On fail goto*//*Label 688*/ 22004, // Rule ID 62 // 9790 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9791 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9792 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen, 9793 // MIs[1] Operand 1 9794 // No operand predicates 9795 GIM_CheckIsSafeToFold, /*InsnID*/1, 9796 // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) 9797 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI, 9798 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9799 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9800 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 9801 GIR_EraseFromParent, /*InsnID*/0, 9802 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9803 // GIR_Coverage, 62, 9804 GIR_Done, 9805 // Label 688: @22004 9806 GIM_Try, /*On fail goto*//*Label 689*/ 22037, // Rule ID 64 // 9807 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9808 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9809 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen, 9810 // MIs[1] Operand 1 9811 // No operand predicates 9812 GIM_CheckIsSafeToFold, /*InsnID*/1, 9813 // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRLI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) 9814 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI, 9815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9817 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 9818 GIR_EraseFromParent, /*InsnID*/0, 9819 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9820 // GIR_Coverage, 64, 9821 GIR_Done, 9822 // Label 689: @22037 9823 GIM_Try, /*On fail goto*//*Label 690*/ 22050, // Rule ID 74 // 9824 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9825 // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9826 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRL, 9827 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9828 // GIR_Coverage, 74, 9829 GIR_Done, 9830 // Label 690: @22050 9831 GIM_Try, /*On fail goto*//*Label 691*/ 22063, // Rule ID 76 // 9832 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9833 // (srl:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRL:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9834 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRL, 9835 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9836 // GIR_Coverage, 76, 9837 GIR_Done, 9838 // Label 691: @22063 9839 GIM_Reject, 9840 // Label 685: @22064 9841 GIM_Reject, 9842 // Label 683: @22065 9843 GIM_Try, /*On fail goto*//*Label 692*/ 22185, 9844 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 9845 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 9846 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9847 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9848 GIM_Try, /*On fail goto*//*Label 693*/ 22138, // Rule ID 78 // 9849 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9850 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 9851 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 9852 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 9853 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9854 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9855 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 9856 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset, 9857 // MIs[2] Operand 1 9858 // No operand predicates 9859 GIM_CheckIsSafeToFold, /*InsnID*/1, 9860 GIM_CheckIsSafeToFold, /*InsnID*/2, 9861 // (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_immbottomxlenset>>)) => (SRL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9862 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRL, 9863 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9864 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9865 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 9866 GIR_EraseFromParent, /*InsnID*/0, 9867 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9868 // GIR_Coverage, 78, 9869 GIR_Done, 9870 // Label 693: @22138 9871 GIM_Try, /*On fail goto*//*Label 694*/ 22171, // Rule ID 63 // 9872 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9873 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9874 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen, 9875 // MIs[1] Operand 1 9876 // No operand predicates 9877 GIM_CheckIsSafeToFold, /*InsnID*/1, 9878 // (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRLI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) 9879 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRLI, 9880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9882 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 9883 GIR_EraseFromParent, /*InsnID*/0, 9884 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9885 // GIR_Coverage, 63, 9886 GIR_Done, 9887 // Label 694: @22171 9888 GIM_Try, /*On fail goto*//*Label 695*/ 22184, // Rule ID 75 // 9889 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9890 // (srl:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SRL:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 9891 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRL, 9892 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9893 // GIR_Coverage, 75, 9894 GIR_Done, 9895 // Label 695: @22184 9896 GIM_Reject, 9897 // Label 692: @22185 9898 GIM_Reject, 9899 // Label 684: @22186 9900 GIM_Reject, 9901 // Label 30: @22187 9902 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 698*/ 22538, 9903 /*GILLT_s32*//*Label 696*/ 22195, 9904 /*GILLT_s64*//*Label 697*/ 22417, 9905 // Label 696: @22195 9906 GIM_Try, /*On fail goto*//*Label 699*/ 22416, 9907 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 9908 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 9909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 9910 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9911 GIM_Try, /*On fail goto*//*Label 700*/ 22268, // Rule ID 83 // 9912 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9913 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 9914 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 9915 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9916 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9917 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9918 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 9919 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset, 9920 // MIs[2] Operand 1 9921 // No operand predicates 9922 GIM_CheckIsSafeToFold, /*InsnID*/1, 9923 GIM_CheckIsSafeToFold, /*InsnID*/2, 9924 // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9925 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRA, 9926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9927 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9928 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 9929 GIR_EraseFromParent, /*InsnID*/0, 9930 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9931 // GIR_Coverage, 83, 9932 GIR_Done, 9933 // Label 700: @22268 9934 GIM_Try, /*On fail goto*//*Label 701*/ 22323, // Rule ID 85 // 9935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9936 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 9937 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 9938 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, 9939 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 9940 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 9941 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 9942 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset, 9943 // MIs[2] Operand 1 9944 // No operand predicates 9945 GIM_CheckIsSafeToFold, /*InsnID*/1, 9946 GIM_CheckIsSafeToFold, /*InsnID*/2, 9947 // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (and:{ *:[i32] } GPR:{ *:[i32] }:$rs2, (imm:{ *:[i32] })<<P:Predicate_immbottomxlenset>>)) => (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9948 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRA, 9949 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9950 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9951 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 9952 GIR_EraseFromParent, /*InsnID*/0, 9953 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9954 // GIR_Coverage, 85, 9955 GIR_Done, 9956 // Label 701: @22323 9957 GIM_Try, /*On fail goto*//*Label 702*/ 22356, // Rule ID 65 // 9958 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9959 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9960 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen, 9961 // MIs[1] Operand 1 9962 // No operand predicates 9963 GIM_CheckIsSafeToFold, /*InsnID*/1, 9964 // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRAI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) 9965 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI, 9966 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9967 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9968 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 9969 GIR_EraseFromParent, /*InsnID*/0, 9970 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9971 // GIR_Coverage, 65, 9972 GIR_Done, 9973 // Label 702: @22356 9974 GIM_Try, /*On fail goto*//*Label 703*/ 22389, // Rule ID 67 // 9975 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 9976 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 9977 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen, 9978 // MIs[1] Operand 1 9979 // No operand predicates 9980 GIM_CheckIsSafeToFold, /*InsnID*/1, 9981 // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRAI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_uimmlog2xlen>>:$shamt) 9982 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI, 9983 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 9984 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 9985 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 9986 GIR_EraseFromParent, /*InsnID*/0, 9987 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9988 // GIR_Coverage, 67, 9989 GIR_Done, 9990 // Label 703: @22389 9991 GIM_Try, /*On fail goto*//*Label 704*/ 22402, // Rule ID 80 // 9992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 9993 // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 9994 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRA, 9995 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 9996 // GIR_Coverage, 80, 9997 GIR_Done, 9998 // Label 704: @22402 9999 GIM_Try, /*On fail goto*//*Label 705*/ 22415, // Rule ID 82 // 10000 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10001 // (sra:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (SRA:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 10002 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRA, 10003 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10004 // GIR_Coverage, 82, 10005 GIR_Done, 10006 // Label 705: @22415 10007 GIM_Reject, 10008 // Label 699: @22416 10009 GIM_Reject, 10010 // Label 697: @22417 10011 GIM_Try, /*On fail goto*//*Label 706*/ 22537, 10012 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 10013 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 10014 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 10015 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 10016 GIM_Try, /*On fail goto*//*Label 707*/ 22490, // Rule ID 84 // 10017 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 10018 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND, 10019 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 10020 GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, 10021 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 10022 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] 10023 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT, 10024 GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immbottomxlenset, 10025 // MIs[2] Operand 1 10026 // No operand predicates 10027 GIM_CheckIsSafeToFold, /*InsnID*/1, 10028 GIM_CheckIsSafeToFold, /*InsnID*/2, 10029 // (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (and:{ *:[i64] } GPR:{ *:[i64] }:$rs2, (imm:{ *:[i64] })<<P:Predicate_immbottomxlenset>>)) => (SRA:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 10030 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRA, 10031 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10032 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 10033 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs2 10034 GIR_EraseFromParent, /*InsnID*/0, 10035 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10036 // GIR_Coverage, 84, 10037 GIR_Done, 10038 // Label 707: @22490 10039 GIM_Try, /*On fail goto*//*Label 708*/ 22523, // Rule ID 66 // 10040 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] 10041 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10042 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_uimmlog2xlen, 10043 // MIs[1] Operand 1 10044 // No operand predicates 10045 GIM_CheckIsSafeToFold, /*InsnID*/1, 10046 // (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) => (SRAI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_uimmlog2xlen>>:$shamt) 10047 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SRAI, 10048 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 10050 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // shamt 10051 GIR_EraseFromParent, /*InsnID*/0, 10052 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10053 // GIR_Coverage, 66, 10054 GIR_Done, 10055 // Label 708: @22523 10056 GIM_Try, /*On fail goto*//*Label 709*/ 22536, // Rule ID 81 // 10057 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10058 // (sra:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (SRA:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 10059 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::SRA, 10060 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10061 // GIR_Coverage, 81, 10062 GIR_Done, 10063 // Label 709: @22536 10064 GIM_Reject, 10065 // Label 706: @22537 10066 GIM_Reject, 10067 // Label 698: @22538 10068 GIM_Reject, 10069 // Label 31: @22539 10070 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 712*/ 24754, 10071 /*GILLT_s32*//*Label 710*/ 22547, 10072 /*GILLT_s64*//*Label 711*/ 24013, 10073 // Label 710: @22547 10074 GIM_Try, /*On fail goto*//*Label 713*/ 24012, 10075 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 10076 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 10077 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 10078 GIM_Try, /*On fail goto*//*Label 714*/ 22594, // Rule ID 102 // 10079 // MIs[0] Operand 1 10080 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, 10081 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10082 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, 10083 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] }) 10084 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10085 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10086 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10087 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10088 GIR_EraseFromParent, /*InsnID*/0, 10089 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10090 // GIR_Coverage, 102, 10091 GIR_Done, 10092 // Label 714: @22594 10093 GIM_Try, /*On fail goto*//*Label 715*/ 22627, // Rule ID 104 // 10094 // MIs[0] Operand 1 10095 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, 10096 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10097 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, 10098 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 1:{ *:[i32] }) 10099 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10100 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10101 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10102 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10103 GIR_EraseFromParent, /*InsnID*/0, 10104 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10105 // GIR_Coverage, 104, 10106 GIR_Done, 10107 // Label 715: @22627 10108 GIM_Try, /*On fail goto*//*Label 716*/ 22661, // Rule ID 111 // 10109 // MIs[0] Operand 1 10110 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, 10111 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10112 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, 10113 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1) 10114 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10115 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10116 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 10117 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10118 GIR_EraseFromParent, /*InsnID*/0, 10119 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10120 // GIR_Coverage, 111, 10121 GIR_Done, 10122 // Label 716: @22661 10123 GIM_Try, /*On fail goto*//*Label 717*/ 22695, // Rule ID 113 // 10124 // MIs[0] Operand 1 10125 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, 10126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10127 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, 10128 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, 0:{ *:[i32] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, GPR:{ *:[i32] }:$rs1) 10129 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10130 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10131 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 10132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10133 GIR_EraseFromParent, /*InsnID*/0, 10134 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10135 // GIR_Coverage, 113, 10136 GIR_Done, 10137 // Label 717: @22695 10138 GIM_Try, /*On fail goto*//*Label 718*/ 22736, // Rule ID 93 // 10139 // MIs[0] Operand 1 10140 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, 10141 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10142 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10143 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10144 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10145 // MIs[1] Operand 1 10146 // No operand predicates 10147 GIM_CheckIsSafeToFold, /*InsnID*/1, 10148 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 10149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI, 10150 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10151 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10152 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 10153 GIR_EraseFromParent, /*InsnID*/0, 10154 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10155 // GIR_Coverage, 93, 10156 GIR_Done, 10157 // Label 718: @22736 10158 GIM_Try, /*On fail goto*//*Label 719*/ 22777, // Rule ID 95 // 10159 // MIs[0] Operand 1 10160 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, 10161 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10162 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10163 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10164 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10165 // MIs[1] Operand 1 10166 // No operand predicates 10167 GIM_CheckIsSafeToFold, /*InsnID*/1, 10168 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 10169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI, 10170 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10171 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10172 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 10173 GIR_EraseFromParent, /*InsnID*/0, 10174 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10175 // GIR_Coverage, 95, 10176 GIR_Done, 10177 // Label 719: @22777 10178 GIM_Try, /*On fail goto*//*Label 720*/ 22818, // Rule ID 99 // 10179 // MIs[0] Operand 1 10180 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, 10181 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10182 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10183 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10184 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10185 // MIs[1] Operand 1 10186 // No operand predicates 10187 GIM_CheckIsSafeToFold, /*InsnID*/1, 10188 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 10189 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10190 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10191 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10192 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 10193 GIR_EraseFromParent, /*InsnID*/0, 10194 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10195 // GIR_Coverage, 99, 10196 GIR_Done, 10197 // Label 720: @22818 10198 GIM_Try, /*On fail goto*//*Label 721*/ 22859, // Rule ID 101 // 10199 // MIs[0] Operand 1 10200 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, 10201 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10202 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10203 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10204 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10205 // MIs[1] Operand 1 10206 // No operand predicates 10207 GIM_CheckIsSafeToFold, /*InsnID*/1, 10208 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12) 10209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10211 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10212 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 10213 GIR_EraseFromParent, /*InsnID*/0, 10214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10215 // GIR_Coverage, 101, 10216 GIR_Done, 10217 // Label 721: @22859 10218 GIM_Try, /*On fail goto*//*Label 722*/ 22919, // Rule ID 108 // 10219 // MIs[0] Operand 1 10220 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, 10221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10222 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10223 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10224 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10225 // MIs[1] Operand 1 10226 // No operand predicates 10227 GIM_CheckIsSafeToFold, /*InsnID*/1, 10228 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), 1:{ *:[i32] }) 10229 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10230 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI, 10231 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10232 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10233 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12 10234 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10235 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10236 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10237 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10238 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10239 GIR_EraseFromParent, /*InsnID*/0, 10240 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10241 // GIR_Coverage, 108, 10242 GIR_Done, 10243 // Label 722: @22919 10244 GIM_Try, /*On fail goto*//*Label 723*/ 22979, // Rule ID 110 // 10245 // MIs[0] Operand 1 10246 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, 10247 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10248 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10249 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10250 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10251 // MIs[1] Operand 1 10252 // No operand predicates 10253 GIM_CheckIsSafeToFold, /*InsnID*/1, 10254 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12), 1:{ *:[i32] }) 10255 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10256 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI, 10257 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10258 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10259 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12 10260 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10261 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10262 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10263 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10264 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10265 GIR_EraseFromParent, /*InsnID*/0, 10266 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10267 // GIR_Coverage, 110, 10268 GIR_Done, 10269 // Label 723: @22979 10270 GIM_Try, /*On fail goto*//*Label 724*/ 23040, // Rule ID 117 // 10271 // MIs[0] Operand 1 10272 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, 10273 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10274 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10275 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10276 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10277 // MIs[1] Operand 1 10278 // No operand predicates 10279 GIM_CheckIsSafeToFold, /*InsnID*/1, 10280 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)) 10281 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10282 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI, 10283 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10284 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10285 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12 10286 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10287 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10288 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10289 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 10290 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10291 GIR_EraseFromParent, /*InsnID*/0, 10292 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10293 // GIR_Coverage, 117, 10294 GIR_Done, 10295 // Label 724: @23040 10296 GIM_Try, /*On fail goto*//*Label 725*/ 23101, // Rule ID 119 // 10297 // MIs[0] Operand 1 10298 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, 10299 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10300 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10301 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10302 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10303 // MIs[1] Operand 1 10304 // No operand predicates 10305 GIM_CheckIsSafeToFold, /*InsnID*/1, 10306 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XORI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)) 10307 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10308 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI, 10309 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10310 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10311 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12 10312 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10313 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10314 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10315 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 10316 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10317 GIR_EraseFromParent, /*InsnID*/0, 10318 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10319 // GIR_Coverage, 119, 10320 GIR_Done, 10321 // Label 725: @23101 10322 GIM_Try, /*On fail goto*//*Label 726*/ 23135, // Rule ID 90 // 10323 // MIs[0] Operand 1 10324 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, 10325 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10326 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10327 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 10328 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT, 10329 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10330 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10331 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10332 GIR_EraseFromParent, /*InsnID*/0, 10333 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10334 // GIR_Coverage, 90, 10335 GIR_Done, 10336 // Label 726: @23135 10337 GIM_Try, /*On fail goto*//*Label 727*/ 23169, // Rule ID 92 // 10338 // MIs[0] Operand 1 10339 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, 10340 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10341 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10342 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 10343 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT, 10344 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10345 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10347 GIR_EraseFromParent, /*InsnID*/0, 10348 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10349 // GIR_Coverage, 92, 10350 GIR_Done, 10351 // Label 727: @23169 10352 GIM_Try, /*On fail goto*//*Label 728*/ 23203, // Rule ID 96 // 10353 // MIs[0] Operand 1 10354 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, 10355 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10356 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10357 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 10358 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10359 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10360 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10361 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10362 GIR_EraseFromParent, /*InsnID*/0, 10363 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10364 // GIR_Coverage, 96, 10365 GIR_Done, 10366 // Label 728: @23203 10367 GIM_Try, /*On fail goto*//*Label 729*/ 23237, // Rule ID 98 // 10368 // MIs[0] Operand 1 10369 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, 10370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10371 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10372 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 10373 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10374 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10375 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10376 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10377 GIR_EraseFromParent, /*InsnID*/0, 10378 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10379 // GIR_Coverage, 98, 10380 GIR_Done, 10381 // Label 729: @23237 10382 GIM_Try, /*On fail goto*//*Label 730*/ 23290, // Rule ID 105 // 10383 // MIs[0] Operand 1 10384 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, 10385 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10386 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10387 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) 10388 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10389 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR, 10390 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10391 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10392 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10393 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10394 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10395 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10396 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10397 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10398 GIR_EraseFromParent, /*InsnID*/0, 10399 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10400 // GIR_Coverage, 105, 10401 GIR_Done, 10402 // Label 730: @23290 10403 GIM_Try, /*On fail goto*//*Label 731*/ 23343, // Rule ID 107 // 10404 // MIs[0] Operand 1 10405 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, 10406 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10407 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10408 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i32] } (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) 10409 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10410 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR, 10411 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10412 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10413 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10414 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10417 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10418 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10419 GIR_EraseFromParent, /*InsnID*/0, 10420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10421 // GIR_Coverage, 107, 10422 GIR_Done, 10423 // Label 731: @23343 10424 GIM_Try, /*On fail goto*//*Label 732*/ 23397, // Rule ID 114 // 10425 // MIs[0] Operand 1 10426 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, 10427 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10428 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10429 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) 10430 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10431 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR, 10432 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10433 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10434 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10435 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10436 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10437 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10438 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 10439 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10440 GIR_EraseFromParent, /*InsnID*/0, 10441 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10442 // GIR_Coverage, 114, 10443 GIR_Done, 10444 // Label 732: @23397 10445 GIM_Try, /*On fail goto*//*Label 733*/ 23451, // Rule ID 116 // 10446 // MIs[0] Operand 1 10447 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, 10448 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10449 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10450 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i32] } X0:{ *:[i32] }, (XOR:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2)) 10451 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10452 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR, 10453 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10454 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10455 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10456 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10457 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10458 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10459 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 10460 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10461 GIR_EraseFromParent, /*InsnID*/0, 10462 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10463 // GIR_Coverage, 116, 10464 GIR_Done, 10465 // Label 733: @23451 10466 GIM_Try, /*On fail goto*//*Label 734*/ 23485, // Rule ID 120 // 10467 // MIs[0] Operand 1 10468 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, 10469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10471 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1) 10472 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10475 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10476 GIR_EraseFromParent, /*InsnID*/0, 10477 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10478 // GIR_Coverage, 120, 10479 GIR_Done, 10480 // Label 734: @23485 10481 GIM_Try, /*On fail goto*//*Label 735*/ 23519, // Rule ID 122 // 10482 // MIs[0] Operand 1 10483 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, 10484 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10485 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10486 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1) 10487 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10488 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10489 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10490 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10491 GIR_EraseFromParent, /*InsnID*/0, 10492 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10493 // GIR_Coverage, 122, 10494 GIR_Done, 10495 // Label 735: @23519 10496 GIM_Try, /*On fail goto*//*Label 736*/ 23572, // Rule ID 123 // 10497 // MIs[0] Operand 1 10498 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, 10499 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10500 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10501 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) 10502 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10503 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU, 10504 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10505 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10506 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10507 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10508 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10509 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10510 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10511 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10512 GIR_EraseFromParent, /*InsnID*/0, 10513 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10514 // GIR_Coverage, 123, 10515 GIR_Done, 10516 // Label 736: @23572 10517 GIM_Try, /*On fail goto*//*Label 737*/ 23625, // Rule ID 125 // 10518 // MIs[0] Operand 1 10519 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, 10520 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10521 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10522 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) 10523 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10524 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU, 10525 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10526 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10527 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10528 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10529 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10530 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10531 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10532 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10533 GIR_EraseFromParent, /*InsnID*/0, 10534 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10535 // GIR_Coverage, 125, 10536 GIR_Done, 10537 // Label 737: @23625 10538 GIM_Try, /*On fail goto*//*Label 738*/ 23678, // Rule ID 126 // 10539 // MIs[0] Operand 1 10540 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, 10541 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10542 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10543 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] }) 10544 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10545 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU, 10546 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10547 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10548 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10549 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10550 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10551 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10552 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10553 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10554 GIR_EraseFromParent, /*InsnID*/0, 10555 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10556 // GIR_Coverage, 126, 10557 GIR_Done, 10558 // Label 738: @23678 10559 GIM_Try, /*On fail goto*//*Label 739*/ 23731, // Rule ID 128 // 10560 // MIs[0] Operand 1 10561 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, 10562 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10563 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10564 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLTU:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] }) 10565 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10566 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU, 10567 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10568 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10569 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10570 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10571 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10572 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10573 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10574 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10575 GIR_EraseFromParent, /*InsnID*/0, 10576 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10577 // GIR_Coverage, 128, 10578 GIR_Done, 10579 // Label 739: @23731 10580 GIM_Try, /*On fail goto*//*Label 740*/ 23765, // Rule ID 129 // 10581 // MIs[0] Operand 1 10582 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 10583 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10584 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10585 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1) 10586 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT, 10587 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10588 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10589 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10590 GIR_EraseFromParent, /*InsnID*/0, 10591 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10592 // GIR_Coverage, 129, 10593 GIR_Done, 10594 // Label 740: @23765 10595 GIM_Try, /*On fail goto*//*Label 741*/ 23799, // Rule ID 131 // 10596 // MIs[0] Operand 1 10597 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 10598 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10599 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10600 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1) 10601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT, 10602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10605 GIR_EraseFromParent, /*InsnID*/0, 10606 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10607 // GIR_Coverage, 131, 10608 GIR_Done, 10609 // Label 741: @23799 10610 GIM_Try, /*On fail goto*//*Label 742*/ 23852, // Rule ID 132 // 10611 // MIs[0] Operand 1 10612 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, 10613 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10614 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10615 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) 10616 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10617 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT, 10618 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10619 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10620 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10621 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10624 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10625 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10626 GIR_EraseFromParent, /*InsnID*/0, 10627 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10628 // GIR_Coverage, 132, 10629 GIR_Done, 10630 // Label 742: @23852 10631 GIM_Try, /*On fail goto*//*Label 743*/ 23905, // Rule ID 134 // 10632 // MIs[0] Operand 1 10633 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, 10634 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10635 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10636 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2), 1:{ *:[i32] }) 10637 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10638 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT, 10639 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10640 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10641 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10642 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10645 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10646 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10647 GIR_EraseFromParent, /*InsnID*/0, 10648 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10649 // GIR_Coverage, 134, 10650 GIR_Done, 10651 // Label 743: @23905 10652 GIM_Try, /*On fail goto*//*Label 744*/ 23958, // Rule ID 135 // 10653 // MIs[0] Operand 1 10654 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, 10655 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10656 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10657 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] }) 10658 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10659 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT, 10660 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10661 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10662 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10663 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10666 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10667 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10668 GIR_EraseFromParent, /*InsnID*/0, 10669 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10670 // GIR_Coverage, 135, 10671 GIR_Done, 10672 // Label 744: @23958 10673 GIM_Try, /*On fail goto*//*Label 745*/ 24011, // Rule ID 137 // 10674 // MIs[0] Operand 1 10675 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, 10676 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10678 // (setcc:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i32] } (SLT:{ *:[i32] } GPR:{ *:[i32] }:$rs2, GPR:{ *:[i32] }:$rs1), 1:{ *:[i32] }) 10679 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 10680 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT, 10681 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10682 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10683 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10684 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10687 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10688 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10689 GIR_EraseFromParent, /*InsnID*/0, 10690 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10691 // GIR_Coverage, 137, 10692 GIR_Done, 10693 // Label 745: @24011 10694 GIM_Reject, 10695 // Label 713: @24012 10696 GIM_Reject, 10697 // Label 711: @24013 10698 GIM_Try, /*On fail goto*//*Label 746*/ 24753, 10699 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 10700 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 10701 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 10702 GIM_Try, /*On fail goto*//*Label 747*/ 24060, // Rule ID 103 // 10703 // MIs[0] Operand 1 10704 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, 10705 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10706 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, 10707 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 1:{ *:[i64] }) 10708 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10711 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10712 GIR_EraseFromParent, /*InsnID*/0, 10713 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10714 // GIR_Coverage, 103, 10715 GIR_Done, 10716 // Label 747: @24060 10717 GIM_Try, /*On fail goto*//*Label 748*/ 24094, // Rule ID 112 // 10718 // MIs[0] Operand 1 10719 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, 10720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10721 GIM_CheckConstantInt, /*MI*/0, /*Op*/3, 0, 10722 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, 0:{ *:[i64] }, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, GPR:{ *:[i64] }:$rs1) 10723 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10724 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10725 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 10726 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10727 GIR_EraseFromParent, /*InsnID*/0, 10728 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10729 // GIR_Coverage, 112, 10730 GIR_Done, 10731 // Label 748: @24094 10732 GIM_Try, /*On fail goto*//*Label 749*/ 24135, // Rule ID 94 // 10733 // MIs[0] Operand 1 10734 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, 10735 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10736 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10737 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10738 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10739 // MIs[1] Operand 1 10740 // No operand predicates 10741 GIM_CheckIsSafeToFold, /*InsnID*/1, 10742 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 10743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI, 10744 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10745 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10746 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 10747 GIR_EraseFromParent, /*InsnID*/0, 10748 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10749 // GIR_Coverage, 94, 10750 GIR_Done, 10751 // Label 749: @24135 10752 GIM_Try, /*On fail goto*//*Label 750*/ 24176, // Rule ID 100 // 10753 // MIs[0] Operand 1 10754 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, 10755 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10756 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10757 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10758 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10759 // MIs[1] Operand 1 10760 // No operand predicates 10761 GIM_CheckIsSafeToFold, /*InsnID*/1, 10762 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETULT:{ *:[Other] }) => (SLTIU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12) 10763 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10766 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm12 10767 GIR_EraseFromParent, /*InsnID*/0, 10768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10769 // GIR_Coverage, 100, 10770 GIR_Done, 10771 // Label 750: @24176 10772 GIM_Try, /*On fail goto*//*Label 751*/ 24236, // Rule ID 109 // 10773 // MIs[0] Operand 1 10774 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, 10775 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10776 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10777 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10778 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10779 // MIs[1] Operand 1 10780 // No operand predicates 10781 GIM_CheckIsSafeToFold, /*InsnID*/1, 10782 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12), 1:{ *:[i64] }) 10783 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10784 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI, 10785 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10786 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10787 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12 10788 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10789 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10791 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10792 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10793 GIR_EraseFromParent, /*InsnID*/0, 10794 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10795 // GIR_Coverage, 109, 10796 GIR_Done, 10797 // Label 751: @24236 10798 GIM_Try, /*On fail goto*//*Label 752*/ 24297, // Rule ID 118 // 10799 // MIs[0] Operand 1 10800 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, 10801 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10802 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 10803 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT, 10804 GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_simm12, 10805 // MIs[1] Operand 1 10806 // No operand predicates 10807 GIM_CheckIsSafeToFold, /*InsnID*/1, 10808 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XORI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)) 10809 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10810 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XORI, 10811 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10812 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10813 GIR_CopyConstantAsSImm, /*NewInsnID*/1, /*OldInsnID*/1, // imm12 10814 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10815 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10816 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10817 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 10818 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10819 GIR_EraseFromParent, /*InsnID*/0, 10820 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10821 // GIR_Coverage, 118, 10822 GIR_Done, 10823 // Label 752: @24297 10824 GIM_Try, /*On fail goto*//*Label 753*/ 24331, // Rule ID 91 // 10825 // MIs[0] Operand 1 10826 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLT, 10827 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10829 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLT:{ *:[Other] }) => (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 10830 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT, 10831 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10832 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10834 GIR_EraseFromParent, /*InsnID*/0, 10835 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10836 // GIR_Coverage, 91, 10837 GIR_Done, 10838 // Label 753: @24331 10839 GIM_Try, /*On fail goto*//*Label 754*/ 24365, // Rule ID 97 // 10840 // MIs[0] Operand 1 10841 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULT, 10842 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10843 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10844 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULT:{ *:[Other] }) => (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 10845 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10846 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10847 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10848 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10849 GIR_EraseFromParent, /*InsnID*/0, 10850 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10851 // GIR_Coverage, 97, 10852 GIR_Done, 10853 // Label 754: @24365 10854 GIM_Try, /*On fail goto*//*Label 755*/ 24418, // Rule ID 106 // 10855 // MIs[0] Operand 1 10856 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ, 10857 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10858 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10859 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETEQ:{ *:[Other] }) => (SLTIU:{ *:[i64] } (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] }) 10860 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10861 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR, 10862 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10863 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10864 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10865 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10866 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 10867 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10868 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10869 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10870 GIR_EraseFromParent, /*InsnID*/0, 10871 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10872 // GIR_Coverage, 106, 10873 GIR_Done, 10874 // Label 755: @24418 10875 GIM_Try, /*On fail goto*//*Label 756*/ 24472, // Rule ID 115 // 10876 // MIs[0] Operand 1 10877 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_NE, 10878 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10879 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10880 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETNE:{ *:[Other] }) => (SLTU:{ *:[i64] } X0:{ *:[i64] }, (XOR:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2)) 10881 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10882 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::XOR, 10883 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10884 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10885 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10886 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10887 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10888 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10889 GIR_AddRegister, /*InsnID*/0, RISCV::X0, /*AddRegisterRegFlags*/0, 10890 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10891 GIR_EraseFromParent, /*InsnID*/0, 10892 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10893 // GIR_Coverage, 115, 10894 GIR_Done, 10895 // Label 756: @24472 10896 GIM_Try, /*On fail goto*//*Label 757*/ 24506, // Rule ID 121 // 10897 // MIs[0] Operand 1 10898 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGT, 10899 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10900 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10901 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGT:{ *:[Other] }) => (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1) 10902 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTU, 10903 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10904 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10905 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10906 GIR_EraseFromParent, /*InsnID*/0, 10907 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10908 // GIR_Coverage, 121, 10909 GIR_Done, 10910 // Label 757: @24506 10911 GIM_Try, /*On fail goto*//*Label 758*/ 24559, // Rule ID 124 // 10912 // MIs[0] Operand 1 10913 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_UGE, 10914 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10915 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10916 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETUGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] }) 10917 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10918 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU, 10919 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10920 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10921 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10922 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10923 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10924 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10925 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10926 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10927 GIR_EraseFromParent, /*InsnID*/0, 10928 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10929 // GIR_Coverage, 124, 10930 GIR_Done, 10931 // Label 758: @24559 10932 GIM_Try, /*On fail goto*//*Label 759*/ 24612, // Rule ID 127 // 10933 // MIs[0] Operand 1 10934 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_ULE, 10935 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10936 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10937 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETULE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLTU:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] }) 10938 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10939 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLTU, 10940 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10941 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10942 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10943 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10944 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10946 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10947 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10948 GIR_EraseFromParent, /*InsnID*/0, 10949 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10950 // GIR_Coverage, 127, 10951 GIR_Done, 10952 // Label 759: @24612 10953 GIM_Try, /*On fail goto*//*Label 760*/ 24646, // Rule ID 130 // 10954 // MIs[0] Operand 1 10955 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGT, 10956 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10957 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10958 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGT:{ *:[Other] }) => (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1) 10959 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLT, 10960 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10961 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10962 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10963 GIR_EraseFromParent, /*InsnID*/0, 10964 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10965 // GIR_Coverage, 130, 10966 GIR_Done, 10967 // Label 760: @24646 10968 GIM_Try, /*On fail goto*//*Label 761*/ 24699, // Rule ID 133 // 10969 // MIs[0] Operand 1 10970 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SGE, 10971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10973 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETGE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2), 1:{ *:[i64] }) 10974 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10975 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT, 10976 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10977 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 10978 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10979 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 10980 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 10981 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 10982 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 10983 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 10984 GIR_EraseFromParent, /*InsnID*/0, 10985 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 10986 // GIR_Coverage, 133, 10987 GIR_Done, 10988 // Label 761: @24699 10989 GIM_Try, /*On fail goto*//*Label 762*/ 24752, // Rule ID 136 // 10990 // MIs[0] Operand 1 10991 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_SLE, 10992 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 10993 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::GPRRegClassID, 10994 // (setcc:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2, SETLE:{ *:[Other] }) => (XORI:{ *:[i64] } (SLT:{ *:[i64] } GPR:{ *:[i64] }:$rs2, GPR:{ *:[i64] }:$rs1), 1:{ *:[i64] }) 10995 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 10996 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::SLT, 10997 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 10998 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rs2 10999 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11000 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11001 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::XORI, 11002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11003 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11004 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 11005 GIR_EraseFromParent, /*InsnID*/0, 11006 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11007 // GIR_Coverage, 136, 11008 GIR_Done, 11009 // Label 762: @24752 11010 GIM_Reject, 11011 // Label 746: @24753 11012 GIM_Reject, 11013 // Label 712: @24754 11014 GIM_Reject, 11015 // Label 32: @24755 11016 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 765*/ 25935, 11017 /*GILLT_s32*//*Label 763*/ 24763, 11018 /*GILLT_s64*//*Label 764*/ 25544, 11019 // Label 763: @24763 11020 GIM_Try, /*On fail goto*//*Label 766*/ 24851, // Rule ID 1124 // 11021 GIM_CheckFeatures, GIFBS_HasStdExtF, 11022 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11023 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11024 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11025 // MIs[0] Operand 1 11026 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11027 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11028 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID, 11029 // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)) 11030 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11031 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11032 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S, 11033 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11034 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11035 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11036 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11037 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_S, 11038 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11039 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11040 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11041 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11042 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND, 11043 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11044 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11045 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 11046 GIR_EraseFromParent, /*InsnID*/0, 11047 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11048 // GIR_Coverage, 1124, 11049 GIR_Done, 11050 // Label 766: @24851 11051 GIM_Try, /*On fail goto*//*Label 767*/ 24939, // Rule ID 1126 // 11052 GIM_CheckFeatures, GIFBS_HasStdExtF, 11053 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11054 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11055 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11056 // MIs[0] Operand 1 11057 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11058 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11059 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID, 11060 // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)) 11061 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11062 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11063 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S, 11064 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11065 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11066 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11067 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11068 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_S, 11069 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11070 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11071 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11072 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11073 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND, 11074 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11075 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11076 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 11077 GIR_EraseFromParent, /*InsnID*/0, 11078 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11079 // GIR_Coverage, 1126, 11080 GIR_Done, 11081 // Label 767: @24939 11082 GIM_Try, /*On fail goto*//*Label 768*/ 25046, // Rule ID 1127 // 11083 GIM_CheckFeatures, GIFBS_HasStdExtF, 11084 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11085 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11086 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11087 // MIs[0] Operand 1 11088 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, 11089 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11090 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID, 11091 // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)), 1:{ *:[i32] }) 11092 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11093 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11094 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11095 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_S, 11096 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11097 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11098 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11099 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11100 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S, 11101 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11102 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11103 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11104 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11105 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND, 11106 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11107 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 11108 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 11109 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11110 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 11111 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11112 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11113 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 11114 GIR_EraseFromParent, /*InsnID*/0, 11115 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11116 // GIR_Coverage, 1127, 11117 GIR_Done, 11118 // Label 768: @25046 11119 GIM_Try, /*On fail goto*//*Label 769*/ 25153, // Rule ID 1129 // 11120 GIM_CheckFeatures, GIFBS_HasStdExtF, 11121 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11122 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11123 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11124 // MIs[0] Operand 1 11125 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, 11126 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11127 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID, 11128 // (setcc:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i32] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)), 1:{ *:[i32] }) 11129 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11130 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11131 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11132 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_S, 11133 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11134 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11135 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11136 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11137 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S, 11138 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11139 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11140 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11141 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11142 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND, 11143 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11144 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 11145 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 11146 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11147 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 11148 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11149 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11150 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 11151 GIR_EraseFromParent, /*InsnID*/0, 11152 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11153 // GIR_Coverage, 1129, 11154 GIR_Done, 11155 // Label 769: @25153 11156 GIM_Try, /*On fail goto*//*Label 770*/ 25241, // Rule ID 1267 // 11157 GIM_CheckFeatures, GIFBS_HasStdExtD, 11158 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11159 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 11160 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11161 // MIs[0] Operand 1 11162 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11163 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11164 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID, 11165 // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)) 11166 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11167 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11168 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D, 11169 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11170 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11171 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11172 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11173 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_D, 11174 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11175 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11176 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11177 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11178 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND, 11179 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11180 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11181 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 11182 GIR_EraseFromParent, /*InsnID*/0, 11183 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11184 // GIR_Coverage, 1267, 11185 GIR_Done, 11186 // Label 770: @25241 11187 GIM_Try, /*On fail goto*//*Label 771*/ 25329, // Rule ID 1269 // 11188 GIM_CheckFeatures, GIFBS_HasStdExtD, 11189 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11190 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 11191 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11192 // MIs[0] Operand 1 11193 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11194 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11195 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID, 11196 // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)) 11197 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11198 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11199 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D, 11200 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11201 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11202 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11203 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11204 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_D, 11205 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11206 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11207 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11208 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11209 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND, 11210 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11211 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11212 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 11213 GIR_EraseFromParent, /*InsnID*/0, 11214 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11215 // GIR_Coverage, 1269, 11216 GIR_Done, 11217 // Label 771: @25329 11218 GIM_Try, /*On fail goto*//*Label 772*/ 25436, // Rule ID 1270 // 11219 GIM_CheckFeatures, GIFBS_HasStdExtD, 11220 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11221 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 11222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11223 // MIs[0] Operand 1 11224 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, 11225 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11226 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID, 11227 // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)), 1:{ *:[i32] }) 11228 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11229 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11230 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11231 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_D, 11232 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11233 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11234 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11235 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11236 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D, 11237 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11238 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11239 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11240 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11241 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND, 11242 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11243 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 11244 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 11245 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11246 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 11247 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11248 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11249 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 11250 GIR_EraseFromParent, /*InsnID*/0, 11251 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11252 // GIR_Coverage, 1270, 11253 GIR_Done, 11254 // Label 772: @25436 11255 GIM_Try, /*On fail goto*//*Label 773*/ 25543, // Rule ID 1272 // 11256 GIM_CheckFeatures, GIFBS_HasStdExtD, 11257 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11258 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 11259 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11260 // MIs[0] Operand 1 11261 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, 11262 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11263 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID, 11264 // (setcc:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i32] } (AND:{ *:[i32] } (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)), 1:{ *:[i32] }) 11265 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, 11266 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, 11267 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, 11268 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_D, 11269 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11270 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11271 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11272 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11273 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D, 11274 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11275 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11276 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11277 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11278 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND, 11279 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11280 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 11281 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 11282 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11283 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 11284 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11285 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11286 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 11287 GIR_EraseFromParent, /*InsnID*/0, 11288 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11289 // GIR_Coverage, 1272, 11290 GIR_Done, 11291 // Label 773: @25543 11292 GIM_Reject, 11293 // Label 764: @25544 11294 GIM_Try, /*On fail goto*//*Label 774*/ 25632, // Rule ID 1125 // 11295 GIM_CheckFeatures, GIFBS_HasStdExtF, 11296 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11297 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11298 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11299 // MIs[0] Operand 1 11300 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11301 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11302 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID, 11303 // (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i64] } (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)) 11304 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 11305 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 11306 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S, 11307 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11308 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11309 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11310 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11311 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_S, 11312 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11313 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11314 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11315 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11316 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND, 11317 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11318 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11319 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 11320 GIR_EraseFromParent, /*InsnID*/0, 11321 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11322 // GIR_Coverage, 1125, 11323 GIR_Done, 11324 // Label 774: @25632 11325 GIM_Try, /*On fail goto*//*Label 775*/ 25739, // Rule ID 1128 // 11326 GIM_CheckFeatures, GIFBS_HasStdExtF, 11327 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11328 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11329 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11330 // MIs[0] Operand 1 11331 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, 11332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID, 11334 // (setcc:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i64] } (AND:{ *:[i64] } (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs1), (FEQ_S:{ *:[i64] } FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs2)), 1:{ *:[i64] }) 11335 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 11336 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 11337 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11338 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_S, 11339 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11340 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11341 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11342 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11343 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_S, 11344 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11345 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11346 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11347 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11348 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND, 11349 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11350 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 11351 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 11352 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11353 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 11354 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11355 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11356 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 11357 GIR_EraseFromParent, /*InsnID*/0, 11358 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11359 // GIR_Coverage, 1128, 11360 GIR_Done, 11361 // Label 775: @25739 11362 GIM_Try, /*On fail goto*//*Label 776*/ 25827, // Rule ID 1268 // 11363 GIM_CheckFeatures, GIFBS_HasStdExtD, 11364 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11365 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 11366 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11367 // MIs[0] Operand 1 11368 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_ORD, 11369 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11370 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID, 11371 // (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETO:{ *:[Other] }) => (AND:{ *:[i64] } (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)) 11372 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 11373 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 11374 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D, 11375 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11376 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11377 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11378 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11379 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::FEQ_D, 11380 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11381 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11382 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11383 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11384 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::AND, 11385 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11386 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11387 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/1, /*TempRegFlags*/0, 11388 GIR_EraseFromParent, /*InsnID*/0, 11389 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11390 // GIR_Coverage, 1268, 11391 GIR_Done, 11392 // Label 776: @25827 11393 GIM_Try, /*On fail goto*//*Label 777*/ 25934, // Rule ID 1271 // 11394 GIM_CheckFeatures, GIFBS_HasStdExtD, 11395 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11396 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 11397 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11398 // MIs[0] Operand 1 11399 GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_UNO, 11400 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11401 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID, 11402 // (setcc:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, SETUO:{ *:[Other] }) => (SLTIU:{ *:[i64] } (AND:{ *:[i64] } (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs1), (FEQ_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs2)), 1:{ *:[i64] }) 11403 GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, 11404 GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, 11405 GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, 11406 GIR_BuildMI, /*InsnID*/3, /*Opcode*/RISCV::FEQ_D, 11407 GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/RegState::Define, 11408 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11409 GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // rs2 11410 GIR_ConstrainSelectedInstOperands, /*InsnID*/3, 11411 GIR_BuildMI, /*InsnID*/2, /*Opcode*/RISCV::FEQ_D, 11412 GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/RegState::Define, 11413 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11414 GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // rs1 11415 GIR_ConstrainSelectedInstOperands, /*InsnID*/2, 11416 GIR_BuildMI, /*InsnID*/1, /*Opcode*/RISCV::AND, 11417 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/RegState::Define, 11418 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/0, 11419 GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/2, /*TempRegFlags*/0, 11420 GIR_ConstrainSelectedInstOperands, /*InsnID*/1, 11421 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTIU, 11422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11423 GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/0, 11424 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 11425 GIR_EraseFromParent, /*InsnID*/0, 11426 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11427 // GIR_Coverage, 1271, 11428 GIR_Done, 11429 // Label 777: @25934 11430 GIM_Reject, 11431 // Label 765: @25935 11432 GIM_Reject, 11433 // Label 33: @25936 11434 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 780*/ 26022, 11435 /*GILLT_s32*//*Label 778*/ 25944, 11436 /*GILLT_s64*//*Label 779*/ 25990, 11437 // Label 778: @25944 11438 GIM_Try, /*On fail goto*//*Label 781*/ 25989, 11439 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 11440 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11441 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11442 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 11443 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 11444 GIM_Try, /*On fail goto*//*Label 782*/ 25977, // Rule ID 479 // 11445 GIM_CheckFeatures, GIFBS_HasStdExtM, 11446 // (mulhu:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 11447 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULHU, 11448 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11449 // GIR_Coverage, 479, 11450 GIR_Done, 11451 // Label 782: @25977 11452 GIM_Try, /*On fail goto*//*Label 783*/ 25988, // Rule ID 481 // 11453 GIM_CheckFeatures, GIFBS_HasStdExtM, 11454 // (mulhu:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULHU:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 11455 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULHU, 11456 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11457 // GIR_Coverage, 481, 11458 GIR_Done, 11459 // Label 783: @25988 11460 GIM_Reject, 11461 // Label 781: @25989 11462 GIM_Reject, 11463 // Label 779: @25990 11464 GIM_Try, /*On fail goto*//*Label 784*/ 26021, // Rule ID 480 // 11465 GIM_CheckFeatures, GIFBS_HasStdExtM, 11466 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 11467 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11468 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11469 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 11470 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 11471 // (mulhu:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MULHU:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 11472 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULHU, 11473 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11474 // GIR_Coverage, 480, 11475 GIR_Done, 11476 // Label 784: @26021 11477 GIM_Reject, 11478 // Label 780: @26022 11479 GIM_Reject, 11480 // Label 34: @26023 11481 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 787*/ 26109, 11482 /*GILLT_s32*//*Label 785*/ 26031, 11483 /*GILLT_s64*//*Label 786*/ 26077, 11484 // Label 785: @26031 11485 GIM_Try, /*On fail goto*//*Label 788*/ 26076, 11486 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 11487 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11488 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11489 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 11490 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 11491 GIM_Try, /*On fail goto*//*Label 789*/ 26064, // Rule ID 476 // 11492 GIM_CheckFeatures, GIFBS_HasStdExtM, 11493 // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 11494 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULH, 11495 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11496 // GIR_Coverage, 476, 11497 GIR_Done, 11498 // Label 789: @26064 11499 GIM_Try, /*On fail goto*//*Label 790*/ 26075, // Rule ID 478 // 11500 GIM_CheckFeatures, GIFBS_HasStdExtM, 11501 // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) => (MULH:{ *:[i32] } GPR:{ *:[i32] }:$rs1, GPR:{ *:[i32] }:$rs2) 11502 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULH, 11503 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11504 // GIR_Coverage, 478, 11505 GIR_Done, 11506 // Label 790: @26075 11507 GIM_Reject, 11508 // Label 788: @26076 11509 GIM_Reject, 11510 // Label 786: @26077 11511 GIM_Try, /*On fail goto*//*Label 791*/ 26108, // Rule ID 477 // 11512 GIM_CheckFeatures, GIFBS_HasStdExtM, 11513 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 11514 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11515 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 11516 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 11517 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::GPRRegClassID, 11518 // (mulhs:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) => (MULH:{ *:[i64] } GPR:{ *:[i64] }:$rs1, GPR:{ *:[i64] }:$rs2) 11519 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::MULH, 11520 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11521 // GIR_Coverage, 477, 11522 GIR_Done, 11523 // Label 791: @26108 11524 GIM_Reject, 11525 // Label 787: @26109 11526 GIM_Reject, 11527 // Label 35: @26110 11528 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 794*/ 27244, 11529 /*GILLT_s32*//*Label 792*/ 26118, 11530 /*GILLT_s64*//*Label 793*/ 26681, 11531 // Label 792: @26118 11532 GIM_Try, /*On fail goto*//*Label 795*/ 26680, 11533 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 11534 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, 11535 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, 11536 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 11537 GIM_Try, /*On fail goto*//*Label 796*/ 26205, // Rule ID 1101 // 11538 GIM_CheckFeatures, GIFBS_HasStdExtF, 11539 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11540 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11541 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 11542 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11543 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11544 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 11545 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 11546 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 11547 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11548 GIM_CheckIsSafeToFold, /*InsnID*/1, 11549 GIM_CheckIsSafeToFold, /*InsnID*/2, 11550 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) 11551 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S, 11552 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11553 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11554 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11555 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 11556 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11557 GIR_EraseFromParent, /*InsnID*/0, 11558 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11559 // GIR_Coverage, 1101, 11560 GIR_Done, 11561 // Label 796: @26205 11562 GIM_Try, /*On fail goto*//*Label 797*/ 26274, // Rule ID 1102 // 11563 GIM_CheckFeatures, GIFBS_HasStdExtF, 11564 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11565 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11566 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 11567 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11568 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11569 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 11570 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 11571 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 11572 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11573 GIM_CheckIsSafeToFold, /*InsnID*/1, 11574 GIM_CheckIsSafeToFold, /*InsnID*/2, 11575 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) 11576 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S, 11577 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11578 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11579 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11580 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 11581 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11582 GIR_EraseFromParent, /*InsnID*/0, 11583 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11584 // GIR_Coverage, 1102, 11585 GIR_Done, 11586 // Label 797: @26274 11587 GIM_Try, /*On fail goto*//*Label 798*/ 26343, // Rule ID 1103 // 11588 GIM_CheckFeatures, GIFBS_HasStdExtF, 11589 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11590 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11591 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 11592 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11593 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11594 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 11595 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 11596 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, 11597 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11598 GIM_CheckIsSafeToFold, /*InsnID*/1, 11599 GIM_CheckIsSafeToFold, /*InsnID*/2, 11600 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FNMADD_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) 11601 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_S, 11602 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11603 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11604 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11605 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 11606 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11607 GIR_EraseFromParent, /*InsnID*/0, 11608 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11609 // GIR_Coverage, 1103, 11610 GIR_Done, 11611 // Label 798: @26343 11612 GIM_Try, /*On fail goto*//*Label 799*/ 26399, // Rule ID 1098 // 11613 GIM_CheckFeatures, GIFBS_HasStdExtF, 11614 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11615 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11616 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 11617 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11618 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11619 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID, 11620 GIM_CheckIsSafeToFold, /*InsnID*/1, 11621 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) 11622 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S, 11623 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11624 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11625 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11626 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3 11627 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11628 GIR_EraseFromParent, /*InsnID*/0, 11629 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11630 // GIR_Coverage, 1098, 11631 GIR_Done, 11632 // Label 799: @26399 11633 GIM_Try, /*On fail goto*//*Label 800*/ 26455, // Rule ID 1099 // 11634 GIM_CheckFeatures, GIFBS_HasStdExtF, 11635 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11636 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11637 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 11638 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11639 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11640 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID, 11641 GIM_CheckIsSafeToFold, /*InsnID*/1, 11642 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) 11643 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S, 11644 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11645 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11646 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11647 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3 11648 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11649 GIR_EraseFromParent, /*InsnID*/0, 11650 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11651 // GIR_Coverage, 1099, 11652 GIR_Done, 11653 // Label 800: @26455 11654 GIM_Try, /*On fail goto*//*Label 801*/ 26511, // Rule ID 1100 // 11655 GIM_CheckFeatures, GIFBS_HasStdExtF, 11656 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11657 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11658 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 11659 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11660 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11661 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR32RegClassID, 11662 GIM_CheckIsSafeToFold, /*InsnID*/1, 11663 // (fma:{ *:[f32] } (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs1), FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3) => (FNMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) 11664 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_S, 11665 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11666 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11667 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11668 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3 11669 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11670 GIR_EraseFromParent, /*InsnID*/0, 11671 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11672 // GIR_Coverage, 1100, 11673 GIR_Done, 11674 // Label 801: @26511 11675 GIM_Try, /*On fail goto*//*Label 802*/ 26567, // Rule ID 1095 // 11676 GIM_CheckFeatures, GIFBS_HasStdExtF, 11677 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11678 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11679 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 11680 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11681 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 11682 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11683 GIM_CheckIsSafeToFold, /*InsnID*/1, 11684 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) 11685 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S, 11686 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11687 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 11688 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11689 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 11690 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11691 GIR_EraseFromParent, /*InsnID*/0, 11692 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11693 // GIR_Coverage, 1095, 11694 GIR_Done, 11695 // Label 802: @26567 11696 GIM_Try, /*On fail goto*//*Label 803*/ 26623, // Rule ID 1096 // 11697 GIM_CheckFeatures, GIFBS_HasStdExtF, 11698 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11699 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11700 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 11701 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11702 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 11703 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11704 GIM_CheckIsSafeToFold, /*InsnID*/1, 11705 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i64] }) 11706 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S, 11707 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11708 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 11709 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11710 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 11711 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11712 GIR_EraseFromParent, /*InsnID*/0, 11713 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11714 // GIR_Coverage, 1096, 11715 GIR_Done, 11716 // Label 803: @26623 11717 GIM_Try, /*On fail goto*//*Label 804*/ 26679, // Rule ID 1097 // 11718 GIM_CheckFeatures, GIFBS_HasStdExtF, 11719 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11720 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR32RegClassID, 11721 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 11722 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11723 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, 11724 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11725 GIM_CheckIsSafeToFold, /*InsnID*/1, 11726 // (fma:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, (fneg:{ *:[f32] } FPR32:{ *:[f32] }:$rs3)) => (FMSUB_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, FPR32:{ *:[f32] }:$rs2, FPR32:{ *:[f32] }:$rs3, 7:{ *:[i32] }) 11727 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_S, 11728 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11729 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 11730 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11731 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 11732 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11733 GIR_EraseFromParent, /*InsnID*/0, 11734 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11735 // GIR_Coverage, 1097, 11736 GIR_Done, 11737 // Label 804: @26679 11738 GIM_Reject, 11739 // Label 795: @26680 11740 GIM_Reject, 11741 // Label 793: @26681 11742 GIM_Try, /*On fail goto*//*Label 805*/ 27243, 11743 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 11744 GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64, 11745 GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64, 11746 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 11747 GIM_Try, /*On fail goto*//*Label 806*/ 26768, // Rule ID 1244 // 11748 GIM_CheckFeatures, GIFBS_HasStdExtD, 11749 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11750 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11751 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 11752 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11753 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11754 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 11755 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 11756 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 11757 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11758 GIM_CheckIsSafeToFold, /*InsnID*/1, 11759 GIM_CheckIsSafeToFold, /*InsnID*/2, 11760 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) 11761 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D, 11762 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11763 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11764 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11765 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 11766 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11767 GIR_EraseFromParent, /*InsnID*/0, 11768 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11769 // GIR_Coverage, 1244, 11770 GIR_Done, 11771 // Label 806: @26768 11772 GIM_Try, /*On fail goto*//*Label 807*/ 26837, // Rule ID 1245 // 11773 GIM_CheckFeatures, GIFBS_HasStdExtD, 11774 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11775 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11776 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 11777 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11778 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11779 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 11780 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 11781 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 11782 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11783 GIM_CheckIsSafeToFold, /*InsnID*/1, 11784 GIM_CheckIsSafeToFold, /*InsnID*/2, 11785 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) 11786 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D, 11787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11789 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11790 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 11791 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11792 GIR_EraseFromParent, /*InsnID*/0, 11793 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11794 // GIR_Coverage, 1245, 11795 GIR_Done, 11796 // Label 807: @26837 11797 GIM_Try, /*On fail goto*//*Label 808*/ 26906, // Rule ID 1246 // 11798 GIM_CheckFeatures, GIFBS_HasStdExtD, 11799 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11800 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11801 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 11802 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11803 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11804 GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] 11805 GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_FNEG, 11806 GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, 11807 GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11808 GIM_CheckIsSafeToFold, /*InsnID*/1, 11809 GIM_CheckIsSafeToFold, /*InsnID*/2, 11810 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FNMADD_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) 11811 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMADD_D, 11812 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11813 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11814 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11815 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // rs3 11816 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11817 GIR_EraseFromParent, /*InsnID*/0, 11818 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11819 // GIR_Coverage, 1246, 11820 GIR_Done, 11821 // Label 808: @26906 11822 GIM_Try, /*On fail goto*//*Label 809*/ 26962, // Rule ID 1241 // 11823 GIM_CheckFeatures, GIFBS_HasStdExtD, 11824 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11825 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11826 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 11827 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11828 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11829 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID, 11830 GIM_CheckIsSafeToFold, /*InsnID*/1, 11831 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) 11832 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D, 11833 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11834 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11835 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11836 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3 11837 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11838 GIR_EraseFromParent, /*InsnID*/0, 11839 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11840 // GIR_Coverage, 1241, 11841 GIR_Done, 11842 // Label 809: @26962 11843 GIM_Try, /*On fail goto*//*Label 810*/ 27018, // Rule ID 1242 // 11844 GIM_CheckFeatures, GIFBS_HasStdExtD, 11845 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11846 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11847 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 11848 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11849 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11850 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID, 11851 GIM_CheckIsSafeToFold, /*InsnID*/1, 11852 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) 11853 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D, 11854 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11855 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11856 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11857 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3 11858 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11859 GIR_EraseFromParent, /*InsnID*/0, 11860 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11861 // GIR_Coverage, 1242, 11862 GIR_Done, 11863 // Label 810: @27018 11864 GIM_Try, /*On fail goto*//*Label 811*/ 27074, // Rule ID 1243 // 11865 GIM_CheckFeatures, GIFBS_HasStdExtD, 11866 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] 11867 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11868 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 11869 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11870 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11871 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/RISCV::FPR64RegClassID, 11872 GIM_CheckIsSafeToFold, /*InsnID*/1, 11873 // (fma:{ *:[f64] } (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs1), FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3) => (FNMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) 11874 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FNMSUB_D, 11875 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11876 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs1 11877 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11878 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rs3 11879 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11880 GIR_EraseFromParent, /*InsnID*/0, 11881 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11882 // GIR_Coverage, 1243, 11883 GIR_Done, 11884 // Label 811: @27074 11885 GIM_Try, /*On fail goto*//*Label 812*/ 27130, // Rule ID 1238 // 11886 GIM_CheckFeatures, GIFBS_HasStdExtD, 11887 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11888 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11889 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 11890 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11891 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 11892 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11893 GIM_CheckIsSafeToFold, /*InsnID*/1, 11894 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) 11895 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D, 11896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11897 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 11898 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11899 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 11900 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11901 GIR_EraseFromParent, /*InsnID*/0, 11902 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11903 // GIR_Coverage, 1238, 11904 GIR_Done, 11905 // Label 812: @27130 11906 GIM_Try, /*On fail goto*//*Label 813*/ 27186, // Rule ID 1239 // 11907 GIM_CheckFeatures, GIFBS_HasStdExtD, 11908 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11909 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11910 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 11911 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11912 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 11913 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11914 GIM_CheckIsSafeToFold, /*InsnID*/1, 11915 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i64] }) 11916 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D, 11917 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11918 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 11919 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11920 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 11921 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11922 GIR_EraseFromParent, /*InsnID*/0, 11923 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11924 // GIR_Coverage, 1239, 11925 GIR_Done, 11926 // Label 813: @27186 11927 GIM_Try, /*On fail goto*//*Label 814*/ 27242, // Rule ID 1240 // 11928 GIM_CheckFeatures, GIFBS_HasStdExtD, 11929 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11930 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/RISCV::FPR64RegClassID, 11931 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] 11932 GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_FNEG, 11933 GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, 11934 GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11935 GIM_CheckIsSafeToFold, /*InsnID*/1, 11936 // (fma:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, (fneg:{ *:[f64] } FPR64:{ *:[f64] }:$rs3)) => (FMSUB_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, FPR64:{ *:[f64] }:$rs2, FPR64:{ *:[f64] }:$rs3, 7:{ *:[i32] }) 11937 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FMSUB_D, 11938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11939 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 11940 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rs2 11941 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs3 11942 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11943 GIR_EraseFromParent, /*InsnID*/0, 11944 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11945 // GIR_Coverage, 1240, 11946 GIR_Done, 11947 // Label 814: @27242 11948 GIM_Reject, 11949 // Label 805: @27243 11950 GIM_Reject, 11951 // Label 794: @27244 11952 GIM_Reject, 11953 // Label 36: @27245 11954 GIM_Try, /*On fail goto*//*Label 815*/ 27272, // Rule ID 1211 // 11955 GIM_CheckFeatures, GIFBS_HasStdExtD, 11956 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 11957 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 11958 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 11959 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 11960 // (fpextend:{ *:[f64] } FPR32:{ *:[f32] }:$rs1) => (FCVT_D_S:{ *:[f64] } FPR32:{ *:[f32] }:$rs1) 11961 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_S, 11962 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11963 // GIR_Coverage, 1211, 11964 GIR_Done, 11965 // Label 815: @27272 11966 GIM_Reject, 11967 // Label 37: @27273 11968 GIM_Try, /*On fail goto*//*Label 816*/ 27361, 11969 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, 11970 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 11971 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 11972 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 11973 GIM_Try, /*On fail goto*//*Label 817*/ 27314, // Rule ID 1208 // 11974 GIM_CheckFeatures, GIFBS_HasStdExtD, 11975 // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) 11976 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D, 11977 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11978 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 11979 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11980 GIR_EraseFromParent, /*InsnID*/0, 11981 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11982 // GIR_Coverage, 1208, 11983 GIR_Done, 11984 // Label 817: @27314 11985 GIM_Try, /*On fail goto*//*Label 818*/ 27337, // Rule ID 1209 // 11986 GIM_CheckFeatures, GIFBS_HasStdExtD, 11987 // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] }) 11988 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D, 11989 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 11990 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 11991 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 11992 GIR_EraseFromParent, /*InsnID*/0, 11993 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 11994 // GIR_Coverage, 1209, 11995 GIR_Done, 11996 // Label 818: @27337 11997 GIM_Try, /*On fail goto*//*Label 819*/ 27360, // Rule ID 1210 // 11998 GIM_CheckFeatures, GIFBS_HasStdExtD, 11999 // (fpround:{ *:[f32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_S_D:{ *:[f32] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) 12000 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_S_D, 12001 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12002 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12003 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12004 GIR_EraseFromParent, /*InsnID*/0, 12005 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12006 // GIR_Coverage, 1210, 12007 GIR_Done, 12008 // Label 819: @27360 12009 GIM_Reject, 12010 // Label 816: @27361 12011 GIM_Reject, 12012 // Label 38: @27362 12013 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 822*/ 27540, 12014 /*GILLT_s32*//*Label 820*/ 27370, 12015 /*GILLT_s64*//*Label 821*/ 27478, 12016 // Label 820: @27370 12017 GIM_Try, /*On fail goto*//*Label 823*/ 27477, 12018 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12019 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 12020 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 12021 GIM_Try, /*On fail goto*//*Label 824*/ 27407, // Rule ID 1303 // 12022 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12023 // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) 12024 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D, 12025 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12026 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12027 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12028 GIR_EraseFromParent, /*InsnID*/0, 12029 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12030 // GIR_Coverage, 1303, 12031 GIR_Done, 12032 // Label 824: @27407 12033 GIM_Try, /*On fail goto*//*Label 825*/ 27430, // Rule ID 1305 // 12034 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12035 // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) 12036 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D, 12037 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12038 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12039 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12040 GIR_EraseFromParent, /*InsnID*/0, 12041 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12042 // GIR_Coverage, 1305, 12043 GIR_Done, 12044 // Label 825: @27430 12045 GIM_Try, /*On fail goto*//*Label 826*/ 27453, // Rule ID 1330 // 12046 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12047 // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) 12048 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D, 12049 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12050 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12051 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12052 GIR_EraseFromParent, /*InsnID*/0, 12053 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12054 // GIR_Coverage, 1330, 12055 GIR_Done, 12056 // Label 826: @27453 12057 GIM_Try, /*On fail goto*//*Label 827*/ 27476, // Rule ID 1332 // 12058 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12059 // (fp_to_sint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) 12060 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D, 12061 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12062 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12063 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12064 GIR_EraseFromParent, /*InsnID*/0, 12065 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12066 // GIR_Coverage, 1332, 12067 GIR_Done, 12068 // Label 827: @27476 12069 GIM_Reject, 12070 // Label 823: @27477 12071 GIM_Reject, 12072 // Label 821: @27478 12073 GIM_Try, /*On fail goto*//*Label 828*/ 27539, 12074 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12075 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 12076 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 12077 GIM_Try, /*On fail goto*//*Label 829*/ 27515, // Rule ID 1304 // 12078 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12079 // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_W_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] }) 12080 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_W_D, 12081 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12082 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12083 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12084 GIR_EraseFromParent, /*InsnID*/0, 12085 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12086 // GIR_Coverage, 1304, 12087 GIR_Done, 12088 // Label 829: @27515 12089 GIM_Try, /*On fail goto*//*Label 830*/ 27538, // Rule ID 1331 // 12090 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12091 // (fp_to_sint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_L_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] }) 12092 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_L_D, 12093 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12094 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12095 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12096 GIR_EraseFromParent, /*InsnID*/0, 12097 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12098 // GIR_Coverage, 1331, 12099 GIR_Done, 12100 // Label 830: @27538 12101 GIM_Reject, 12102 // Label 828: @27539 12103 GIM_Reject, 12104 // Label 822: @27540 12105 GIM_Reject, 12106 // Label 39: @27541 12107 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 833*/ 27719, 12108 /*GILLT_s32*//*Label 831*/ 27549, 12109 /*GILLT_s64*//*Label 832*/ 27657, 12110 // Label 831: @27549 12111 GIM_Try, /*On fail goto*//*Label 834*/ 27656, 12112 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12113 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 12114 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 12115 GIM_Try, /*On fail goto*//*Label 835*/ 27586, // Rule ID 1306 // 12116 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12117 // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_WU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) 12118 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D, 12119 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12120 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12121 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12122 GIR_EraseFromParent, /*InsnID*/0, 12123 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12124 // GIR_Coverage, 1306, 12125 GIR_Done, 12126 // Label 835: @27586 12127 GIM_Try, /*On fail goto*//*Label 836*/ 27609, // Rule ID 1308 // 12128 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12129 // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_WU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) 12130 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D, 12131 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12132 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12133 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12134 GIR_EraseFromParent, /*InsnID*/0, 12135 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12136 // GIR_Coverage, 1308, 12137 GIR_Done, 12138 // Label 836: @27609 12139 GIM_Try, /*On fail goto*//*Label 837*/ 27632, // Rule ID 1333 // 12140 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12141 // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_LU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) 12142 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D, 12143 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12144 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12145 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12146 GIR_EraseFromParent, /*InsnID*/0, 12147 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12148 // GIR_Coverage, 1333, 12149 GIR_Done, 12150 // Label 837: @27632 12151 GIM_Try, /*On fail goto*//*Label 838*/ 27655, // Rule ID 1335 // 12152 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12153 // (fp_to_uint:{ *:[i32] } FPR64:{ *:[f64] }:$rs1) => (FCVT_LU_D:{ *:[i32] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i32] }) 12154 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D, 12155 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12156 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12157 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12158 GIR_EraseFromParent, /*InsnID*/0, 12159 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12160 // GIR_Coverage, 1335, 12161 GIR_Done, 12162 // Label 838: @27655 12163 GIM_Reject, 12164 // Label 834: @27656 12165 GIM_Reject, 12166 // Label 832: @27657 12167 GIM_Try, /*On fail goto*//*Label 839*/ 27718, 12168 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12169 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::GPRRegClassID, 12170 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 12171 GIM_Try, /*On fail goto*//*Label 840*/ 27694, // Rule ID 1307 // 12172 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12173 // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_WU_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] }) 12174 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_WU_D, 12175 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12176 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12177 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12178 GIR_EraseFromParent, /*InsnID*/0, 12179 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12180 // GIR_Coverage, 1307, 12181 GIR_Done, 12182 // Label 840: @27694 12183 GIM_Try, /*On fail goto*//*Label 841*/ 27717, // Rule ID 1334 // 12184 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12185 // (fp_to_uint:{ *:[i64] } FPR64:{ *:[f64] }:$rs1) => (FCVT_LU_D:{ *:[i64] } FPR64:{ *:[f64] }:$rs1, 1:{ *:[i64] }) 12186 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_LU_D, 12187 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12188 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12189 GIR_AddImm, /*InsnID*/0, /*Imm*/1, 12190 GIR_EraseFromParent, /*InsnID*/0, 12191 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12192 // GIR_Coverage, 1334, 12193 GIR_Done, 12194 // Label 841: @27717 12195 GIM_Reject, 12196 // Label 839: @27718 12197 GIM_Reject, 12198 // Label 833: @27719 12199 GIM_Reject, 12200 // Label 40: @27720 12201 GIM_Try, /*On fail goto*//*Label 842*/ 27896, 12202 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 12203 GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/0, 2, /*)*//*default:*//*Label 845*/ 27774, 12204 /*GILLT_s32*//*Label 843*/ 27734, 12205 /*GILLT_s64*//*Label 844*/ 27754, 12206 // Label 843: @27734 12207 GIM_Try, /*On fail goto*//*Label 846*/ 27753, // Rule ID 1309 // 12208 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12209 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12210 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12211 // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_W:{ *:[f64] } GPR:{ *:[i32] }:$rs1) 12212 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_W, 12213 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12214 // GIR_Coverage, 1309, 12215 GIR_Done, 12216 // Label 846: @27753 12217 GIM_Reject, 12218 // Label 844: @27754 12219 GIM_Try, /*On fail goto*//*Label 847*/ 27773, // Rule ID 1310 // 12220 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12221 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12222 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12223 // (sint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_W:{ *:[f64] } GPR:{ *:[i64] }:$rs1) 12224 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_W, 12225 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12226 // GIR_Coverage, 1310, 12227 GIR_Done, 12228 // Label 847: @27773 12229 GIM_Reject, 12230 // Label 845: @27774 12231 GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/0, 2, /*)*//*default:*//*Label 850*/ 27860, 12232 /*GILLT_s32*//*Label 848*/ 27782, 12233 /*GILLT_s64*//*Label 849*/ 27828, 12234 // Label 848: @27782 12235 GIM_Try, /*On fail goto*//*Label 851*/ 27827, 12236 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12237 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12238 GIM_Try, /*On fail goto*//*Label 852*/ 27803, // Rule ID 1311 // 12239 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12240 // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_W:{ *:[f64] } GPR:{ *:[i32] }:$rs1) 12241 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_W, 12242 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12243 // GIR_Coverage, 1311, 12244 GIR_Done, 12245 // Label 852: @27803 12246 GIM_Try, /*On fail goto*//*Label 853*/ 27826, // Rule ID 1336 // 12247 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12248 // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_L:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] }) 12249 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L, 12250 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12251 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12252 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12253 GIR_EraseFromParent, /*InsnID*/0, 12254 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12255 // GIR_Coverage, 1336, 12256 GIR_Done, 12257 // Label 853: @27826 12258 GIM_Reject, 12259 // Label 851: @27827 12260 GIM_Reject, 12261 // Label 849: @27828 12262 GIM_Try, /*On fail goto*//*Label 854*/ 27859, // Rule ID 1337 // 12263 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12264 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12265 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12266 // (sint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_L:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] }) 12267 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L, 12268 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12269 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12270 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12271 GIR_EraseFromParent, /*InsnID*/0, 12272 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12273 // GIR_Coverage, 1337, 12274 GIR_Done, 12275 // Label 854: @27859 12276 GIM_Reject, 12277 // Label 850: @27860 12278 GIM_Try, /*On fail goto*//*Label 855*/ 27895, // Rule ID 1338 // 12279 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12280 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12281 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12282 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12283 // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_L:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] }) 12284 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_L, 12285 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12286 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12287 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12288 GIR_EraseFromParent, /*InsnID*/0, 12289 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12290 // GIR_Coverage, 1338, 12291 GIR_Done, 12292 // Label 855: @27895 12293 GIM_Reject, 12294 // Label 842: @27896 12295 GIM_Reject, 12296 // Label 41: @27897 12297 GIM_Try, /*On fail goto*//*Label 856*/ 28073, 12298 GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, 12299 GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/0, 2, /*)*//*default:*//*Label 859*/ 27951, 12300 /*GILLT_s32*//*Label 857*/ 27911, 12301 /*GILLT_s64*//*Label 858*/ 27931, 12302 // Label 857: @27911 12303 GIM_Try, /*On fail goto*//*Label 860*/ 27930, // Rule ID 1312 // 12304 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12305 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12306 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12307 // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i32] }:$rs1) 12308 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_WU, 12309 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12310 // GIR_Coverage, 1312, 12311 GIR_Done, 12312 // Label 860: @27930 12313 GIM_Reject, 12314 // Label 858: @27931 12315 GIM_Try, /*On fail goto*//*Label 861*/ 27950, // Rule ID 1313 // 12316 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12317 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12318 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12319 // (uint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i64] }:$rs1) 12320 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_WU, 12321 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12322 // GIR_Coverage, 1313, 12323 GIR_Done, 12324 // Label 861: @27950 12325 GIM_Reject, 12326 // Label 859: @27951 12327 GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/0, 2, /*)*//*default:*//*Label 864*/ 28037, 12328 /*GILLT_s32*//*Label 862*/ 27959, 12329 /*GILLT_s64*//*Label 863*/ 28005, 12330 // Label 862: @27959 12331 GIM_Try, /*On fail goto*//*Label 865*/ 28004, 12332 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12333 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12334 GIM_Try, /*On fail goto*//*Label 866*/ 27980, // Rule ID 1314 // 12335 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV32, 12336 // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_WU:{ *:[f64] } GPR:{ *:[i32] }:$rs1) 12337 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::FCVT_D_WU, 12338 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12339 // GIR_Coverage, 1314, 12340 GIR_Done, 12341 // Label 866: @27980 12342 GIM_Try, /*On fail goto*//*Label 867*/ 28003, // Rule ID 1339 // 12343 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12344 // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] }) 12345 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU, 12346 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12347 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12348 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12349 GIR_EraseFromParent, /*InsnID*/0, 12350 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12351 // GIR_Coverage, 1339, 12352 GIR_Done, 12353 // Label 867: @28003 12354 GIM_Reject, 12355 // Label 865: @28004 12356 GIM_Reject, 12357 // Label 863: @28005 12358 GIM_Try, /*On fail goto*//*Label 868*/ 28036, // Rule ID 1340 // 12359 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12360 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12361 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12362 // (uint_to_fp:{ *:[f64] } GPR:{ *:[i64] }:$rs1) => (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i64] }:$rs1, 7:{ *:[i64] }) 12363 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU, 12364 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12365 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12366 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12367 GIR_EraseFromParent, /*InsnID*/0, 12368 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12369 // GIR_Coverage, 1340, 12370 GIR_Done, 12371 // Label 868: @28036 12372 GIM_Reject, 12373 // Label 864: @28037 12374 GIM_Try, /*On fail goto*//*Label 869*/ 28072, // Rule ID 1341 // 12375 GIM_CheckFeatures, GIFBS_HasStdExtD_IsRV64, 12376 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12377 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12378 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::GPRRegClassID, 12379 // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$rs1) => (FCVT_D_LU:{ *:[f64] } GPR:{ *:[i32] }:$rs1, 7:{ *:[i32] }) 12380 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FCVT_D_LU, 12381 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12382 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12383 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12384 GIR_EraseFromParent, /*InsnID*/0, 12385 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12386 // GIR_Coverage, 1341, 12387 GIR_Done, 12388 // Label 869: @28072 12389 GIM_Reject, 12390 // Label 856: @28073 12391 GIM_Reject, 12392 // Label 42: @28074 12393 GIM_Try, /*On fail goto*//*Label 870*/ 28086, // Rule ID 3 // 12394 // MIs[0] imm20 12395 GIM_CheckIsMBB, /*MI*/0, /*Op*/0, 12396 // (br (bb:{ *:[Other] }):$imm20) => (PseudoBR (bb:{ *:[Other] }):$imm20) 12397 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/RISCV::PseudoBR, 12398 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12399 // GIR_Coverage, 3, 12400 GIR_Done, 12401 // Label 870: @28086 12402 GIM_Reject, 12403 // Label 43: @28087 12404 GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/0, 2, /*)*//*default:*//*Label 873*/ 28265, 12405 /*GILLT_s32*//*Label 871*/ 28095, 12406 /*GILLT_s64*//*Label 872*/ 28180, 12407 // Label 871: @28095 12408 GIM_Try, /*On fail goto*//*Label 874*/ 28179, 12409 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, 12410 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR32RegClassID, 12411 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR32RegClassID, 12412 GIM_Try, /*On fail goto*//*Label 875*/ 28132, // Rule ID 1085 // 12413 GIM_CheckFeatures, GIFBS_HasStdExtF, 12414 // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] }) 12415 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S, 12416 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12417 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12418 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12419 GIR_EraseFromParent, /*InsnID*/0, 12420 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12421 // GIR_Coverage, 1085, 12422 GIR_Done, 12423 // Label 875: @28132 12424 GIM_Try, /*On fail goto*//*Label 876*/ 28155, // Rule ID 1086 // 12425 GIM_CheckFeatures, GIFBS_HasStdExtF, 12426 // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i64] }) 12427 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S, 12428 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12429 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12430 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12431 GIR_EraseFromParent, /*InsnID*/0, 12432 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12433 // GIR_Coverage, 1086, 12434 GIR_Done, 12435 // Label 876: @28155 12436 GIM_Try, /*On fail goto*//*Label 877*/ 28178, // Rule ID 1087 // 12437 GIM_CheckFeatures, GIFBS_HasStdExtF, 12438 // (fsqrt:{ *:[f32] } FPR32:{ *:[f32] }:$rs1) => (FSQRT_S:{ *:[f32] } FPR32:{ *:[f32] }:$rs1, 7:{ *:[i32] }) 12439 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_S, 12440 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12441 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12442 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12443 GIR_EraseFromParent, /*InsnID*/0, 12444 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12445 // GIR_Coverage, 1087, 12446 GIR_Done, 12447 // Label 877: @28178 12448 GIM_Reject, 12449 // Label 874: @28179 12450 GIM_Reject, 12451 // Label 872: @28180 12452 GIM_Try, /*On fail goto*//*Label 878*/ 28264, 12453 GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64, 12454 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/RISCV::FPR64RegClassID, 12455 GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/RISCV::FPR64RegClassID, 12456 GIM_Try, /*On fail goto*//*Label 879*/ 28217, // Rule ID 1224 // 12457 GIM_CheckFeatures, GIFBS_HasStdExtD, 12458 // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) 12459 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D, 12460 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12461 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12462 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12463 GIR_EraseFromParent, /*InsnID*/0, 12464 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12465 // GIR_Coverage, 1224, 12466 GIR_Done, 12467 // Label 879: @28217 12468 GIM_Try, /*On fail goto*//*Label 880*/ 28240, // Rule ID 1225 // 12469 GIM_CheckFeatures, GIFBS_HasStdExtD, 12470 // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i64] }) 12471 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D, 12472 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12473 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12474 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12475 GIR_EraseFromParent, /*InsnID*/0, 12476 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12477 // GIR_Coverage, 1225, 12478 GIR_Done, 12479 // Label 880: @28240 12480 GIM_Try, /*On fail goto*//*Label 881*/ 28263, // Rule ID 1226 // 12481 GIM_CheckFeatures, GIFBS_HasStdExtD, 12482 // (fsqrt:{ *:[f64] } FPR64:{ *:[f64] }:$rs1) => (FSQRT_D:{ *:[f64] } FPR64:{ *:[f64] }:$rs1, 7:{ *:[i32] }) 12483 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::FSQRT_D, 12484 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd 12485 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1 12486 GIR_AddImm, /*InsnID*/0, /*Imm*/7, 12487 GIR_EraseFromParent, /*InsnID*/0, 12488 GIR_ConstrainSelectedInstOperands, /*InsnID*/0, 12489 // GIR_Coverage, 1226, 12490 GIR_Done, 12491 // Label 881: @28263 12492 GIM_Reject, 12493 // Label 878: @28264 12494 GIM_Reject, 12495 // Label 873: @28265 12496 GIM_Reject, 12497 // Label 44: @28266 12498 GIM_Reject, 12499 }; 12500 return MatchTable0; 12501} 12502#endif // ifdef GET_GLOBALISEL_IMPL 12503#ifdef GET_GLOBALISEL_PREDICATES_DECL 12504PredicateBitset AvailableModuleFeatures; 12505mutable PredicateBitset AvailableFunctionFeatures; 12506PredicateBitset getAvailableFeatures() const { 12507 return AvailableModuleFeatures | AvailableFunctionFeatures; 12508} 12509PredicateBitset 12510computeAvailableModuleFeatures(const RISCVSubtarget *Subtarget) const; 12511PredicateBitset 12512computeAvailableFunctionFeatures(const RISCVSubtarget *Subtarget, 12513 const MachineFunction *MF) const; 12514void setupGeneratedPerFunctionState(MachineFunction &MF) override; 12515#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL 12516#ifdef GET_GLOBALISEL_PREDICATES_INIT 12517AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), 12518AvailableFunctionFeatures() 12519#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT 12520