1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Machine Code Emitter *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9uint64_t RISCVMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, 10 SmallVectorImpl<MCFixup> &Fixups, 11 const MCSubtargetInfo &STI) const { 12 static const uint64_t InstBits[] = { 13 UINT64_C(0), 14 UINT64_C(0), 15 UINT64_C(0), 16 UINT64_C(0), 17 UINT64_C(0), 18 UINT64_C(0), 19 UINT64_C(0), 20 UINT64_C(0), 21 UINT64_C(0), 22 UINT64_C(0), 23 UINT64_C(0), 24 UINT64_C(0), 25 UINT64_C(0), 26 UINT64_C(0), 27 UINT64_C(0), 28 UINT64_C(0), 29 UINT64_C(0), 30 UINT64_C(0), 31 UINT64_C(0), 32 UINT64_C(0), 33 UINT64_C(0), 34 UINT64_C(0), 35 UINT64_C(0), 36 UINT64_C(0), 37 UINT64_C(0), 38 UINT64_C(0), 39 UINT64_C(0), 40 UINT64_C(0), 41 UINT64_C(0), 42 UINT64_C(0), 43 UINT64_C(0), 44 UINT64_C(0), 45 UINT64_C(0), 46 UINT64_C(0), 47 UINT64_C(0), 48 UINT64_C(0), 49 UINT64_C(0), 50 UINT64_C(0), 51 UINT64_C(0), 52 UINT64_C(0), 53 UINT64_C(0), 54 UINT64_C(0), 55 UINT64_C(0), 56 UINT64_C(0), 57 UINT64_C(0), 58 UINT64_C(0), 59 UINT64_C(0), 60 UINT64_C(0), 61 UINT64_C(0), 62 UINT64_C(0), 63 UINT64_C(0), 64 UINT64_C(0), 65 UINT64_C(0), 66 UINT64_C(0), 67 UINT64_C(0), 68 UINT64_C(0), 69 UINT64_C(0), 70 UINT64_C(0), 71 UINT64_C(0), 72 UINT64_C(0), 73 UINT64_C(0), 74 UINT64_C(0), 75 UINT64_C(0), 76 UINT64_C(0), 77 UINT64_C(0), 78 UINT64_C(0), 79 UINT64_C(0), 80 UINT64_C(0), 81 UINT64_C(0), 82 UINT64_C(0), 83 UINT64_C(0), 84 UINT64_C(0), 85 UINT64_C(0), 86 UINT64_C(0), 87 UINT64_C(0), 88 UINT64_C(0), 89 UINT64_C(0), 90 UINT64_C(0), 91 UINT64_C(0), 92 UINT64_C(0), 93 UINT64_C(0), 94 UINT64_C(0), 95 UINT64_C(0), 96 UINT64_C(0), 97 UINT64_C(0), 98 UINT64_C(0), 99 UINT64_C(0), 100 UINT64_C(0), 101 UINT64_C(0), 102 UINT64_C(0), 103 UINT64_C(0), 104 UINT64_C(0), 105 UINT64_C(0), 106 UINT64_C(0), 107 UINT64_C(0), 108 UINT64_C(0), 109 UINT64_C(0), 110 UINT64_C(0), 111 UINT64_C(0), 112 UINT64_C(0), 113 UINT64_C(0), 114 UINT64_C(0), 115 UINT64_C(0), 116 UINT64_C(0), 117 UINT64_C(0), 118 UINT64_C(0), 119 UINT64_C(0), 120 UINT64_C(0), 121 UINT64_C(0), 122 UINT64_C(0), 123 UINT64_C(0), 124 UINT64_C(0), 125 UINT64_C(0), 126 UINT64_C(0), 127 UINT64_C(0), 128 UINT64_C(0), 129 UINT64_C(0), 130 UINT64_C(0), 131 UINT64_C(0), 132 UINT64_C(0), 133 UINT64_C(0), 134 UINT64_C(0), 135 UINT64_C(0), 136 UINT64_C(0), 137 UINT64_C(0), 138 UINT64_C(0), 139 UINT64_C(0), 140 UINT64_C(0), 141 UINT64_C(0), 142 UINT64_C(0), 143 UINT64_C(0), 144 UINT64_C(0), 145 UINT64_C(0), 146 UINT64_C(0), 147 UINT64_C(0), 148 UINT64_C(0), 149 UINT64_C(0), 150 UINT64_C(0), 151 UINT64_C(0), 152 UINT64_C(0), 153 UINT64_C(0), 154 UINT64_C(0), 155 UINT64_C(0), 156 UINT64_C(0), 157 UINT64_C(0), 158 UINT64_C(0), 159 UINT64_C(0), 160 UINT64_C(0), 161 UINT64_C(0), 162 UINT64_C(0), 163 UINT64_C(0), 164 UINT64_C(0), 165 UINT64_C(0), 166 UINT64_C(0), 167 UINT64_C(0), 168 UINT64_C(0), 169 UINT64_C(0), 170 UINT64_C(0), 171 UINT64_C(0), 172 UINT64_C(0), 173 UINT64_C(0), 174 UINT64_C(0), 175 UINT64_C(0), 176 UINT64_C(0), 177 UINT64_C(0), 178 UINT64_C(0), 179 UINT64_C(0), 180 UINT64_C(0), 181 UINT64_C(0), 182 UINT64_C(0), 183 UINT64_C(0), 184 UINT64_C(0), 185 UINT64_C(0), 186 UINT64_C(0), 187 UINT64_C(0), 188 UINT64_C(0), 189 UINT64_C(0), 190 UINT64_C(0), 191 UINT64_C(0), 192 UINT64_C(0), 193 UINT64_C(0), 194 UINT64_C(0), 195 UINT64_C(0), 196 UINT64_C(0), 197 UINT64_C(0), 198 UINT64_C(0), 199 UINT64_C(0), 200 UINT64_C(0), 201 UINT64_C(0), 202 UINT64_C(0), 203 UINT64_C(0), 204 UINT64_C(0), 205 UINT64_C(0), 206 UINT64_C(0), 207 UINT64_C(0), 208 UINT64_C(0), 209 UINT64_C(0), 210 UINT64_C(0), 211 UINT64_C(0), 212 UINT64_C(0), 213 UINT64_C(0), 214 UINT64_C(0), 215 UINT64_C(0), 216 UINT64_C(0), 217 UINT64_C(0), 218 UINT64_C(0), 219 UINT64_C(0), 220 UINT64_C(0), 221 UINT64_C(0), 222 UINT64_C(0), 223 UINT64_C(0), 224 UINT64_C(0), 225 UINT64_C(0), 226 UINT64_C(0), 227 UINT64_C(0), 228 UINT64_C(0), 229 UINT64_C(0), 230 UINT64_C(0), 231 UINT64_C(0), 232 UINT64_C(0), 233 UINT64_C(0), 234 UINT64_C(0), 235 UINT64_C(0), 236 UINT64_C(0), 237 UINT64_C(0), 238 UINT64_C(0), 239 UINT64_C(0), 240 UINT64_C(51), // ADD 241 UINT64_C(19), // ADDI 242 UINT64_C(27), // ADDIW 243 UINT64_C(59), // ADDW 244 UINT64_C(12335), // AMOADD_D 245 UINT64_C(67121199), // AMOADD_D_AQ 246 UINT64_C(100675631), // AMOADD_D_AQ_RL 247 UINT64_C(33566767), // AMOADD_D_RL 248 UINT64_C(8239), // AMOADD_W 249 UINT64_C(67117103), // AMOADD_W_AQ 250 UINT64_C(100671535), // AMOADD_W_AQ_RL 251 UINT64_C(33562671), // AMOADD_W_RL 252 UINT64_C(1610625071), // AMOAND_D 253 UINT64_C(1677733935), // AMOAND_D_AQ 254 UINT64_C(1711288367), // AMOAND_D_AQ_RL 255 UINT64_C(1644179503), // AMOAND_D_RL 256 UINT64_C(1610620975), // AMOAND_W 257 UINT64_C(1677729839), // AMOAND_W_AQ 258 UINT64_C(1711284271), // AMOAND_W_AQ_RL 259 UINT64_C(1644175407), // AMOAND_W_RL 260 UINT64_C(3758108719), // AMOMAXU_D 261 UINT64_C(3825217583), // AMOMAXU_D_AQ 262 UINT64_C(3858772015), // AMOMAXU_D_AQ_RL 263 UINT64_C(3791663151), // AMOMAXU_D_RL 264 UINT64_C(3758104623), // AMOMAXU_W 265 UINT64_C(3825213487), // AMOMAXU_W_AQ 266 UINT64_C(3858767919), // AMOMAXU_W_AQ_RL 267 UINT64_C(3791659055), // AMOMAXU_W_RL 268 UINT64_C(2684366895), // AMOMAX_D 269 UINT64_C(2751475759), // AMOMAX_D_AQ 270 UINT64_C(2785030191), // AMOMAX_D_AQ_RL 271 UINT64_C(2717921327), // AMOMAX_D_RL 272 UINT64_C(2684362799), // AMOMAX_W 273 UINT64_C(2751471663), // AMOMAX_W_AQ 274 UINT64_C(2785026095), // AMOMAX_W_AQ_RL 275 UINT64_C(2717917231), // AMOMAX_W_RL 276 UINT64_C(3221237807), // AMOMINU_D 277 UINT64_C(3288346671), // AMOMINU_D_AQ 278 UINT64_C(3321901103), // AMOMINU_D_AQ_RL 279 UINT64_C(3254792239), // AMOMINU_D_RL 280 UINT64_C(3221233711), // AMOMINU_W 281 UINT64_C(3288342575), // AMOMINU_W_AQ 282 UINT64_C(3321897007), // AMOMINU_W_AQ_RL 283 UINT64_C(3254788143), // AMOMINU_W_RL 284 UINT64_C(2147495983), // AMOMIN_D 285 UINT64_C(2214604847), // AMOMIN_D_AQ 286 UINT64_C(2248159279), // AMOMIN_D_AQ_RL 287 UINT64_C(2181050415), // AMOMIN_D_RL 288 UINT64_C(2147491887), // AMOMIN_W 289 UINT64_C(2214600751), // AMOMIN_W_AQ 290 UINT64_C(2248155183), // AMOMIN_W_AQ_RL 291 UINT64_C(2181046319), // AMOMIN_W_RL 292 UINT64_C(1073754159), // AMOOR_D 293 UINT64_C(1140863023), // AMOOR_D_AQ 294 UINT64_C(1174417455), // AMOOR_D_AQ_RL 295 UINT64_C(1107308591), // AMOOR_D_RL 296 UINT64_C(1073750063), // AMOOR_W 297 UINT64_C(1140858927), // AMOOR_W_AQ 298 UINT64_C(1174413359), // AMOOR_W_AQ_RL 299 UINT64_C(1107304495), // AMOOR_W_RL 300 UINT64_C(134230063), // AMOSWAP_D 301 UINT64_C(201338927), // AMOSWAP_D_AQ 302 UINT64_C(234893359), // AMOSWAP_D_AQ_RL 303 UINT64_C(167784495), // AMOSWAP_D_RL 304 UINT64_C(134225967), // AMOSWAP_W 305 UINT64_C(201334831), // AMOSWAP_W_AQ 306 UINT64_C(234889263), // AMOSWAP_W_AQ_RL 307 UINT64_C(167780399), // AMOSWAP_W_RL 308 UINT64_C(536883247), // AMOXOR_D 309 UINT64_C(603992111), // AMOXOR_D_AQ 310 UINT64_C(637546543), // AMOXOR_D_AQ_RL 311 UINT64_C(570437679), // AMOXOR_D_RL 312 UINT64_C(536879151), // AMOXOR_W 313 UINT64_C(603988015), // AMOXOR_W_AQ 314 UINT64_C(637542447), // AMOXOR_W_AQ_RL 315 UINT64_C(570433583), // AMOXOR_W_RL 316 UINT64_C(28723), // AND 317 UINT64_C(28691), // ANDI 318 UINT64_C(23), // AUIPC 319 UINT64_C(99), // BEQ 320 UINT64_C(20579), // BGE 321 UINT64_C(28771), // BGEU 322 UINT64_C(16483), // BLT 323 UINT64_C(24675), // BLTU 324 UINT64_C(4195), // BNE 325 UINT64_C(12403), // CSRRC 326 UINT64_C(28787), // CSRRCI 327 UINT64_C(8307), // CSRRS 328 UINT64_C(24691), // CSRRSI 329 UINT64_C(4211), // CSRRW 330 UINT64_C(20595), // CSRRWI 331 UINT64_C(36866), // C_ADD 332 UINT64_C(1), // C_ADDI 333 UINT64_C(24833), // C_ADDI16SP 334 UINT64_C(0), // C_ADDI4SPN 335 UINT64_C(8193), // C_ADDIW 336 UINT64_C(1), // C_ADDI_HINT_IMM_ZERO 337 UINT64_C(1), // C_ADDI_HINT_X0 338 UINT64_C(1), // C_ADDI_NOP 339 UINT64_C(39969), // C_ADDW 340 UINT64_C(36866), // C_ADD_HINT 341 UINT64_C(35937), // C_AND 342 UINT64_C(34817), // C_ANDI 343 UINT64_C(49153), // C_BEQZ 344 UINT64_C(57345), // C_BNEZ 345 UINT64_C(36866), // C_EBREAK 346 UINT64_C(8192), // C_FLD 347 UINT64_C(8194), // C_FLDSP 348 UINT64_C(24576), // C_FLW 349 UINT64_C(24578), // C_FLWSP 350 UINT64_C(40960), // C_FSD 351 UINT64_C(40962), // C_FSDSP 352 UINT64_C(57344), // C_FSW 353 UINT64_C(57346), // C_FSWSP 354 UINT64_C(40961), // C_J 355 UINT64_C(8193), // C_JAL 356 UINT64_C(36866), // C_JALR 357 UINT64_C(32770), // C_JR 358 UINT64_C(24576), // C_LD 359 UINT64_C(24578), // C_LDSP 360 UINT64_C(16385), // C_LI 361 UINT64_C(16385), // C_LI_HINT 362 UINT64_C(24577), // C_LUI 363 UINT64_C(24577), // C_LUI_HINT 364 UINT64_C(16384), // C_LW 365 UINT64_C(16386), // C_LWSP 366 UINT64_C(32770), // C_MV 367 UINT64_C(32770), // C_MV_HINT 368 UINT64_C(1), // C_NOP 369 UINT64_C(1), // C_NOP_HINT 370 UINT64_C(35905), // C_OR 371 UINT64_C(57344), // C_SD 372 UINT64_C(57346), // C_SDSP 373 UINT64_C(2), // C_SLLI 374 UINT64_C(2), // C_SLLI64_HINT 375 UINT64_C(2), // C_SLLI_HINT 376 UINT64_C(33793), // C_SRAI 377 UINT64_C(33793), // C_SRAI64_HINT 378 UINT64_C(32769), // C_SRLI 379 UINT64_C(32769), // C_SRLI64_HINT 380 UINT64_C(35841), // C_SUB 381 UINT64_C(39937), // C_SUBW 382 UINT64_C(49152), // C_SW 383 UINT64_C(49154), // C_SWSP 384 UINT64_C(0), // C_UNIMP 385 UINT64_C(35873), // C_XOR 386 UINT64_C(33570867), // DIV 387 UINT64_C(33574963), // DIVU 388 UINT64_C(33574971), // DIVUW 389 UINT64_C(33570875), // DIVW 390 UINT64_C(1048691), // EBREAK 391 UINT64_C(115), // ECALL 392 UINT64_C(33554515), // FADD_D 393 UINT64_C(83), // FADD_S 394 UINT64_C(3791654995), // FCLASS_D 395 UINT64_C(3758100563), // FCLASS_S 396 UINT64_C(3525312595), // FCVT_D_L 397 UINT64_C(3526361171), // FCVT_D_LU 398 UINT64_C(1107296339), // FCVT_D_S 399 UINT64_C(3523215443), // FCVT_D_W 400 UINT64_C(3524264019), // FCVT_D_WU 401 UINT64_C(3257925715), // FCVT_LU_D 402 UINT64_C(3224371283), // FCVT_LU_S 403 UINT64_C(3256877139), // FCVT_L_D 404 UINT64_C(3223322707), // FCVT_L_S 405 UINT64_C(1074790483), // FCVT_S_D 406 UINT64_C(3491758163), // FCVT_S_L 407 UINT64_C(3492806739), // FCVT_S_LU 408 UINT64_C(3489661011), // FCVT_S_W 409 UINT64_C(3490709587), // FCVT_S_WU 410 UINT64_C(3255828563), // FCVT_WU_D 411 UINT64_C(3222274131), // FCVT_WU_S 412 UINT64_C(3254779987), // FCVT_W_D 413 UINT64_C(3221225555), // FCVT_W_S 414 UINT64_C(436207699), // FDIV_D 415 UINT64_C(402653267), // FDIV_S 416 UINT64_C(15), // FENCE 417 UINT64_C(4111), // FENCE_I 418 UINT64_C(2200961039), // FENCE_TSO 419 UINT64_C(2717917267), // FEQ_D 420 UINT64_C(2684362835), // FEQ_S 421 UINT64_C(12295), // FLD 422 UINT64_C(2717909075), // FLE_D 423 UINT64_C(2684354643), // FLE_S 424 UINT64_C(2717913171), // FLT_D 425 UINT64_C(2684358739), // FLT_S 426 UINT64_C(8199), // FLW 427 UINT64_C(33554499), // FMADD_D 428 UINT64_C(67), // FMADD_S 429 UINT64_C(704647251), // FMAX_D 430 UINT64_C(671092819), // FMAX_S 431 UINT64_C(704643155), // FMIN_D 432 UINT64_C(671088723), // FMIN_S 433 UINT64_C(33554503), // FMSUB_D 434 UINT64_C(71), // FMSUB_S 435 UINT64_C(301989971), // FMUL_D 436 UINT64_C(268435539), // FMUL_S 437 UINT64_C(4060086355), // FMV_D_X 438 UINT64_C(4026531923), // FMV_W_X 439 UINT64_C(3791650899), // FMV_X_D 440 UINT64_C(3758096467), // FMV_X_W 441 UINT64_C(33554511), // FNMADD_D 442 UINT64_C(79), // FNMADD_S 443 UINT64_C(33554507), // FNMSUB_D 444 UINT64_C(75), // FNMSUB_S 445 UINT64_C(12327), // FSD 446 UINT64_C(570429523), // FSGNJN_D 447 UINT64_C(536875091), // FSGNJN_S 448 UINT64_C(570433619), // FSGNJX_D 449 UINT64_C(536879187), // FSGNJX_S 450 UINT64_C(570425427), // FSGNJ_D 451 UINT64_C(536870995), // FSGNJ_S 452 UINT64_C(1509949523), // FSQRT_D 453 UINT64_C(1476395091), // FSQRT_S 454 UINT64_C(167772243), // FSUB_D 455 UINT64_C(134217811), // FSUB_S 456 UINT64_C(8231), // FSW 457 UINT64_C(111), // JAL 458 UINT64_C(103), // JALR 459 UINT64_C(3), // LB 460 UINT64_C(16387), // LBU 461 UINT64_C(12291), // LD 462 UINT64_C(4099), // LH 463 UINT64_C(20483), // LHU 464 UINT64_C(268447791), // LR_D 465 UINT64_C(335556655), // LR_D_AQ 466 UINT64_C(369111087), // LR_D_AQ_RL 467 UINT64_C(302002223), // LR_D_RL 468 UINT64_C(268443695), // LR_W 469 UINT64_C(335552559), // LR_W_AQ 470 UINT64_C(369106991), // LR_W_AQ_RL 471 UINT64_C(301998127), // LR_W_RL 472 UINT64_C(55), // LUI 473 UINT64_C(8195), // LW 474 UINT64_C(24579), // LWU 475 UINT64_C(807403635), // MRET 476 UINT64_C(33554483), // MUL 477 UINT64_C(33558579), // MULH 478 UINT64_C(33562675), // MULHSU 479 UINT64_C(33566771), // MULHU 480 UINT64_C(33554491), // MULW 481 UINT64_C(24627), // OR 482 UINT64_C(24595), // ORI 483 UINT64_C(33579059), // REM 484 UINT64_C(33583155), // REMU 485 UINT64_C(33583163), // REMUW 486 UINT64_C(33579067), // REMW 487 UINT64_C(35), // SB 488 UINT64_C(402665519), // SC_D 489 UINT64_C(469774383), // SC_D_AQ 490 UINT64_C(503328815), // SC_D_AQ_RL 491 UINT64_C(436219951), // SC_D_RL 492 UINT64_C(402661423), // SC_W 493 UINT64_C(469770287), // SC_W_AQ 494 UINT64_C(503324719), // SC_W_AQ_RL 495 UINT64_C(436215855), // SC_W_RL 496 UINT64_C(12323), // SD 497 UINT64_C(301990003), // SFENCE_VMA 498 UINT64_C(4131), // SH 499 UINT64_C(4147), // SLL 500 UINT64_C(4115), // SLLI 501 UINT64_C(4123), // SLLIW 502 UINT64_C(4155), // SLLW 503 UINT64_C(8243), // SLT 504 UINT64_C(8211), // SLTI 505 UINT64_C(12307), // SLTIU 506 UINT64_C(12339), // SLTU 507 UINT64_C(1073762355), // SRA 508 UINT64_C(1073762323), // SRAI 509 UINT64_C(1073762331), // SRAIW 510 UINT64_C(1073762363), // SRAW 511 UINT64_C(270532723), // SRET 512 UINT64_C(20531), // SRL 513 UINT64_C(20499), // SRLI 514 UINT64_C(20507), // SRLIW 515 UINT64_C(20539), // SRLW 516 UINT64_C(1073741875), // SUB 517 UINT64_C(1073741883), // SUBW 518 UINT64_C(8227), // SW 519 UINT64_C(3221229683), // UNIMP 520 UINT64_C(2097267), // URET 521 UINT64_C(273678451), // WFI 522 UINT64_C(16435), // XOR 523 UINT64_C(16403), // XORI 524 UINT64_C(0) 525 }; 526 const unsigned opcode = MI.getOpcode(); 527 uint64_t Value = InstBits[opcode]; 528 uint64_t op = 0; 529 (void)op; // suppress warning 530 switch (opcode) { 531 case RISCV::C_EBREAK: 532 case RISCV::C_NOP: 533 case RISCV::C_UNIMP: 534 case RISCV::EBREAK: 535 case RISCV::ECALL: 536 case RISCV::FENCE_I: 537 case RISCV::FENCE_TSO: 538 case RISCV::MRET: 539 case RISCV::SRET: 540 case RISCV::UNIMP: 541 case RISCV::URET: 542 case RISCV::WFI: { 543 break; 544 } 545 case RISCV::C_NOP_HINT: { 546 // op: imm 547 op = getImmOpValue(MI, 0, Fixups, STI); 548 Value |= (op & UINT64_C(32)) << 7; 549 Value |= (op & UINT64_C(31)) << 2; 550 break; 551 } 552 case RISCV::C_LI_HINT: 553 case RISCV::C_LUI_HINT: { 554 // op: imm 555 op = getImmOpValue(MI, 1, Fixups, STI); 556 Value |= (op & UINT64_C(32)) << 7; 557 Value |= (op & UINT64_C(31)) << 2; 558 break; 559 } 560 case RISCV::C_LI: 561 case RISCV::C_LUI: { 562 // op: imm 563 op = getImmOpValue(MI, 1, Fixups, STI); 564 Value |= (op & UINT64_C(32)) << 7; 565 Value |= (op & UINT64_C(31)) << 2; 566 // op: rd 567 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 568 op &= UINT64_C(31); 569 op <<= 7; 570 Value |= op; 571 break; 572 } 573 case RISCV::C_FLDSP: 574 case RISCV::C_LDSP: { 575 // op: imm 576 op = getImmOpValue(MI, 2, Fixups, STI); 577 Value |= (op & UINT64_C(32)) << 7; 578 Value |= (op & UINT64_C(24)) << 2; 579 Value |= (op & UINT64_C(448)) >> 4; 580 // op: rd 581 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 582 op &= UINT64_C(31); 583 op <<= 7; 584 Value |= op; 585 break; 586 } 587 case RISCV::C_FLWSP: 588 case RISCV::C_LWSP: { 589 // op: imm 590 op = getImmOpValue(MI, 2, Fixups, STI); 591 Value |= (op & UINT64_C(32)) << 7; 592 Value |= (op & UINT64_C(28)) << 2; 593 Value |= (op & UINT64_C(192)) >> 4; 594 // op: rd 595 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 596 op &= UINT64_C(31); 597 op <<= 7; 598 Value |= op; 599 break; 600 } 601 case RISCV::C_ADDI: 602 case RISCV::C_ADDIW: 603 case RISCV::C_ADDI_HINT_X0: { 604 // op: imm 605 op = getImmOpValue(MI, 2, Fixups, STI); 606 Value |= (op & UINT64_C(32)) << 7; 607 Value |= (op & UINT64_C(31)) << 2; 608 // op: rd 609 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 610 op &= UINT64_C(31); 611 op <<= 7; 612 Value |= op; 613 break; 614 } 615 case RISCV::C_ANDI: { 616 // op: imm 617 op = getImmOpValue(MI, 2, Fixups, STI); 618 Value |= (op & UINT64_C(32)) << 7; 619 Value |= (op & UINT64_C(31)) << 2; 620 // op: rs1 621 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 622 op &= UINT64_C(7); 623 op <<= 7; 624 Value |= op; 625 break; 626 } 627 case RISCV::C_ADDI4SPN: { 628 // op: imm 629 op = getImmOpValue(MI, 2, Fixups, STI); 630 Value |= (op & UINT64_C(48)) << 7; 631 Value |= (op & UINT64_C(960)) << 1; 632 Value |= (op & UINT64_C(4)) << 4; 633 Value |= (op & UINT64_C(8)) << 2; 634 // op: rd 635 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 636 op &= UINT64_C(7); 637 op <<= 2; 638 Value |= op; 639 break; 640 } 641 case RISCV::C_ADDI16SP: { 642 // op: imm 643 op = getImmOpValue(MI, 2, Fixups, STI); 644 Value |= (op & UINT64_C(512)) << 3; 645 Value |= (op & UINT64_C(16)) << 2; 646 Value |= (op & UINT64_C(64)) >> 1; 647 Value |= (op & UINT64_C(384)) >> 4; 648 Value |= (op & UINT64_C(32)) >> 3; 649 break; 650 } 651 case RISCV::C_FSDSP: 652 case RISCV::C_SDSP: { 653 // op: imm 654 op = getImmOpValue(MI, 2, Fixups, STI); 655 Value |= (op & UINT64_C(56)) << 7; 656 Value |= (op & UINT64_C(448)) << 1; 657 // op: rs2 658 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 659 op &= UINT64_C(31); 660 op <<= 2; 661 Value |= op; 662 break; 663 } 664 case RISCV::C_FSWSP: 665 case RISCV::C_SWSP: { 666 // op: imm 667 op = getImmOpValue(MI, 2, Fixups, STI); 668 Value |= (op & UINT64_C(60)) << 7; 669 Value |= (op & UINT64_C(192)) << 1; 670 // op: rs2 671 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 672 op &= UINT64_C(31); 673 op <<= 2; 674 Value |= op; 675 break; 676 } 677 case RISCV::C_BEQZ: 678 case RISCV::C_BNEZ: { 679 // op: imm 680 op = getImmOpValueAsr1(MI, 1, Fixups, STI); 681 Value |= (op & UINT64_C(128)) << 5; 682 Value |= (op & UINT64_C(12)) << 8; 683 Value |= (op & UINT64_C(96)); 684 Value |= (op & UINT64_C(3)) << 3; 685 Value |= (op & UINT64_C(16)) >> 2; 686 // op: rs1 687 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 688 op &= UINT64_C(7); 689 op <<= 7; 690 Value |= op; 691 break; 692 } 693 case RISCV::C_SLLI_HINT: { 694 // op: imm 695 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 696 Value |= (op & UINT64_C(32)) << 7; 697 Value |= (op & UINT64_C(31)) << 2; 698 break; 699 } 700 case RISCV::C_SLLI: { 701 // op: imm 702 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 703 Value |= (op & UINT64_C(32)) << 7; 704 Value |= (op & UINT64_C(31)) << 2; 705 // op: rd 706 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 707 op &= UINT64_C(31); 708 op <<= 7; 709 Value |= op; 710 break; 711 } 712 case RISCV::C_SRAI: 713 case RISCV::C_SRLI: { 714 // op: imm 715 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 716 Value |= (op & UINT64_C(32)) << 7; 717 Value |= (op & UINT64_C(31)) << 2; 718 // op: rs1 719 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 720 op &= UINT64_C(7); 721 op <<= 7; 722 Value |= op; 723 break; 724 } 725 case RISCV::C_ADDI_HINT_IMM_ZERO: 726 case RISCV::C_ADDI_NOP: { 727 // op: imm 728 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 729 op &= UINT64_C(32); 730 op <<= 7; 731 Value |= op; 732 // op: rd 733 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 734 op &= UINT64_C(31); 735 op <<= 7; 736 Value |= op; 737 break; 738 } 739 case RISCV::FSD: 740 case RISCV::FSW: 741 case RISCV::SB: 742 case RISCV::SD: 743 case RISCV::SH: 744 case RISCV::SW: { 745 // op: imm12 746 op = getImmOpValue(MI, 2, Fixups, STI); 747 Value |= (op & UINT64_C(4064)) << 20; 748 Value |= (op & UINT64_C(31)) << 7; 749 // op: rs2 750 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 751 op &= UINT64_C(31); 752 op <<= 20; 753 Value |= op; 754 // op: rs1 755 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 756 op &= UINT64_C(31); 757 op <<= 15; 758 Value |= op; 759 break; 760 } 761 case RISCV::ADDI: 762 case RISCV::ADDIW: 763 case RISCV::ANDI: 764 case RISCV::FLD: 765 case RISCV::FLW: 766 case RISCV::JALR: 767 case RISCV::LB: 768 case RISCV::LBU: 769 case RISCV::LD: 770 case RISCV::LH: 771 case RISCV::LHU: 772 case RISCV::LW: 773 case RISCV::LWU: 774 case RISCV::ORI: 775 case RISCV::SLTI: 776 case RISCV::SLTIU: 777 case RISCV::XORI: { 778 // op: imm12 779 op = getImmOpValue(MI, 2, Fixups, STI); 780 op &= UINT64_C(4095); 781 op <<= 20; 782 Value |= op; 783 // op: rs1 784 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 785 op &= UINT64_C(31); 786 op <<= 15; 787 Value |= op; 788 // op: rd 789 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 790 op &= UINT64_C(31); 791 op <<= 7; 792 Value |= op; 793 break; 794 } 795 case RISCV::BEQ: 796 case RISCV::BGE: 797 case RISCV::BGEU: 798 case RISCV::BLT: 799 case RISCV::BLTU: 800 case RISCV::BNE: { 801 // op: imm12 802 op = getImmOpValueAsr1(MI, 2, Fixups, STI); 803 Value |= (op & UINT64_C(2048)) << 20; 804 Value |= (op & UINT64_C(1008)) << 21; 805 Value |= (op & UINT64_C(15)) << 8; 806 Value |= (op & UINT64_C(1024)) >> 3; 807 // op: rs2 808 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 809 op &= UINT64_C(31); 810 op <<= 20; 811 Value |= op; 812 // op: rs1 813 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 814 op &= UINT64_C(31); 815 op <<= 15; 816 Value |= op; 817 break; 818 } 819 case RISCV::CSRRC: 820 case RISCV::CSRRCI: 821 case RISCV::CSRRS: 822 case RISCV::CSRRSI: 823 case RISCV::CSRRW: 824 case RISCV::CSRRWI: { 825 // op: imm12 826 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 827 op &= UINT64_C(4095); 828 op <<= 20; 829 Value |= op; 830 // op: rs1 831 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 832 op &= UINT64_C(31); 833 op <<= 15; 834 Value |= op; 835 // op: rd 836 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 837 op &= UINT64_C(31); 838 op <<= 7; 839 Value |= op; 840 break; 841 } 842 case RISCV::AUIPC: 843 case RISCV::LUI: { 844 // op: imm20 845 op = getImmOpValue(MI, 1, Fixups, STI); 846 op &= UINT64_C(1048575); 847 op <<= 12; 848 Value |= op; 849 // op: rd 850 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 851 op &= UINT64_C(31); 852 op <<= 7; 853 Value |= op; 854 break; 855 } 856 case RISCV::JAL: { 857 // op: imm20 858 op = getImmOpValueAsr1(MI, 1, Fixups, STI); 859 Value |= (op & UINT64_C(524288)) << 12; 860 Value |= (op & UINT64_C(1023)) << 21; 861 Value |= (op & UINT64_C(1024)) << 10; 862 Value |= (op & UINT64_C(522240)) << 1; 863 // op: rd 864 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 865 op &= UINT64_C(31); 866 op <<= 7; 867 Value |= op; 868 break; 869 } 870 case RISCV::C_J: 871 case RISCV::C_JAL: { 872 // op: offset 873 op = getImmOpValueAsr1(MI, 0, Fixups, STI); 874 Value |= (op & UINT64_C(1024)) << 2; 875 Value |= (op & UINT64_C(8)) << 8; 876 Value |= (op & UINT64_C(384)) << 2; 877 Value |= (op & UINT64_C(512)) >> 1; 878 Value |= (op & UINT64_C(32)) << 2; 879 Value |= (op & UINT64_C(64)); 880 Value |= (op & UINT64_C(7)) << 3; 881 Value |= (op & UINT64_C(16)) >> 2; 882 break; 883 } 884 case RISCV::FENCE: { 885 // op: pred 886 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 887 op &= UINT64_C(15); 888 op <<= 24; 889 Value |= op; 890 // op: succ 891 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 892 op &= UINT64_C(15); 893 op <<= 20; 894 Value |= op; 895 break; 896 } 897 case RISCV::C_FLD: 898 case RISCV::C_LD: { 899 // op: rd 900 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 901 op &= UINT64_C(7); 902 op <<= 2; 903 Value |= op; 904 // op: rs1 905 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 906 op &= UINT64_C(7); 907 op <<= 7; 908 Value |= op; 909 // op: imm 910 op = getImmOpValue(MI, 2, Fixups, STI); 911 Value |= (op & UINT64_C(56)) << 7; 912 Value |= (op & UINT64_C(192)) >> 1; 913 break; 914 } 915 case RISCV::C_FLW: 916 case RISCV::C_LW: { 917 // op: rd 918 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 919 op &= UINT64_C(7); 920 op <<= 2; 921 Value |= op; 922 // op: rs1 923 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 924 op &= UINT64_C(7); 925 op <<= 7; 926 Value |= op; 927 // op: imm 928 op = getImmOpValue(MI, 2, Fixups, STI); 929 Value |= (op & UINT64_C(56)) << 7; 930 Value |= (op & UINT64_C(4)) << 4; 931 Value |= (op & UINT64_C(64)) >> 1; 932 break; 933 } 934 case RISCV::C_SLLI64_HINT: { 935 // op: rd 936 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 937 op &= UINT64_C(31); 938 op <<= 7; 939 Value |= op; 940 break; 941 } 942 case RISCV::C_SRAI64_HINT: 943 case RISCV::C_SRLI64_HINT: { 944 // op: rd 945 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 946 op &= UINT64_C(7); 947 op <<= 7; 948 Value |= op; 949 break; 950 } 951 case RISCV::C_JALR: 952 case RISCV::C_JR: { 953 // op: rs1 954 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 955 op &= UINT64_C(31); 956 op <<= 7; 957 Value |= op; 958 break; 959 } 960 case RISCV::C_MV: { 961 // op: rs1 962 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 963 op &= UINT64_C(31); 964 op <<= 7; 965 Value |= op; 966 // op: rs2 967 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 968 op &= UINT64_C(31); 969 op <<= 2; 970 Value |= op; 971 break; 972 } 973 case RISCV::FCVT_D_L: 974 case RISCV::FCVT_D_LU: 975 case RISCV::FCVT_LU_D: 976 case RISCV::FCVT_LU_S: 977 case RISCV::FCVT_L_D: 978 case RISCV::FCVT_L_S: 979 case RISCV::FCVT_S_D: 980 case RISCV::FCVT_S_L: 981 case RISCV::FCVT_S_LU: 982 case RISCV::FCVT_S_W: 983 case RISCV::FCVT_S_WU: 984 case RISCV::FCVT_WU_D: 985 case RISCV::FCVT_WU_S: 986 case RISCV::FCVT_W_D: 987 case RISCV::FCVT_W_S: 988 case RISCV::FSQRT_D: 989 case RISCV::FSQRT_S: { 990 // op: rs1 991 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 992 op &= UINT64_C(31); 993 op <<= 15; 994 Value |= op; 995 // op: funct3 996 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 997 op &= UINT64_C(7); 998 op <<= 12; 999 Value |= op; 1000 // op: rd 1001 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1002 op &= UINT64_C(31); 1003 op <<= 7; 1004 Value |= op; 1005 break; 1006 } 1007 case RISCV::FCLASS_D: 1008 case RISCV::FCLASS_S: 1009 case RISCV::FCVT_D_S: 1010 case RISCV::FCVT_D_W: 1011 case RISCV::FCVT_D_WU: 1012 case RISCV::FMV_D_X: 1013 case RISCV::FMV_W_X: 1014 case RISCV::FMV_X_D: 1015 case RISCV::FMV_X_W: 1016 case RISCV::LR_D: 1017 case RISCV::LR_D_AQ: 1018 case RISCV::LR_D_AQ_RL: 1019 case RISCV::LR_D_RL: 1020 case RISCV::LR_W: 1021 case RISCV::LR_W_AQ: 1022 case RISCV::LR_W_AQ_RL: 1023 case RISCV::LR_W_RL: { 1024 // op: rs1 1025 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1026 op &= UINT64_C(31); 1027 op <<= 15; 1028 Value |= op; 1029 // op: rd 1030 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1031 op &= UINT64_C(31); 1032 op <<= 7; 1033 Value |= op; 1034 break; 1035 } 1036 case RISCV::C_ADD: { 1037 // op: rs1 1038 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1039 op &= UINT64_C(31); 1040 op <<= 7; 1041 Value |= op; 1042 // op: rs2 1043 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 1044 op &= UINT64_C(31); 1045 op <<= 2; 1046 Value |= op; 1047 break; 1048 } 1049 case RISCV::C_FSD: 1050 case RISCV::C_SD: { 1051 // op: rs2 1052 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1053 op &= UINT64_C(7); 1054 op <<= 2; 1055 Value |= op; 1056 // op: rs1 1057 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1058 op &= UINT64_C(7); 1059 op <<= 7; 1060 Value |= op; 1061 // op: imm 1062 op = getImmOpValue(MI, 2, Fixups, STI); 1063 Value |= (op & UINT64_C(56)) << 7; 1064 Value |= (op & UINT64_C(192)) >> 1; 1065 break; 1066 } 1067 case RISCV::C_FSW: 1068 case RISCV::C_SW: { 1069 // op: rs2 1070 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1071 op &= UINT64_C(7); 1072 op <<= 2; 1073 Value |= op; 1074 // op: rs1 1075 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1076 op &= UINT64_C(7); 1077 op <<= 7; 1078 Value |= op; 1079 // op: imm 1080 op = getImmOpValue(MI, 2, Fixups, STI); 1081 Value |= (op & UINT64_C(56)) << 7; 1082 Value |= (op & UINT64_C(4)) << 4; 1083 Value |= (op & UINT64_C(64)) >> 1; 1084 break; 1085 } 1086 case RISCV::SFENCE_VMA: { 1087 // op: rs2 1088 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1089 op &= UINT64_C(31); 1090 op <<= 20; 1091 Value |= op; 1092 // op: rs1 1093 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1094 op &= UINT64_C(31); 1095 op <<= 15; 1096 Value |= op; 1097 break; 1098 } 1099 case RISCV::C_MV_HINT: { 1100 // op: rs2 1101 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1102 op &= UINT64_C(31); 1103 op <<= 2; 1104 Value |= op; 1105 break; 1106 } 1107 case RISCV::FADD_D: 1108 case RISCV::FADD_S: 1109 case RISCV::FDIV_D: 1110 case RISCV::FDIV_S: 1111 case RISCV::FMUL_D: 1112 case RISCV::FMUL_S: 1113 case RISCV::FSUB_D: 1114 case RISCV::FSUB_S: { 1115 // op: rs2 1116 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 1117 op &= UINT64_C(31); 1118 op <<= 20; 1119 Value |= op; 1120 // op: rs1 1121 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1122 op &= UINT64_C(31); 1123 op <<= 15; 1124 Value |= op; 1125 // op: funct3 1126 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 1127 op &= UINT64_C(7); 1128 op <<= 12; 1129 Value |= op; 1130 // op: rd 1131 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1132 op &= UINT64_C(31); 1133 op <<= 7; 1134 Value |= op; 1135 break; 1136 } 1137 case RISCV::ADD: 1138 case RISCV::ADDW: 1139 case RISCV::AMOADD_D: 1140 case RISCV::AMOADD_D_AQ: 1141 case RISCV::AMOADD_D_AQ_RL: 1142 case RISCV::AMOADD_D_RL: 1143 case RISCV::AMOADD_W: 1144 case RISCV::AMOADD_W_AQ: 1145 case RISCV::AMOADD_W_AQ_RL: 1146 case RISCV::AMOADD_W_RL: 1147 case RISCV::AMOAND_D: 1148 case RISCV::AMOAND_D_AQ: 1149 case RISCV::AMOAND_D_AQ_RL: 1150 case RISCV::AMOAND_D_RL: 1151 case RISCV::AMOAND_W: 1152 case RISCV::AMOAND_W_AQ: 1153 case RISCV::AMOAND_W_AQ_RL: 1154 case RISCV::AMOAND_W_RL: 1155 case RISCV::AMOMAXU_D: 1156 case RISCV::AMOMAXU_D_AQ: 1157 case RISCV::AMOMAXU_D_AQ_RL: 1158 case RISCV::AMOMAXU_D_RL: 1159 case RISCV::AMOMAXU_W: 1160 case RISCV::AMOMAXU_W_AQ: 1161 case RISCV::AMOMAXU_W_AQ_RL: 1162 case RISCV::AMOMAXU_W_RL: 1163 case RISCV::AMOMAX_D: 1164 case RISCV::AMOMAX_D_AQ: 1165 case RISCV::AMOMAX_D_AQ_RL: 1166 case RISCV::AMOMAX_D_RL: 1167 case RISCV::AMOMAX_W: 1168 case RISCV::AMOMAX_W_AQ: 1169 case RISCV::AMOMAX_W_AQ_RL: 1170 case RISCV::AMOMAX_W_RL: 1171 case RISCV::AMOMINU_D: 1172 case RISCV::AMOMINU_D_AQ: 1173 case RISCV::AMOMINU_D_AQ_RL: 1174 case RISCV::AMOMINU_D_RL: 1175 case RISCV::AMOMINU_W: 1176 case RISCV::AMOMINU_W_AQ: 1177 case RISCV::AMOMINU_W_AQ_RL: 1178 case RISCV::AMOMINU_W_RL: 1179 case RISCV::AMOMIN_D: 1180 case RISCV::AMOMIN_D_AQ: 1181 case RISCV::AMOMIN_D_AQ_RL: 1182 case RISCV::AMOMIN_D_RL: 1183 case RISCV::AMOMIN_W: 1184 case RISCV::AMOMIN_W_AQ: 1185 case RISCV::AMOMIN_W_AQ_RL: 1186 case RISCV::AMOMIN_W_RL: 1187 case RISCV::AMOOR_D: 1188 case RISCV::AMOOR_D_AQ: 1189 case RISCV::AMOOR_D_AQ_RL: 1190 case RISCV::AMOOR_D_RL: 1191 case RISCV::AMOOR_W: 1192 case RISCV::AMOOR_W_AQ: 1193 case RISCV::AMOOR_W_AQ_RL: 1194 case RISCV::AMOOR_W_RL: 1195 case RISCV::AMOSWAP_D: 1196 case RISCV::AMOSWAP_D_AQ: 1197 case RISCV::AMOSWAP_D_AQ_RL: 1198 case RISCV::AMOSWAP_D_RL: 1199 case RISCV::AMOSWAP_W: 1200 case RISCV::AMOSWAP_W_AQ: 1201 case RISCV::AMOSWAP_W_AQ_RL: 1202 case RISCV::AMOSWAP_W_RL: 1203 case RISCV::AMOXOR_D: 1204 case RISCV::AMOXOR_D_AQ: 1205 case RISCV::AMOXOR_D_AQ_RL: 1206 case RISCV::AMOXOR_D_RL: 1207 case RISCV::AMOXOR_W: 1208 case RISCV::AMOXOR_W_AQ: 1209 case RISCV::AMOXOR_W_AQ_RL: 1210 case RISCV::AMOXOR_W_RL: 1211 case RISCV::AND: 1212 case RISCV::DIV: 1213 case RISCV::DIVU: 1214 case RISCV::DIVUW: 1215 case RISCV::DIVW: 1216 case RISCV::FEQ_D: 1217 case RISCV::FEQ_S: 1218 case RISCV::FLE_D: 1219 case RISCV::FLE_S: 1220 case RISCV::FLT_D: 1221 case RISCV::FLT_S: 1222 case RISCV::FMAX_D: 1223 case RISCV::FMAX_S: 1224 case RISCV::FMIN_D: 1225 case RISCV::FMIN_S: 1226 case RISCV::FSGNJN_D: 1227 case RISCV::FSGNJN_S: 1228 case RISCV::FSGNJX_D: 1229 case RISCV::FSGNJX_S: 1230 case RISCV::FSGNJ_D: 1231 case RISCV::FSGNJ_S: 1232 case RISCV::MUL: 1233 case RISCV::MULH: 1234 case RISCV::MULHSU: 1235 case RISCV::MULHU: 1236 case RISCV::MULW: 1237 case RISCV::OR: 1238 case RISCV::REM: 1239 case RISCV::REMU: 1240 case RISCV::REMUW: 1241 case RISCV::REMW: 1242 case RISCV::SC_D: 1243 case RISCV::SC_D_AQ: 1244 case RISCV::SC_D_AQ_RL: 1245 case RISCV::SC_D_RL: 1246 case RISCV::SC_W: 1247 case RISCV::SC_W_AQ: 1248 case RISCV::SC_W_AQ_RL: 1249 case RISCV::SC_W_RL: 1250 case RISCV::SLL: 1251 case RISCV::SLLW: 1252 case RISCV::SLT: 1253 case RISCV::SLTU: 1254 case RISCV::SRA: 1255 case RISCV::SRAW: 1256 case RISCV::SRL: 1257 case RISCV::SRLW: 1258 case RISCV::SUB: 1259 case RISCV::SUBW: 1260 case RISCV::XOR: { 1261 // op: rs2 1262 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 1263 op &= UINT64_C(31); 1264 op <<= 20; 1265 Value |= op; 1266 // op: rs1 1267 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1268 op &= UINT64_C(31); 1269 op <<= 15; 1270 Value |= op; 1271 // op: rd 1272 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1273 op &= UINT64_C(31); 1274 op <<= 7; 1275 Value |= op; 1276 break; 1277 } 1278 case RISCV::C_ADD_HINT: { 1279 // op: rs2 1280 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 1281 op &= UINT64_C(31); 1282 op <<= 2; 1283 Value |= op; 1284 break; 1285 } 1286 case RISCV::C_ADDW: 1287 case RISCV::C_AND: 1288 case RISCV::C_OR: 1289 case RISCV::C_SUB: 1290 case RISCV::C_SUBW: 1291 case RISCV::C_XOR: { 1292 // op: rs2 1293 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 1294 op &= UINT64_C(7); 1295 op <<= 2; 1296 Value |= op; 1297 // op: rd 1298 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1299 op &= UINT64_C(7); 1300 op <<= 7; 1301 Value |= op; 1302 break; 1303 } 1304 case RISCV::FMADD_D: 1305 case RISCV::FMADD_S: 1306 case RISCV::FMSUB_D: 1307 case RISCV::FMSUB_S: 1308 case RISCV::FNMADD_D: 1309 case RISCV::FNMADD_S: 1310 case RISCV::FNMSUB_D: 1311 case RISCV::FNMSUB_S: { 1312 // op: rs3 1313 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); 1314 op &= UINT64_C(31); 1315 op <<= 27; 1316 Value |= op; 1317 // op: rs2 1318 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 1319 op &= UINT64_C(31); 1320 op <<= 20; 1321 Value |= op; 1322 // op: rs1 1323 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1324 op &= UINT64_C(31); 1325 op <<= 15; 1326 Value |= op; 1327 // op: funct3 1328 op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); 1329 op &= UINT64_C(7); 1330 op <<= 12; 1331 Value |= op; 1332 // op: rd 1333 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1334 op &= UINT64_C(31); 1335 op <<= 7; 1336 Value |= op; 1337 break; 1338 } 1339 case RISCV::SLLIW: 1340 case RISCV::SRAIW: 1341 case RISCV::SRLIW: { 1342 // op: shamt 1343 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 1344 op &= UINT64_C(31); 1345 op <<= 20; 1346 Value |= op; 1347 // op: rs1 1348 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1349 op &= UINT64_C(31); 1350 op <<= 15; 1351 Value |= op; 1352 // op: rd 1353 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1354 op &= UINT64_C(31); 1355 op <<= 7; 1356 Value |= op; 1357 break; 1358 } 1359 case RISCV::SLLI: 1360 case RISCV::SRAI: 1361 case RISCV::SRLI: { 1362 // op: shamt 1363 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); 1364 op &= UINT64_C(63); 1365 op <<= 20; 1366 Value |= op; 1367 // op: rs1 1368 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); 1369 op &= UINT64_C(31); 1370 op <<= 15; 1371 Value |= op; 1372 // op: rd 1373 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); 1374 op &= UINT64_C(31); 1375 op <<= 7; 1376 Value |= op; 1377 break; 1378 } 1379 default: 1380 std::string msg; 1381 raw_string_ostream Msg(msg); 1382 Msg << "Not supported instr: " << MI; 1383 report_fatal_error(Msg.str()); 1384 } 1385 return Value; 1386} 1387 1388#ifdef ENABLE_INSTR_PREDICATE_VERIFIER 1389#undef ENABLE_INSTR_PREDICATE_VERIFIER 1390#include <sstream> 1391 1392// Bits for subtarget features that participate in instruction matching. 1393enum SubtargetFeatureBits : uint8_t { 1394 Feature_HasStdExtMBit = 5, 1395 Feature_HasStdExtABit = 1, 1396 Feature_HasStdExtFBit = 4, 1397 Feature_HasStdExtDBit = 3, 1398 Feature_HasStdExtCBit = 2, 1399 Feature_HasRVCHintsBit = 0, 1400 Feature_IsRV64Bit = 8, 1401 Feature_IsRV32Bit = 6, 1402 Feature_IsRV32EBit = 7, 1403}; 1404 1405#ifndef NDEBUG 1406static const char *SubtargetFeatureNames[] = { 1407 "Feature_HasRVCHints", 1408 "Feature_HasStdExtA", 1409 "Feature_HasStdExtC", 1410 "Feature_HasStdExtD", 1411 "Feature_HasStdExtF", 1412 "Feature_HasStdExtM", 1413 "Feature_IsRV32", 1414 "Feature_IsRV32E", 1415 "Feature_IsRV64", 1416 nullptr 1417}; 1418 1419#endif // NDEBUG 1420FeatureBitset RISCVMCCodeEmitter:: 1421computeAvailableFeatures(const FeatureBitset& FB) const { 1422 FeatureBitset Features; 1423 if ((FB[RISCV::FeatureStdExtM])) 1424 Features.set(Feature_HasStdExtMBit); 1425 if ((FB[RISCV::FeatureStdExtA])) 1426 Features.set(Feature_HasStdExtABit); 1427 if ((FB[RISCV::FeatureStdExtF])) 1428 Features.set(Feature_HasStdExtFBit); 1429 if ((FB[RISCV::FeatureStdExtD])) 1430 Features.set(Feature_HasStdExtDBit); 1431 if ((FB[RISCV::FeatureStdExtC])) 1432 Features.set(Feature_HasStdExtCBit); 1433 if ((FB[RISCV::FeatureRVCHints])) 1434 Features.set(Feature_HasRVCHintsBit); 1435 if ((FB[RISCV::Feature64Bit])) 1436 Features.set(Feature_IsRV64Bit); 1437 if ((!FB[RISCV::Feature64Bit])) 1438 Features.set(Feature_IsRV32Bit); 1439 if ((FB[RISCV::FeatureRV32E])) 1440 Features.set(Feature_IsRV32EBit); 1441 return Features; 1442} 1443 1444#ifndef NDEBUG 1445// Feature bitsets. 1446enum : uint8_t { 1447 CEFBS_None, 1448 CEFBS_HasStdExtA, 1449 CEFBS_HasStdExtC, 1450 CEFBS_HasStdExtD, 1451 CEFBS_HasStdExtF, 1452 CEFBS_HasStdExtM, 1453 CEFBS_IsRV32, 1454 CEFBS_IsRV64, 1455 CEFBS_HasStdExtA_IsRV64, 1456 CEFBS_HasStdExtC_HasRVCHints, 1457 CEFBS_HasStdExtC_HasStdExtD, 1458 CEFBS_HasStdExtC_IsRV32, 1459 CEFBS_HasStdExtC_IsRV64, 1460 CEFBS_HasStdExtD_IsRV64, 1461 CEFBS_HasStdExtF_IsRV64, 1462 CEFBS_HasStdExtM_IsRV64, 1463 CEFBS_HasStdExtC_HasStdExtF_IsRV32, 1464}; 1465 1466static constexpr FeatureBitset FeatureBitsets[] = { 1467 {}, // CEFBS_None 1468 {Feature_HasStdExtABit, }, 1469 {Feature_HasStdExtCBit, }, 1470 {Feature_HasStdExtDBit, }, 1471 {Feature_HasStdExtFBit, }, 1472 {Feature_HasStdExtMBit, }, 1473 {Feature_IsRV32Bit, }, 1474 {Feature_IsRV64Bit, }, 1475 {Feature_HasStdExtABit, Feature_IsRV64Bit, }, 1476 {Feature_HasStdExtCBit, Feature_HasRVCHintsBit, }, 1477 {Feature_HasStdExtCBit, Feature_HasStdExtDBit, }, 1478 {Feature_HasStdExtCBit, Feature_IsRV32Bit, }, 1479 {Feature_HasStdExtCBit, Feature_IsRV64Bit, }, 1480 {Feature_HasStdExtDBit, Feature_IsRV64Bit, }, 1481 {Feature_HasStdExtFBit, Feature_IsRV64Bit, }, 1482 {Feature_HasStdExtMBit, Feature_IsRV64Bit, }, 1483 {Feature_HasStdExtCBit, Feature_HasStdExtFBit, Feature_IsRV32Bit, }, 1484}; 1485#endif // NDEBUG 1486 1487void RISCVMCCodeEmitter::verifyInstructionPredicates( 1488 const MCInst &Inst, const FeatureBitset &AvailableFeatures) const { 1489#ifndef NDEBUG 1490 static uint8_t RequiredFeaturesRefs[] = { 1491 CEFBS_None, // PHI = 0 1492 CEFBS_None, // INLINEASM = 1 1493 CEFBS_None, // INLINEASM_BR = 2 1494 CEFBS_None, // CFI_INSTRUCTION = 3 1495 CEFBS_None, // EH_LABEL = 4 1496 CEFBS_None, // GC_LABEL = 5 1497 CEFBS_None, // ANNOTATION_LABEL = 6 1498 CEFBS_None, // KILL = 7 1499 CEFBS_None, // EXTRACT_SUBREG = 8 1500 CEFBS_None, // INSERT_SUBREG = 9 1501 CEFBS_None, // IMPLICIT_DEF = 10 1502 CEFBS_None, // SUBREG_TO_REG = 11 1503 CEFBS_None, // COPY_TO_REGCLASS = 12 1504 CEFBS_None, // DBG_VALUE = 13 1505 CEFBS_None, // DBG_LABEL = 14 1506 CEFBS_None, // REG_SEQUENCE = 15 1507 CEFBS_None, // COPY = 16 1508 CEFBS_None, // BUNDLE = 17 1509 CEFBS_None, // LIFETIME_START = 18 1510 CEFBS_None, // LIFETIME_END = 19 1511 CEFBS_None, // STACKMAP = 20 1512 CEFBS_None, // FENTRY_CALL = 21 1513 CEFBS_None, // PATCHPOINT = 22 1514 CEFBS_None, // LOAD_STACK_GUARD = 23 1515 CEFBS_None, // STATEPOINT = 24 1516 CEFBS_None, // LOCAL_ESCAPE = 25 1517 CEFBS_None, // FAULTING_OP = 26 1518 CEFBS_None, // PATCHABLE_OP = 27 1519 CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 28 1520 CEFBS_None, // PATCHABLE_RET = 29 1521 CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 30 1522 CEFBS_None, // PATCHABLE_TAIL_CALL = 31 1523 CEFBS_None, // PATCHABLE_EVENT_CALL = 32 1524 CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 33 1525 CEFBS_None, // ICALL_BRANCH_FUNNEL = 34 1526 CEFBS_None, // G_ADD = 35 1527 CEFBS_None, // G_SUB = 36 1528 CEFBS_None, // G_MUL = 37 1529 CEFBS_None, // G_SDIV = 38 1530 CEFBS_None, // G_UDIV = 39 1531 CEFBS_None, // G_SREM = 40 1532 CEFBS_None, // G_UREM = 41 1533 CEFBS_None, // G_AND = 42 1534 CEFBS_None, // G_OR = 43 1535 CEFBS_None, // G_XOR = 44 1536 CEFBS_None, // G_IMPLICIT_DEF = 45 1537 CEFBS_None, // G_PHI = 46 1538 CEFBS_None, // G_FRAME_INDEX = 47 1539 CEFBS_None, // G_GLOBAL_VALUE = 48 1540 CEFBS_None, // G_EXTRACT = 49 1541 CEFBS_None, // G_UNMERGE_VALUES = 50 1542 CEFBS_None, // G_INSERT = 51 1543 CEFBS_None, // G_MERGE_VALUES = 52 1544 CEFBS_None, // G_BUILD_VECTOR = 53 1545 CEFBS_None, // G_BUILD_VECTOR_TRUNC = 54 1546 CEFBS_None, // G_CONCAT_VECTORS = 55 1547 CEFBS_None, // G_PTRTOINT = 56 1548 CEFBS_None, // G_INTTOPTR = 57 1549 CEFBS_None, // G_BITCAST = 58 1550 CEFBS_None, // G_INTRINSIC_TRUNC = 59 1551 CEFBS_None, // G_INTRINSIC_ROUND = 60 1552 CEFBS_None, // G_READCYCLECOUNTER = 61 1553 CEFBS_None, // G_LOAD = 62 1554 CEFBS_None, // G_SEXTLOAD = 63 1555 CEFBS_None, // G_ZEXTLOAD = 64 1556 CEFBS_None, // G_INDEXED_LOAD = 65 1557 CEFBS_None, // G_INDEXED_SEXTLOAD = 66 1558 CEFBS_None, // G_INDEXED_ZEXTLOAD = 67 1559 CEFBS_None, // G_STORE = 68 1560 CEFBS_None, // G_INDEXED_STORE = 69 1561 CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70 1562 CEFBS_None, // G_ATOMIC_CMPXCHG = 71 1563 CEFBS_None, // G_ATOMICRMW_XCHG = 72 1564 CEFBS_None, // G_ATOMICRMW_ADD = 73 1565 CEFBS_None, // G_ATOMICRMW_SUB = 74 1566 CEFBS_None, // G_ATOMICRMW_AND = 75 1567 CEFBS_None, // G_ATOMICRMW_NAND = 76 1568 CEFBS_None, // G_ATOMICRMW_OR = 77 1569 CEFBS_None, // G_ATOMICRMW_XOR = 78 1570 CEFBS_None, // G_ATOMICRMW_MAX = 79 1571 CEFBS_None, // G_ATOMICRMW_MIN = 80 1572 CEFBS_None, // G_ATOMICRMW_UMAX = 81 1573 CEFBS_None, // G_ATOMICRMW_UMIN = 82 1574 CEFBS_None, // G_ATOMICRMW_FADD = 83 1575 CEFBS_None, // G_ATOMICRMW_FSUB = 84 1576 CEFBS_None, // G_FENCE = 85 1577 CEFBS_None, // G_BRCOND = 86 1578 CEFBS_None, // G_BRINDIRECT = 87 1579 CEFBS_None, // G_INTRINSIC = 88 1580 CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 89 1581 CEFBS_None, // G_ANYEXT = 90 1582 CEFBS_None, // G_TRUNC = 91 1583 CEFBS_None, // G_CONSTANT = 92 1584 CEFBS_None, // G_FCONSTANT = 93 1585 CEFBS_None, // G_VASTART = 94 1586 CEFBS_None, // G_VAARG = 95 1587 CEFBS_None, // G_SEXT = 96 1588 CEFBS_None, // G_SEXT_INREG = 97 1589 CEFBS_None, // G_ZEXT = 98 1590 CEFBS_None, // G_SHL = 99 1591 CEFBS_None, // G_LSHR = 100 1592 CEFBS_None, // G_ASHR = 101 1593 CEFBS_None, // G_ICMP = 102 1594 CEFBS_None, // G_FCMP = 103 1595 CEFBS_None, // G_SELECT = 104 1596 CEFBS_None, // G_UADDO = 105 1597 CEFBS_None, // G_UADDE = 106 1598 CEFBS_None, // G_USUBO = 107 1599 CEFBS_None, // G_USUBE = 108 1600 CEFBS_None, // G_SADDO = 109 1601 CEFBS_None, // G_SADDE = 110 1602 CEFBS_None, // G_SSUBO = 111 1603 CEFBS_None, // G_SSUBE = 112 1604 CEFBS_None, // G_UMULO = 113 1605 CEFBS_None, // G_SMULO = 114 1606 CEFBS_None, // G_UMULH = 115 1607 CEFBS_None, // G_SMULH = 116 1608 CEFBS_None, // G_FADD = 117 1609 CEFBS_None, // G_FSUB = 118 1610 CEFBS_None, // G_FMUL = 119 1611 CEFBS_None, // G_FMA = 120 1612 CEFBS_None, // G_FMAD = 121 1613 CEFBS_None, // G_FDIV = 122 1614 CEFBS_None, // G_FREM = 123 1615 CEFBS_None, // G_FPOW = 124 1616 CEFBS_None, // G_FEXP = 125 1617 CEFBS_None, // G_FEXP2 = 126 1618 CEFBS_None, // G_FLOG = 127 1619 CEFBS_None, // G_FLOG2 = 128 1620 CEFBS_None, // G_FLOG10 = 129 1621 CEFBS_None, // G_FNEG = 130 1622 CEFBS_None, // G_FPEXT = 131 1623 CEFBS_None, // G_FPTRUNC = 132 1624 CEFBS_None, // G_FPTOSI = 133 1625 CEFBS_None, // G_FPTOUI = 134 1626 CEFBS_None, // G_SITOFP = 135 1627 CEFBS_None, // G_UITOFP = 136 1628 CEFBS_None, // G_FABS = 137 1629 CEFBS_None, // G_FCOPYSIGN = 138 1630 CEFBS_None, // G_FCANONICALIZE = 139 1631 CEFBS_None, // G_FMINNUM = 140 1632 CEFBS_None, // G_FMAXNUM = 141 1633 CEFBS_None, // G_FMINNUM_IEEE = 142 1634 CEFBS_None, // G_FMAXNUM_IEEE = 143 1635 CEFBS_None, // G_FMINIMUM = 144 1636 CEFBS_None, // G_FMAXIMUM = 145 1637 CEFBS_None, // G_PTR_ADD = 146 1638 CEFBS_None, // G_PTR_MASK = 147 1639 CEFBS_None, // G_SMIN = 148 1640 CEFBS_None, // G_SMAX = 149 1641 CEFBS_None, // G_UMIN = 150 1642 CEFBS_None, // G_UMAX = 151 1643 CEFBS_None, // G_BR = 152 1644 CEFBS_None, // G_BRJT = 153 1645 CEFBS_None, // G_INSERT_VECTOR_ELT = 154 1646 CEFBS_None, // G_EXTRACT_VECTOR_ELT = 155 1647 CEFBS_None, // G_SHUFFLE_VECTOR = 156 1648 CEFBS_None, // G_CTTZ = 157 1649 CEFBS_None, // G_CTTZ_ZERO_UNDEF = 158 1650 CEFBS_None, // G_CTLZ = 159 1651 CEFBS_None, // G_CTLZ_ZERO_UNDEF = 160 1652 CEFBS_None, // G_CTPOP = 161 1653 CEFBS_None, // G_BSWAP = 162 1654 CEFBS_None, // G_BITREVERSE = 163 1655 CEFBS_None, // G_FCEIL = 164 1656 CEFBS_None, // G_FCOS = 165 1657 CEFBS_None, // G_FSIN = 166 1658 CEFBS_None, // G_FSQRT = 167 1659 CEFBS_None, // G_FFLOOR = 168 1660 CEFBS_None, // G_FRINT = 169 1661 CEFBS_None, // G_FNEARBYINT = 170 1662 CEFBS_None, // G_ADDRSPACE_CAST = 171 1663 CEFBS_None, // G_BLOCK_ADDR = 172 1664 CEFBS_None, // G_JUMP_TABLE = 173 1665 CEFBS_None, // G_DYN_STACKALLOC = 174 1666 CEFBS_None, // G_READ_REGISTER = 175 1667 CEFBS_None, // G_WRITE_REGISTER = 176 1668 CEFBS_None, // ADJCALLSTACKDOWN = 177 1669 CEFBS_None, // ADJCALLSTACKUP = 178 1670 CEFBS_HasStdExtD, // BuildPairF64Pseudo = 179 1671 CEFBS_None, // PseudoAddTPRel = 180 1672 CEFBS_HasStdExtA, // PseudoAtomicLoadNand32 = 181 1673 CEFBS_HasStdExtA_IsRV64, // PseudoAtomicLoadNand64 = 182 1674 CEFBS_None, // PseudoBR = 183 1675 CEFBS_None, // PseudoBRIND = 184 1676 CEFBS_None, // PseudoCALL = 185 1677 CEFBS_None, // PseudoCALLIndirect = 186 1678 CEFBS_None, // PseudoCALLReg = 187 1679 CEFBS_HasStdExtA, // PseudoCmpXchg32 = 188 1680 CEFBS_HasStdExtA_IsRV64, // PseudoCmpXchg64 = 189 1681 CEFBS_HasStdExtD, // PseudoFLD = 190 1682 CEFBS_HasStdExtF, // PseudoFLW = 191 1683 CEFBS_HasStdExtD, // PseudoFSD = 192 1684 CEFBS_HasStdExtF, // PseudoFSW = 193 1685 CEFBS_None, // PseudoLA = 194 1686 CEFBS_None, // PseudoLA_TLS_GD = 195 1687 CEFBS_None, // PseudoLA_TLS_IE = 196 1688 CEFBS_None, // PseudoLB = 197 1689 CEFBS_None, // PseudoLBU = 198 1690 CEFBS_IsRV64, // PseudoLD = 199 1691 CEFBS_None, // PseudoLH = 200 1692 CEFBS_None, // PseudoLHU = 201 1693 CEFBS_None, // PseudoLI = 202 1694 CEFBS_None, // PseudoLLA = 203 1695 CEFBS_None, // PseudoLW = 204 1696 CEFBS_IsRV64, // PseudoLWU = 205 1697 CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadAdd32 = 206 1698 CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadMax32 = 207 1699 CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadMin32 = 208 1700 CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadNand32 = 209 1701 CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadSub32 = 210 1702 CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadUMax32 = 211 1703 CEFBS_HasStdExtA, // PseudoMaskedAtomicLoadUMin32 = 212 1704 CEFBS_HasStdExtA, // PseudoMaskedAtomicSwap32 = 213 1705 CEFBS_HasStdExtA, // PseudoMaskedCmpXchg32 = 214 1706 CEFBS_None, // PseudoRET = 215 1707 CEFBS_None, // PseudoSB = 216 1708 CEFBS_IsRV64, // PseudoSD = 217 1709 CEFBS_None, // PseudoSH = 218 1710 CEFBS_None, // PseudoSW = 219 1711 CEFBS_None, // PseudoTAIL = 220 1712 CEFBS_None, // PseudoTAILIndirect = 221 1713 CEFBS_IsRV32, // ReadCycleWide = 222 1714 CEFBS_HasStdExtF, // Select_FPR32_Using_CC_GPR = 223 1715 CEFBS_HasStdExtD, // Select_FPR64_Using_CC_GPR = 224 1716 CEFBS_None, // Select_GPR_Using_CC_GPR = 225 1717 CEFBS_HasStdExtD, // SplitF64Pseudo = 226 1718 CEFBS_None, // ADD = 227 1719 CEFBS_None, // ADDI = 228 1720 CEFBS_IsRV64, // ADDIW = 229 1721 CEFBS_IsRV64, // ADDW = 230 1722 CEFBS_HasStdExtA_IsRV64, // AMOADD_D = 231 1723 CEFBS_HasStdExtA_IsRV64, // AMOADD_D_AQ = 232 1724 CEFBS_HasStdExtA_IsRV64, // AMOADD_D_AQ_RL = 233 1725 CEFBS_HasStdExtA_IsRV64, // AMOADD_D_RL = 234 1726 CEFBS_HasStdExtA, // AMOADD_W = 235 1727 CEFBS_HasStdExtA, // AMOADD_W_AQ = 236 1728 CEFBS_HasStdExtA, // AMOADD_W_AQ_RL = 237 1729 CEFBS_HasStdExtA, // AMOADD_W_RL = 238 1730 CEFBS_HasStdExtA_IsRV64, // AMOAND_D = 239 1731 CEFBS_HasStdExtA_IsRV64, // AMOAND_D_AQ = 240 1732 CEFBS_HasStdExtA_IsRV64, // AMOAND_D_AQ_RL = 241 1733 CEFBS_HasStdExtA_IsRV64, // AMOAND_D_RL = 242 1734 CEFBS_HasStdExtA, // AMOAND_W = 243 1735 CEFBS_HasStdExtA, // AMOAND_W_AQ = 244 1736 CEFBS_HasStdExtA, // AMOAND_W_AQ_RL = 245 1737 CEFBS_HasStdExtA, // AMOAND_W_RL = 246 1738 CEFBS_HasStdExtA_IsRV64, // AMOMAXU_D = 247 1739 CEFBS_HasStdExtA_IsRV64, // AMOMAXU_D_AQ = 248 1740 CEFBS_HasStdExtA_IsRV64, // AMOMAXU_D_AQ_RL = 249 1741 CEFBS_HasStdExtA_IsRV64, // AMOMAXU_D_RL = 250 1742 CEFBS_HasStdExtA, // AMOMAXU_W = 251 1743 CEFBS_HasStdExtA, // AMOMAXU_W_AQ = 252 1744 CEFBS_HasStdExtA, // AMOMAXU_W_AQ_RL = 253 1745 CEFBS_HasStdExtA, // AMOMAXU_W_RL = 254 1746 CEFBS_HasStdExtA_IsRV64, // AMOMAX_D = 255 1747 CEFBS_HasStdExtA_IsRV64, // AMOMAX_D_AQ = 256 1748 CEFBS_HasStdExtA_IsRV64, // AMOMAX_D_AQ_RL = 257 1749 CEFBS_HasStdExtA_IsRV64, // AMOMAX_D_RL = 258 1750 CEFBS_HasStdExtA, // AMOMAX_W = 259 1751 CEFBS_HasStdExtA, // AMOMAX_W_AQ = 260 1752 CEFBS_HasStdExtA, // AMOMAX_W_AQ_RL = 261 1753 CEFBS_HasStdExtA, // AMOMAX_W_RL = 262 1754 CEFBS_HasStdExtA_IsRV64, // AMOMINU_D = 263 1755 CEFBS_HasStdExtA_IsRV64, // AMOMINU_D_AQ = 264 1756 CEFBS_HasStdExtA_IsRV64, // AMOMINU_D_AQ_RL = 265 1757 CEFBS_HasStdExtA_IsRV64, // AMOMINU_D_RL = 266 1758 CEFBS_HasStdExtA, // AMOMINU_W = 267 1759 CEFBS_HasStdExtA, // AMOMINU_W_AQ = 268 1760 CEFBS_HasStdExtA, // AMOMINU_W_AQ_RL = 269 1761 CEFBS_HasStdExtA, // AMOMINU_W_RL = 270 1762 CEFBS_HasStdExtA_IsRV64, // AMOMIN_D = 271 1763 CEFBS_HasStdExtA_IsRV64, // AMOMIN_D_AQ = 272 1764 CEFBS_HasStdExtA_IsRV64, // AMOMIN_D_AQ_RL = 273 1765 CEFBS_HasStdExtA_IsRV64, // AMOMIN_D_RL = 274 1766 CEFBS_HasStdExtA, // AMOMIN_W = 275 1767 CEFBS_HasStdExtA, // AMOMIN_W_AQ = 276 1768 CEFBS_HasStdExtA, // AMOMIN_W_AQ_RL = 277 1769 CEFBS_HasStdExtA, // AMOMIN_W_RL = 278 1770 CEFBS_HasStdExtA_IsRV64, // AMOOR_D = 279 1771 CEFBS_HasStdExtA_IsRV64, // AMOOR_D_AQ = 280 1772 CEFBS_HasStdExtA_IsRV64, // AMOOR_D_AQ_RL = 281 1773 CEFBS_HasStdExtA_IsRV64, // AMOOR_D_RL = 282 1774 CEFBS_HasStdExtA, // AMOOR_W = 283 1775 CEFBS_HasStdExtA, // AMOOR_W_AQ = 284 1776 CEFBS_HasStdExtA, // AMOOR_W_AQ_RL = 285 1777 CEFBS_HasStdExtA, // AMOOR_W_RL = 286 1778 CEFBS_HasStdExtA_IsRV64, // AMOSWAP_D = 287 1779 CEFBS_HasStdExtA_IsRV64, // AMOSWAP_D_AQ = 288 1780 CEFBS_HasStdExtA_IsRV64, // AMOSWAP_D_AQ_RL = 289 1781 CEFBS_HasStdExtA_IsRV64, // AMOSWAP_D_RL = 290 1782 CEFBS_HasStdExtA, // AMOSWAP_W = 291 1783 CEFBS_HasStdExtA, // AMOSWAP_W_AQ = 292 1784 CEFBS_HasStdExtA, // AMOSWAP_W_AQ_RL = 293 1785 CEFBS_HasStdExtA, // AMOSWAP_W_RL = 294 1786 CEFBS_HasStdExtA_IsRV64, // AMOXOR_D = 295 1787 CEFBS_HasStdExtA_IsRV64, // AMOXOR_D_AQ = 296 1788 CEFBS_HasStdExtA_IsRV64, // AMOXOR_D_AQ_RL = 297 1789 CEFBS_HasStdExtA_IsRV64, // AMOXOR_D_RL = 298 1790 CEFBS_HasStdExtA, // AMOXOR_W = 299 1791 CEFBS_HasStdExtA, // AMOXOR_W_AQ = 300 1792 CEFBS_HasStdExtA, // AMOXOR_W_AQ_RL = 301 1793 CEFBS_HasStdExtA, // AMOXOR_W_RL = 302 1794 CEFBS_None, // AND = 303 1795 CEFBS_None, // ANDI = 304 1796 CEFBS_None, // AUIPC = 305 1797 CEFBS_None, // BEQ = 306 1798 CEFBS_None, // BGE = 307 1799 CEFBS_None, // BGEU = 308 1800 CEFBS_None, // BLT = 309 1801 CEFBS_None, // BLTU = 310 1802 CEFBS_None, // BNE = 311 1803 CEFBS_None, // CSRRC = 312 1804 CEFBS_None, // CSRRCI = 313 1805 CEFBS_None, // CSRRS = 314 1806 CEFBS_None, // CSRRSI = 315 1807 CEFBS_None, // CSRRW = 316 1808 CEFBS_None, // CSRRWI = 317 1809 CEFBS_HasStdExtC, // C_ADD = 318 1810 CEFBS_HasStdExtC, // C_ADDI = 319 1811 CEFBS_HasStdExtC, // C_ADDI16SP = 320 1812 CEFBS_HasStdExtC, // C_ADDI4SPN = 321 1813 CEFBS_HasStdExtC_IsRV64, // C_ADDIW = 322 1814 CEFBS_HasStdExtC_HasRVCHints, // C_ADDI_HINT_IMM_ZERO = 323 1815 CEFBS_HasStdExtC_HasRVCHints, // C_ADDI_HINT_X0 = 324 1816 CEFBS_HasStdExtC, // C_ADDI_NOP = 325 1817 CEFBS_HasStdExtC_IsRV64, // C_ADDW = 326 1818 CEFBS_HasStdExtC_HasRVCHints, // C_ADD_HINT = 327 1819 CEFBS_HasStdExtC, // C_AND = 328 1820 CEFBS_HasStdExtC, // C_ANDI = 329 1821 CEFBS_HasStdExtC, // C_BEQZ = 330 1822 CEFBS_HasStdExtC, // C_BNEZ = 331 1823 CEFBS_HasStdExtC, // C_EBREAK = 332 1824 CEFBS_HasStdExtC_HasStdExtD, // C_FLD = 333 1825 CEFBS_HasStdExtC_HasStdExtD, // C_FLDSP = 334 1826 CEFBS_HasStdExtC_HasStdExtF_IsRV32, // C_FLW = 335 1827 CEFBS_HasStdExtC_HasStdExtF_IsRV32, // C_FLWSP = 336 1828 CEFBS_HasStdExtC_HasStdExtD, // C_FSD = 337 1829 CEFBS_HasStdExtC_HasStdExtD, // C_FSDSP = 338 1830 CEFBS_HasStdExtC_HasStdExtF_IsRV32, // C_FSW = 339 1831 CEFBS_HasStdExtC_HasStdExtF_IsRV32, // C_FSWSP = 340 1832 CEFBS_HasStdExtC, // C_J = 341 1833 CEFBS_HasStdExtC_IsRV32, // C_JAL = 342 1834 CEFBS_HasStdExtC, // C_JALR = 343 1835 CEFBS_HasStdExtC, // C_JR = 344 1836 CEFBS_HasStdExtC_IsRV64, // C_LD = 345 1837 CEFBS_HasStdExtC_IsRV64, // C_LDSP = 346 1838 CEFBS_HasStdExtC, // C_LI = 347 1839 CEFBS_HasStdExtC_HasRVCHints, // C_LI_HINT = 348 1840 CEFBS_HasStdExtC, // C_LUI = 349 1841 CEFBS_HasStdExtC_HasRVCHints, // C_LUI_HINT = 350 1842 CEFBS_HasStdExtC, // C_LW = 351 1843 CEFBS_HasStdExtC, // C_LWSP = 352 1844 CEFBS_HasStdExtC, // C_MV = 353 1845 CEFBS_HasStdExtC_HasRVCHints, // C_MV_HINT = 354 1846 CEFBS_HasStdExtC, // C_NOP = 355 1847 CEFBS_HasStdExtC_HasRVCHints, // C_NOP_HINT = 356 1848 CEFBS_HasStdExtC, // C_OR = 357 1849 CEFBS_HasStdExtC_IsRV64, // C_SD = 358 1850 CEFBS_HasStdExtC_IsRV64, // C_SDSP = 359 1851 CEFBS_HasStdExtC, // C_SLLI = 360 1852 CEFBS_HasStdExtC_HasRVCHints, // C_SLLI64_HINT = 361 1853 CEFBS_HasStdExtC_HasRVCHints, // C_SLLI_HINT = 362 1854 CEFBS_HasStdExtC, // C_SRAI = 363 1855 CEFBS_HasStdExtC_HasRVCHints, // C_SRAI64_HINT = 364 1856 CEFBS_HasStdExtC, // C_SRLI = 365 1857 CEFBS_HasStdExtC_HasRVCHints, // C_SRLI64_HINT = 366 1858 CEFBS_HasStdExtC, // C_SUB = 367 1859 CEFBS_HasStdExtC_IsRV64, // C_SUBW = 368 1860 CEFBS_HasStdExtC, // C_SW = 369 1861 CEFBS_HasStdExtC, // C_SWSP = 370 1862 CEFBS_HasStdExtC, // C_UNIMP = 371 1863 CEFBS_HasStdExtC, // C_XOR = 372 1864 CEFBS_HasStdExtM, // DIV = 373 1865 CEFBS_HasStdExtM, // DIVU = 374 1866 CEFBS_HasStdExtM_IsRV64, // DIVUW = 375 1867 CEFBS_HasStdExtM_IsRV64, // DIVW = 376 1868 CEFBS_None, // EBREAK = 377 1869 CEFBS_None, // ECALL = 378 1870 CEFBS_HasStdExtD, // FADD_D = 379 1871 CEFBS_HasStdExtF, // FADD_S = 380 1872 CEFBS_HasStdExtD, // FCLASS_D = 381 1873 CEFBS_HasStdExtF, // FCLASS_S = 382 1874 CEFBS_HasStdExtD_IsRV64, // FCVT_D_L = 383 1875 CEFBS_HasStdExtD_IsRV64, // FCVT_D_LU = 384 1876 CEFBS_HasStdExtD, // FCVT_D_S = 385 1877 CEFBS_HasStdExtD, // FCVT_D_W = 386 1878 CEFBS_HasStdExtD, // FCVT_D_WU = 387 1879 CEFBS_HasStdExtD_IsRV64, // FCVT_LU_D = 388 1880 CEFBS_HasStdExtF_IsRV64, // FCVT_LU_S = 389 1881 CEFBS_HasStdExtD_IsRV64, // FCVT_L_D = 390 1882 CEFBS_HasStdExtF_IsRV64, // FCVT_L_S = 391 1883 CEFBS_HasStdExtD, // FCVT_S_D = 392 1884 CEFBS_HasStdExtF_IsRV64, // FCVT_S_L = 393 1885 CEFBS_HasStdExtF_IsRV64, // FCVT_S_LU = 394 1886 CEFBS_HasStdExtF, // FCVT_S_W = 395 1887 CEFBS_HasStdExtF, // FCVT_S_WU = 396 1888 CEFBS_HasStdExtD, // FCVT_WU_D = 397 1889 CEFBS_HasStdExtF, // FCVT_WU_S = 398 1890 CEFBS_HasStdExtD, // FCVT_W_D = 399 1891 CEFBS_HasStdExtF, // FCVT_W_S = 400 1892 CEFBS_HasStdExtD, // FDIV_D = 401 1893 CEFBS_HasStdExtF, // FDIV_S = 402 1894 CEFBS_None, // FENCE = 403 1895 CEFBS_None, // FENCE_I = 404 1896 CEFBS_None, // FENCE_TSO = 405 1897 CEFBS_HasStdExtD, // FEQ_D = 406 1898 CEFBS_HasStdExtF, // FEQ_S = 407 1899 CEFBS_HasStdExtD, // FLD = 408 1900 CEFBS_HasStdExtD, // FLE_D = 409 1901 CEFBS_HasStdExtF, // FLE_S = 410 1902 CEFBS_HasStdExtD, // FLT_D = 411 1903 CEFBS_HasStdExtF, // FLT_S = 412 1904 CEFBS_HasStdExtF, // FLW = 413 1905 CEFBS_HasStdExtD, // FMADD_D = 414 1906 CEFBS_HasStdExtF, // FMADD_S = 415 1907 CEFBS_HasStdExtD, // FMAX_D = 416 1908 CEFBS_HasStdExtF, // FMAX_S = 417 1909 CEFBS_HasStdExtD, // FMIN_D = 418 1910 CEFBS_HasStdExtF, // FMIN_S = 419 1911 CEFBS_HasStdExtD, // FMSUB_D = 420 1912 CEFBS_HasStdExtF, // FMSUB_S = 421 1913 CEFBS_HasStdExtD, // FMUL_D = 422 1914 CEFBS_HasStdExtF, // FMUL_S = 423 1915 CEFBS_HasStdExtD_IsRV64, // FMV_D_X = 424 1916 CEFBS_HasStdExtF, // FMV_W_X = 425 1917 CEFBS_HasStdExtD_IsRV64, // FMV_X_D = 426 1918 CEFBS_HasStdExtF, // FMV_X_W = 427 1919 CEFBS_HasStdExtD, // FNMADD_D = 428 1920 CEFBS_HasStdExtF, // FNMADD_S = 429 1921 CEFBS_HasStdExtD, // FNMSUB_D = 430 1922 CEFBS_HasStdExtF, // FNMSUB_S = 431 1923 CEFBS_HasStdExtD, // FSD = 432 1924 CEFBS_HasStdExtD, // FSGNJN_D = 433 1925 CEFBS_HasStdExtF, // FSGNJN_S = 434 1926 CEFBS_HasStdExtD, // FSGNJX_D = 435 1927 CEFBS_HasStdExtF, // FSGNJX_S = 436 1928 CEFBS_HasStdExtD, // FSGNJ_D = 437 1929 CEFBS_HasStdExtF, // FSGNJ_S = 438 1930 CEFBS_HasStdExtD, // FSQRT_D = 439 1931 CEFBS_HasStdExtF, // FSQRT_S = 440 1932 CEFBS_HasStdExtD, // FSUB_D = 441 1933 CEFBS_HasStdExtF, // FSUB_S = 442 1934 CEFBS_HasStdExtF, // FSW = 443 1935 CEFBS_None, // JAL = 444 1936 CEFBS_None, // JALR = 445 1937 CEFBS_None, // LB = 446 1938 CEFBS_None, // LBU = 447 1939 CEFBS_IsRV64, // LD = 448 1940 CEFBS_None, // LH = 449 1941 CEFBS_None, // LHU = 450 1942 CEFBS_HasStdExtA_IsRV64, // LR_D = 451 1943 CEFBS_HasStdExtA_IsRV64, // LR_D_AQ = 452 1944 CEFBS_HasStdExtA_IsRV64, // LR_D_AQ_RL = 453 1945 CEFBS_HasStdExtA_IsRV64, // LR_D_RL = 454 1946 CEFBS_HasStdExtA, // LR_W = 455 1947 CEFBS_HasStdExtA, // LR_W_AQ = 456 1948 CEFBS_HasStdExtA, // LR_W_AQ_RL = 457 1949 CEFBS_HasStdExtA, // LR_W_RL = 458 1950 CEFBS_None, // LUI = 459 1951 CEFBS_None, // LW = 460 1952 CEFBS_IsRV64, // LWU = 461 1953 CEFBS_None, // MRET = 462 1954 CEFBS_HasStdExtM, // MUL = 463 1955 CEFBS_HasStdExtM, // MULH = 464 1956 CEFBS_HasStdExtM, // MULHSU = 465 1957 CEFBS_HasStdExtM, // MULHU = 466 1958 CEFBS_HasStdExtM_IsRV64, // MULW = 467 1959 CEFBS_None, // OR = 468 1960 CEFBS_None, // ORI = 469 1961 CEFBS_HasStdExtM, // REM = 470 1962 CEFBS_HasStdExtM, // REMU = 471 1963 CEFBS_HasStdExtM_IsRV64, // REMUW = 472 1964 CEFBS_HasStdExtM_IsRV64, // REMW = 473 1965 CEFBS_None, // SB = 474 1966 CEFBS_HasStdExtA_IsRV64, // SC_D = 475 1967 CEFBS_HasStdExtA_IsRV64, // SC_D_AQ = 476 1968 CEFBS_HasStdExtA_IsRV64, // SC_D_AQ_RL = 477 1969 CEFBS_HasStdExtA_IsRV64, // SC_D_RL = 478 1970 CEFBS_HasStdExtA, // SC_W = 479 1971 CEFBS_HasStdExtA, // SC_W_AQ = 480 1972 CEFBS_HasStdExtA, // SC_W_AQ_RL = 481 1973 CEFBS_HasStdExtA, // SC_W_RL = 482 1974 CEFBS_IsRV64, // SD = 483 1975 CEFBS_None, // SFENCE_VMA = 484 1976 CEFBS_None, // SH = 485 1977 CEFBS_None, // SLL = 486 1978 CEFBS_None, // SLLI = 487 1979 CEFBS_IsRV64, // SLLIW = 488 1980 CEFBS_IsRV64, // SLLW = 489 1981 CEFBS_None, // SLT = 490 1982 CEFBS_None, // SLTI = 491 1983 CEFBS_None, // SLTIU = 492 1984 CEFBS_None, // SLTU = 493 1985 CEFBS_None, // SRA = 494 1986 CEFBS_None, // SRAI = 495 1987 CEFBS_IsRV64, // SRAIW = 496 1988 CEFBS_IsRV64, // SRAW = 497 1989 CEFBS_None, // SRET = 498 1990 CEFBS_None, // SRL = 499 1991 CEFBS_None, // SRLI = 500 1992 CEFBS_IsRV64, // SRLIW = 501 1993 CEFBS_IsRV64, // SRLW = 502 1994 CEFBS_None, // SUB = 503 1995 CEFBS_IsRV64, // SUBW = 504 1996 CEFBS_None, // SW = 505 1997 CEFBS_None, // UNIMP = 506 1998 CEFBS_None, // URET = 507 1999 CEFBS_None, // WFI = 508 2000 CEFBS_None, // XOR = 509 2001 CEFBS_None, // XORI = 510 2002 }; 2003 2004 assert(Inst.getOpcode() < 511); 2005 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]]; 2006 FeatureBitset MissingFeatures = 2007 (AvailableFeatures & RequiredFeatures) ^ 2008 RequiredFeatures; 2009 if (MissingFeatures.any()) { 2010 std::ostringstream Msg; 2011 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str() 2012 << " instruction but the "; 2013 for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) 2014 if (MissingFeatures.test(i)) 2015 Msg << SubtargetFeatureNames[i] << " "; 2016 Msg << "predicate(s) are not met"; 2017 report_fatal_error(Msg.str()); 2018 } 2019#else 2020// Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF). 2021(void)MCII; 2022#endif // NDEBUG 2023} 2024#endif 2025