1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Pseudo-instruction MC lowering Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9bool RISCVAsmPrinter:: 10emitPseudoExpansionLowering(MCStreamer &OutStreamer, 11 const MachineInstr *MI) { 12 switch (MI->getOpcode()) { 13 default: return false; 14 case RISCV::PseudoBR: { 15 MCInst TmpInst; 16 MCOperand MCOp; 17 TmpInst.setOpcode(RISCV::JAL); 18 // Operand: rd 19 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 20 // Operand: imm20 21 lowerOperand(MI->getOperand(0), MCOp); 22 TmpInst.addOperand(MCOp); 23 EmitToStreamer(OutStreamer, TmpInst); 24 break; 25 } 26 case RISCV::PseudoBRIND: { 27 MCInst TmpInst; 28 MCOperand MCOp; 29 TmpInst.setOpcode(RISCV::JALR); 30 // Operand: rd 31 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 32 // Operand: rs1 33 lowerOperand(MI->getOperand(0), MCOp); 34 TmpInst.addOperand(MCOp); 35 // Operand: imm12 36 lowerOperand(MI->getOperand(1), MCOp); 37 TmpInst.addOperand(MCOp); 38 EmitToStreamer(OutStreamer, TmpInst); 39 break; 40 } 41 case RISCV::PseudoCALLIndirect: { 42 MCInst TmpInst; 43 MCOperand MCOp; 44 TmpInst.setOpcode(RISCV::JALR); 45 // Operand: rd 46 TmpInst.addOperand(MCOperand::createReg(RISCV::X1)); 47 // Operand: rs1 48 lowerOperand(MI->getOperand(0), MCOp); 49 TmpInst.addOperand(MCOp); 50 // Operand: imm12 51 TmpInst.addOperand(MCOperand::createImm(0)); 52 EmitToStreamer(OutStreamer, TmpInst); 53 break; 54 } 55 case RISCV::PseudoRET: { 56 MCInst TmpInst; 57 MCOperand MCOp; 58 TmpInst.setOpcode(RISCV::JALR); 59 // Operand: rd 60 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 61 // Operand: rs1 62 TmpInst.addOperand(MCOperand::createReg(RISCV::X1)); 63 // Operand: imm12 64 TmpInst.addOperand(MCOperand::createImm(0)); 65 EmitToStreamer(OutStreamer, TmpInst); 66 break; 67 } 68 case RISCV::PseudoTAILIndirect: { 69 MCInst TmpInst; 70 MCOperand MCOp; 71 TmpInst.setOpcode(RISCV::JALR); 72 // Operand: rd 73 TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); 74 // Operand: rs1 75 lowerOperand(MI->getOperand(0), MCOp); 76 TmpInst.addOperand(MCOp); 77 // Operand: imm12 78 TmpInst.addOperand(MCOperand::createImm(0)); 79 EmitToStreamer(OutStreamer, TmpInst); 80 break; 81 } 82 } 83 return true; 84} 85 86