| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 123 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
131 unsigned DefIdx) const override { in hasLowDefLatency()
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| D | PPCVSXSwapRemoval.cpp | 617 int DefIdx = SwapMap[DefMI]; in formWebs() local
696 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
771 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
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| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 128 unsigned DefIdx = 0; in findDefIdx() local
188 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
228 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
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| D | TargetInstrInfo.cpp | 982 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
1070 unsigned DefIdx, in getOperandLatency()
1096 unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const { in computeOperandLatency()
1124 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs()
1149 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs()
1172 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs()
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| D | LiveRangeCalc.cpp | 46 SlotIndex DefIdx = in createDeadDef() local
195 unsigned DefIdx; in extendToUses() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.h | 131 unsigned DefIdx; variable
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.h | 141 unsigned DefIdx; variable
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 186 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
207 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
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| D | MCSubtargetInfo.h | 129 unsigned DefIdx) const { in getWriteLatencyEntry()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 181 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
202 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
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| D | MCSubtargetInfo.h | 170 unsigned DefIdx) const { in getWriteLatencyEntry()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 620 int DefIdx = SwapMap[DefMI]; in formWebs() local
701 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
777 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
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| D | PPCInstrInfo.h | 217 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
225 unsigned DefIdx) const override { in hasLowDefLatency()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 158 unsigned DefIdx = 0; in findDefIdx() local
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
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| D | TargetInstrInfo.cpp | 1037 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
1189 unsigned DefIdx, in getOperandLatency()
1214 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs()
1241 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs()
1266 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs()
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| D | LiveRangeCalc.cpp | 67 SlotIndex DefIdx = in createDeadDef() local
199 unsigned DefIdx; in extendToUses() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCSchedule.cpp | 43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 3187 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3228 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3331 unsigned DefIdx, unsigned DefAlign, in getOperandLatency()
3442 unsigned &DefIdx, unsigned &Dist) { in getBundledDefMI()
3675 unsigned DefIdx, in getOperandLatency()
3711 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, in getOperandLatencyImpl()
3771 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
4074 unsigned DefIdx, in hasHighOperandLatency()
4596 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
4621 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
[all …]
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 934 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
948 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
962 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs()
1282 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 327 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineMerges() local
363 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineMerges() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 3746 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3803 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3906 unsigned DefIdx, unsigned DefAlign, in getOperandLatency()
4017 unsigned &DefIdx, unsigned &Dist) { in getBundledDefMI()
4250 unsigned DefIdx, in getOperandLatency()
4286 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, in getOperandLatencyImpl()
4346 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
4692 unsigned DefIdx, in hasHighOperandLatency()
5245 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
5272 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 204 unsigned DefIdx = 0; in tryInlineAsm() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1145 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
1159 unsigned DefIdx, in getExtractSubregLikeInputs()
1173 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs()
1498 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 205 unsigned DefIdx = 0; in tryInlineAsm() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CollectLOH.cpp | 536 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
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