| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| D | WebAssemblyMCTargetDesc.h | 150 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { in GetDefaultP2AlignAny()
364 inline unsigned GetDefaultP2Align(unsigned Opc) { in GetDefaultP2Align()
372 inline bool isArgument(unsigned Opc) { in isArgument()
402 inline bool isCopy(unsigned Opc) { in isCopy()
422 inline bool isTee(unsigned Opc) { in isTee()
442 inline bool isCallDirect(unsigned Opc) { in isCallDirect()
476 inline bool isCallIndirect(unsigned Opc) { in isCallIndirect()
512 inline unsigned getCalleeOpNo(unsigned Opc) { in getCalleeOpNo()
573 inline bool isMarker(unsigned Opc) { in isMarker()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 420 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
425 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
430 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
436 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
440 static inline bool isPopOpcode(int Opc) { in isPopOpcode()
446 static inline bool isPushOpcode(int Opc) { in isPushOpcode()
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| D | ARMISelDAGToDAG.cpp | 112 SDValue &Opc) { in SelectAddrMode2Base()
117 SDValue &Opc) { in SelectAddrMode2ShOp()
122 SDValue &Opc) { in SelectAddrMode2()
308 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate()
533 SDValue &Opc, in SelectImmShifterOperand()
573 SDValue &Opc, in SelectRegShifterOperand()
652 SDValue &Opc) { in SelectLdStSOReg()
763 SDValue &Opc) { in SelectAddrMode2Worker()
900 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetReg()
936 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImmPre()
[all …]
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| D | ARMFastISel.cpp | 436 unsigned Opc; in ARMMaterializeFP() local
461 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
480 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
496 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
564 unsigned Opc; in ARMMaterializeGV() local
597 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci; in ARMMaterializeGV() local
613 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV() local
678 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in fastMaterializeAlloca() local
856 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
921 unsigned Opc; in ARMEmitLoad() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 487 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
512 static inline bool isVPTOpcode(int Opc) { in isVPTOpcode()
619 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
623 static inline bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
630 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
634 static inline bool isPopOpcode(int Opc) { in isPopOpcode()
640 static inline bool isPushOpcode(int Opc) { in isPushOpcode()
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| D | ARMFastISel.cpp | 429 unsigned Opc; in ARMMaterializeFP() local
454 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
472 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
488 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
560 unsigned Opc; in ARMMaterializeGV() local
593 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci; in ARMMaterializeGV() local
609 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV() local
674 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in fastMaterializeAlloca() local
852 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
918 unsigned Opc; in ARMEmitLoad() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 258 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode()
260 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
277 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; } in isIndirectBranchOpcode()
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| D | AArch64LoadStoreOptimizer.cpp | 199 static bool isNarrowStore(unsigned Opc) { in isNarrowStore()
211 static bool isNarrowLoad(unsigned Opc) { in isNarrowLoad()
231 static bool isNarrowLoadOrStore(unsigned Opc) { in isNarrowLoadOrStore()
293 static unsigned getMatchingNonSExtOpcode(unsigned Opc, in getMatchingNonSExtOpcode()
346 static unsigned getMatchingWideOpcode(unsigned Opc) { in getMatchingWideOpcode()
377 static unsigned getMatchingPairOpcode(unsigned Opc) { in getMatchingPairOpcode()
447 static unsigned getPreIndexedOpcode(unsigned Opc) { in getPreIndexedOpcode()
506 static unsigned getPostIndexedOpcode(unsigned Opc) { in getPostIndexedOpcode()
617 static bool isPromotableZeroStoreOpcode(unsigned Opc) { in isPromotableZeroStoreOpcode()
643 unsigned Opc = I->getOpcode(); in mergeNarrowInsns() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyExplicitLocals.cpp | 249 unsigned Opc = getLocalGetOpcode(RC); in runOnMachineFunction() local
259 unsigned Opc = getLocalTeeOpcode(RC); in runOnMachineFunction() local
287 unsigned Opc = getDropOpcode(RC); in runOnMachineFunction() local
295 unsigned Opc = getLocalSetOpcode(RC); in runOnMachineFunction() local
355 unsigned Opc = getLocalGetOpcode(RC); in runOnMachineFunction() local
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| D | WebAssemblyFastISel.cpp | 386 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in materializeLoadStoreOperands() local
605 unsigned Opc = in fastMaterializeAlloca() local
624 unsigned Opc = Subtarget->hasAddr64() ? WebAssembly::CONST_I64 in fastMaterializeConstant() local
659 unsigned Opc; in fastLowerArguments() local
762 unsigned Opc; in selectCall() local
906 unsigned Opc; in selectSelect() local
1003 unsigned Opc; in selectICmp() local
1072 unsigned Opc; in selectFCmp() local
1169 unsigned Opc; in selectLoad() local
1225 unsigned Opc; in selectStore() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 352 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode()
354 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
371 static inline bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
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| D | AArch64ConditionOptimizer.cpp | 217 static int getComplementOpc(int Opc) { in getComplementOpc()
244 unsigned Opc = CmpMI->getOpcode(); in adjustCmp() local
273 unsigned Opc; in modifyCmp() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 61 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch()
67 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump()
115 int Opc = MI.getOpcode(); in runOnMachineFunction() local
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| D | HexagonGenPredicate.cpp | 118 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm()
164 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
188 unsigned Opc = MI->getOpcode(); in collectPredicateGPR() local
236 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
265 bool HexagonGenPredicate::isScalarCmp(unsigned Opc) { in isScalarCmp()
351 unsigned Opc = MI->getOpcode(); in convertToPredForm() local
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| D | HexagonBitSimplify.cpp | 414 bool HexagonBitSimplify::getUsedBitsInStore(unsigned Opc, BitVector &Bits, in getUsedBitsInStore()
574 bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN, in getUsedBits()
949 unsigned Opc = MI->getOpcode(); in runOnNode() local
1028 unsigned Opc = MI.getOpcode(); in isLossyShiftLeft() local
1088 unsigned Opc = MI.getOpcode(); in isLossyShiftRight() local
1198 unsigned Opc = MI.getOpcode(); in computeUsedBits() local
1350 unsigned Opc = MI.getOpcode(); in isTfrConst() local
1386 unsigned Opc = isInt<8>(Lo) ? Hexagon::A2_combineii in genTfrConst() local
1400 unsigned Opc; in genTfrConst() local
1545 unsigned Opc = I->getOpcode(); in processBlock() local
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFastISel.cpp | 331 unsigned Opc = Subtarget->hasAddr64() ? in materializeLoadStoreOperands() local
531 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeAlloca() local
547 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeConstant() local
581 unsigned Opc; in fastLowerArguments() local
635 unsigned Opc; in selectCall() local
735 unsigned Opc; in selectSelect() local
822 unsigned Opc; in selectICmp() local
890 unsigned Opc; in selectFCmp() local
982 unsigned Opc; in selectLoad() local
1035 unsigned Opc; in selectStore() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 47 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
69 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
252 unsigned Opc = 0; in storeRegToStack() local
325 unsigned Opc = 0; in loadRegFromStack() local
406 unsigned Opc; in expandPostRAPseudo() local
591 unsigned Opc = ABI.GetPtrAdduOp(); in adjustStackPtr() local
696 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize()
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| D | MipsRegisterBankInfo.cpp | 109 static bool isFloatingPointOpcode(unsigned Opc) { in isFloatingPointOpcode()
130 static bool isFloatingPointOpcodeUse(unsigned Opc) { in isFloatingPointOpcodeUse()
146 static bool isFloatingPointOpcodeDef(unsigned Opc) { in isFloatingPointOpcodeDef()
159 static bool isAmbiguous(unsigned Opc) { in isAmbiguous()
404 unsigned Opc = MI.getOpcode(); in getInstrMapping() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 43 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
65 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
190 unsigned Opc = 0; in storeRegToStack() local
258 unsigned Opc = 0; in loadRegFromStack() local
334 unsigned Opc; in expandPostRAPseudo() local
454 unsigned Opc = ABI.GetPtrAdduOp(); in adjustStackPtr() local
537 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 61 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch()
76 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump()
128 int Opc = MI.getOpcode(); in runOnMachineFunction() local
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| D | HexagonGenPredicate.cpp | 143 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm()
188 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
211 unsigned Opc = MI->getOpcode(); in collectPredicateGPR() local
257 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
286 bool HexagonGenPredicate::isScalarCmp(unsigned Opc) { in isScalarCmp()
371 unsigned Opc = MI->getOpcode(); in convertToPredForm() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCFrameLowering.cpp | 138 unsigned Opc = ARC::SUB_rrlimm; in emitPrologue() local
255 unsigned Opc = ARC::SUB_rrlimm; in emitEpilogue() local
283 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
298 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
325 unsigned Opc = ARC::ADD_rrlimm; in emitEpilogue() local
456 unsigned Opc; in emitRegUpdate() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CSEMIRBuilder.cpp | 90 void CSEMIRBuilder::profileEverything(unsigned Opc, ArrayRef<DstOp> DstOps, in profileEverything()
137 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc, in buildInstr()
206 constexpr unsigned Opc = TargetOpcode::G_CONSTANT; in buildConstant() local
233 constexpr unsigned Opc = TargetOpcode::G_FCONSTANT; in buildFConstant() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 357 unsigned Opc = 0; in X86FastEmitLoad() local
510 unsigned Opc = 0; in X86FastEmitStore() local
658 unsigned Opc = 0; in X86FastEmitStore() local
695 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend()
756 unsigned Opc = 0; in handleConstantAddresses() local
1491 unsigned Opc = X86::getSETFromCond(CC); in X86SelectCmp() local
2044 unsigned Opc = X86::getCMovFromCond(CC, RC->getSize()); in X86FastEmitCMoveSelect() local
2097 unsigned *Opc = nullptr; in X86FastEmitSSESelect() local
2163 unsigned Opc; in X86FastEmitPseudoSelect() local
2335 unsigned Opc = Subtarget->hasAVX() ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr; in X86SelectFPExt() local
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| D | X86InstrInfo.cpp | 2566 unsigned Opc, bool AllowSP, unsigned &NewSrc, in classifyLEAReg()
2649 unsigned Opc, leaInReg; in convertToThreeAddressWithLEA() local
2800 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
2844 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r in convertToThreeAddress() local
2877 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r in convertToThreeAddress() local
2913 unsigned Opc; in convertToThreeAddress() local
2988 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
3203 unsigned Opc; in commuteInstructionImpl() local
3335 unsigned Opc; in commuteInstructionImpl() local
3394 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2); in commuteInstructionImpl() local
[all …]
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