| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 78 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
127 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
180 for(MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
193 for(MCRegAliasIterator SRI(R2, &RI, !MCSubRegIterator(R2, &RI).isValid()); in init() local
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| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 37 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
49 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNSchedStrategy.cpp | 34 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); in initialize() local
64 const SIRegisterInfo *SRI, in initCandidate()
146 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); in pickNodeFromQueue() local
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| D | AMDGPUMachineCFGStructurizer.cpp | 2107 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2118 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2151 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2156 auto SRI = PHIInfo.sources_begin(DestReg); in createEntryPHI() local
2167 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2267 auto SRI = PHIInfo.sources_begin(DestReg); in resolvePHIInfos() local
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| D | SIFoldOperands.cpp | 436 const SIRegisterInfo &SRI = TII->getRegisterInfo(); in tryAddToFoldList() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 266 for (MCSubRegIterator SRI(PhysReg, TRI, true); SRI.isValid(); ++SRI) in ScanInstruction() local
299 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
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| D | VirtRegMap.cpp | 295 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
|
| /external/capstone/ |
| D | MCRegisterInfo.c | 111 const uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; in MCRegisterInfo_getSubReg() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 79 for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in initReg() local
138 for (MCRegAliasIterator SRI(R, &RI, !MCSubRegIterator(R, &RI).isValid()); in init() local
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| /external/llvm/lib/CodeGen/ |
| D | VirtRegMap.cpp | 272 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
|
| D | CriticalAntiDepBreaker.cpp | 273 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 267 SubRegMap::const_iterator SRI = Map.find(I->first); in computeSubRegs() local
1449 for (CodeGenRegister::SubRegMap::const_iterator SRI = SRM.begin(), in normalizeWeight() local
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| D | CodeGenSchedule.cpp | 284 for (RecIter SRI = SRDefs.begin(), SRE = SRDefs.end(); SRI != SRE; ++SRI) { in collectSchedRW() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 2798 unsigned SRI; in Select() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 4922 unsigned SRI; in Select() local
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 5407 ### SRI ### subsection
10912 ### SRI ### subsection
|