| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 130 SrcOp(Register R) : Reg(R), Ty(SrcType::Ty_Reg) {} in SrcOp() function
131 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {} in SrcOp() function
132 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {} in SrcOp() function
133 SrcOp(const CmpInst::Predicate P) : Pred(P), Ty(SrcType::Ty_Predicate) {} in SrcOp() function
139 SrcOp(uint64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
140 SrcOp(int64_t V) : Imm(V), Ty(SrcType::Ty_Imm) {} in SrcOp() function
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| D | LegalizationArtifactCombiner.h | 300 unsigned SrcOp = SrcDef->getOpcode(); in tryCombineMerges() local
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1467 const MachineOperand &SrcOp = MI->getOperand(SrcIdx); in EmitInstruction() local
1489 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
1511 const MachineOperand &SrcOp = MI->getOperand(1); in EmitInstruction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 139 const MachineOperand &SrcOp = MI->getOperand(1); in INITIALIZE_PASS_DEPENDENCY() local
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| D | HexagonExpandCondsets.cpp | 623 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor()
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| D | HexagonFrameLowering.cpp | 2305 MachineOperand &SrcOp = SI.getOperand(2); in optimizeSpillSlots() local
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| D | HexagonBitSimplify.cpp | 2535 const MachineOperand &SrcOp = MI->getOperand(1); in simplifyExtractLow() local
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| D | HexagonInstrInfo.cpp | 1098 const MachineOperand &SrcOp = MI.getOperand(2); in expandPostRAPseudo() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 123 const MachineOperand &SrcOp = MI->getOperand(1); in interpretAsCopy() local
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| D | HexagonExpandCondsets.cpp | 611 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, in genCondTfrFor()
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| D | HexagonFrameLowering.cpp | 2108 MachineOperand &SrcOp = SI->getOperand(2); in optimizeSpillSlots() local
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.cpp | 244 std::pair<unsigned,unsigned> SrcOp = Ops.ParseOperandName(SrcOpName, false); in ParseConstraint() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILowerControlFlow.cpp | 465 for (const auto &SrcOp : Def->explicit_operands()) in findMaskOperands() local
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| D | SIInstrInfo.cpp | 1432 const MachineOperand &SrcOp = MI.getOperand(1); in expandPostRAPseudo() local
1596 const MachineOperand &SrcOp = MI.getOperand(I); in expandMovDPP64() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineVerifier.cpp | 1279 const MachineOperand &SrcOp = MI->getOperand(1); in verifyPreISelGenericInstruction() local
1301 const MachineOperand &SrcOp = MI->getOperand(2); in verifyPreISelGenericInstruction() local
1529 const MachineOperand &SrcOp = MI->getOperand(1); in visitMachineInstrBefore() local
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| D | MachineScheduler.cpp | 1689 const MachineOperand &SrcOp = Copy->getOperand(1); in constrainLocalCopy() local
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| /external/llvm/tools/llvm-c-test/ |
| D | echo.cpp | 429 LLVMValueRef SrcOp = LLVMGetOperand(Src, 0); in CloneInstruction() local
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| /external/llvm/lib/Linker/ |
| D | IRMover.cpp | 1045 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Linker/ |
| D | IRMover.cpp | 1227 MDNode *SrcOp = SrcModFlags->getOperand(I); in linkModuleFlagsMetadata() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 1745 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT, in EmitStackConvert()
1750 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT, in EmitStackConvert()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCasts.cpp | 1118 if (auto *SrcOp = dyn_cast<Instruction>(Src)) in visitZExt() local
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| D | InstructionCombining.cpp | 2196 Value *SrcOp = BCI->getOperand(0); in visitGetElementPtrInst() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 1599 const MachineOperand &SrcOp = Copy->getOperand(1); in constrainLocalCopy() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 861 const MachineOperand &SrcOp = MI.getOperand(1); in expandPostRAPseudo() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 6579 SDValue SrcOp = Op.getOperand(1); in computeKnownBitsForTargetNode() local
6598 SDValue SrcOp = Op.getOperand(0); in computeKnownBitsForTargetNode() local
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