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Searched defs:SubIdx (Results 1 – 25 of 62) sorted by relevance

123

/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DDetectDeadLanes.cpp242 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
246 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
266 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
316 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
322 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
334 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
DExpandPostRAPseudos.cpp86 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
DRegisterCoalescer.cpp1681 unsigned SubIdx) { in updateRegDefsUses()
2208 const unsigned SubIdx; member in __anonaebb90330311::JoinVals
2373 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals()
2865 bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx, in usesLanes()
DTargetRegisterInfo.cpp90 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg()
/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp245 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
249 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
269 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
319 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
325 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
337 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
DExpandPostRAPseudos.cpp90 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
DMachineCopyPropagation.cpp139 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src); in isNopCopy() local
DRegisterCoalescer.cpp1244 unsigned SubIdx) { in updateRegDefsUses()
1708 const unsigned SubIdx; member in __anon40bdeb910211::JoinVals
1863 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals()
2296 bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx, in usesLanes()
DTargetRegisterInfo.cpp46 unsigned SubIdx) { in PrintReg()
DMachineInstr.cpp77 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg()
1251 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect() local
1490 unsigned SubIdx, in substituteRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
/external/llvm/lib/Target/AMDGPU/
DSIMachineFunctionInfo.cpp187 unsigned SubIdx) { in getSpilledReg()
/external/llvm/lib/MC/
DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp444 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
493 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
534 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
626 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCRegisterInfo.cpp24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp449 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
498 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
553 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
652 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
/external/capstone/
DMCRegisterInfo.c86 unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx… in MCRegisterInfo_getMatchingSuperReg()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h370 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
380 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
499 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
DTargetInstrInfo.h171 unsigned &SubIdx) const { in isCoalescableExtInstr()
367 unsigned SubIdx; member
/external/llvm/utils/TableGen/
DCodeGenRegisters.h349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg()
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass()
DCodeGenRegisters.cpp469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
898 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses()
1565 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1927 for (const auto &SubIdx : SubRegIndices) { in inferSubClassWithSubReg() local
1959 for (auto &SubIdx : SubRegIndices) { in inferMatchingSuperRegClass() local
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h338 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
348 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
516 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp204 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
742 unsigned SubIdx; in selectTruncOrPtrToInt() local
1201 unsigned SubIdx = X86::NoSubRegister; in emitExtractSubreg() local
1239 unsigned SubIdx = X86::NoSubRegister; in emitInsertSubreg() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp314 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32() local
681 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in extractHvxElementReg() local
742 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in insertHvxElementReg() local
780 unsigned SubIdx; in extractHvxSubvectorReg() local
903 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi; in insertHvxSubvectorReg() local

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