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Searched defs:VirtReg (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/lib/CodeGen/
DLiveRegMatrix.cpp97 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
114 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
139 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
157 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
171 LiveIntervalUnion::Query &LiveRegMatrix::query(LiveInterval &VirtReg, in query()
179 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
DRegAllocFast.cpp71 unsigned VirtReg; // Virtual register number. member
184 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg()
205 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { in getStackSpaceFor()
260 void RAFast::killVirtReg(unsigned VirtReg) { in killVirtReg()
270 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg) { in spillVirtReg()
419 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
435 switch (unsigned VirtReg = PhysRegState[Alias]) { in definePhysReg() local
462 switch (unsigned VirtReg = PhysRegState[PhysReg]) { in calcSpillCost() local
483 switch (unsigned VirtReg = PhysRegState[Alias]) { in calcSpillCost() local
516 RAFast::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) { in assignVirtToPhysReg()
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DRegAllocGreedy.cpp216 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
494 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
506 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
618 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
662 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
725 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
807 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
858 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
1353 unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, in tryRegionSplit()
1383 unsigned RAGreedy::calculateRegionSplitCost(LiveInterval &VirtReg, in calculateRegionSplitCost()
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DVirtRegMap.cpp82 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys()
91 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) { in hasKnownPreference()
291 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
398 unsigned VirtReg = MO.getReg(); in rewrite() local
DLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
DRegAllocBasic.cpp166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
DAllocationOrder.cpp30 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
DRegAllocBase.cpp85 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
DRegisterCoalescer.h66 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair()
DLiveDebugVariables.cpp479 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg()
485 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg()
923 unsigned VirtReg = Loc.getReg(); in rewriteLocations() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegAllocFast.cpp86 Register VirtReg; ///< Virtual register number. member
203 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg()
248 int RegAllocFast::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor()
267 bool RegAllocFast::mayLiveOut(Register VirtReg) { in mayLiveOut()
296 bool RegAllocFast::mayLiveIn(Register VirtReg) { in mayLiveIn()
315 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg, in spill()
343 void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg, in reload()
397 void RegAllocFast::killVirtReg(Register VirtReg) { in killVirtReg()
408 Register VirtReg) { in spillVirtReg()
524 switch (Register VirtReg = PhysRegState[PhysReg]) { in definePhysReg() local
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DLiveRegMatrix.cpp104 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign()
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
146 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
164 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, unsigned PhysReg) { in checkInterference()
DRegAllocGreedy.cpp259 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
636 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg()
651 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
762 unsigned RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
809 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign()
872 bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, in canEvictInterference()
969 bool RAGreedy::canEvictInterferenceInRange(LiveInterval &VirtReg, in canEvictInterferenceInRange()
1023 LiveInterval &VirtReg, in getCheapestEvicteeWeight()
1048 void RAGreedy::evictInterference(LiveInterval &VirtReg, unsigned PhysReg, in evictInterference()
1106 unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, in tryEvict()
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DRegAllocBasic.cpp159 void RABasic::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg()
204 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences()
256 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
DLiveIntervalUnion.cpp29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
DVirtRegMap.cpp101 bool VirtRegMap::hasPreferredPhys(Register VirtReg) { in hasPreferredPhys()
110 bool VirtRegMap::hasKnownPreference(Register VirtReg) { in hasKnownPreference()
314 Register VirtReg = Register::index2VirtReg(Idx); in addMBBLiveIns() local
517 Register VirtReg = MO.getReg(); in rewrite() local
DAllocationOrder.cpp29 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder()
DRegAllocBase.cpp89 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
DRegisterCoalescer.h62 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair()
/external/llvm/include/llvm/CodeGen/
DLiveIntervalUnion.h88 void unify(LiveInterval &VirtReg) { in unify()
94 void extract(LiveInterval &VirtReg) { in extract()
113 LiveInterval *VirtReg; variable
DVirtRegMap.h151 unsigned getOriginal(unsigned VirtReg) const { in getOriginal()
DScheduleDAGInstrs.h36 unsigned VirtReg; member
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIPreAllocateWWMRegs.cpp128 const Register VirtReg = MO.getReg(); in rewriteRegs() local
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DVirtRegMap.h148 unsigned getOriginal(unsigned VirtReg) const { in getOriginal()
DScheduleDAGInstrs.h53 unsigned VirtReg; member

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