| /art/compiler/debug/ |
| D | elf_debug_frame_writer.h | 50 for (int reg = 0; reg < 13; reg++) { in WriteCIE() local
58 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
73 for (int reg = 0; reg < 30; reg++) { in WriteCIE() local
81 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
103 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
114 for (int reg = 0; reg < 8; reg++) { in WriteCIE() local
127 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
137 for (int reg = 0; reg < 16; reg++) { in WriteCIE() local
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| /art/compiler/utils/x86/ |
| D | managed_register_x86_test.cc | 27 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
33 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
67 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); in TEST() local
93 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); in TEST() local
119 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
257 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
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| D | assembler_x86.h | 92 bool IsRegister(Register reg) const { in IsRegister()
152 explicit Operand(Register reg) : disp_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand()
902 void cmpxchgb(const Address& address, Register reg) { in cmpxchgb()
907 void LockCmpxchgb(const Address& address, Register reg) { in LockCmpxchgb()
911 void LockCmpxchgb(const Address& address, ByteRegister reg) { in LockCmpxchgb()
915 void LockCmpxchgw(const Address& address, Register reg) { in LockCmpxchgw()
926 void LockCmpxchgl(const Address& address, Register reg) { in LockCmpxchgl()
935 void LockXaddb(const Address& address, Register reg) { in LockXaddb()
939 void LockXaddb(const Address& address, ByteRegister reg) { in LockXaddb()
943 void LockXaddw(const Address& address, Register reg) { in LockXaddw()
[all …]
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| D | managed_register_x86.cc | 41 RegisterPair reg; // Used to verify that the enum is in sync. member
53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { in operator <<()
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| /art/compiler/utils/x86_64/ |
| D | managed_register_x86_64_test.cc | 26 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
32 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
66 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); in TEST() local
92 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); in TEST() local
118 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
256 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
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| D | assembler_x86_64.h | 130 bool IsRegister(CpuRegister reg) const { in IsRegister()
196 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand()
996 void LockCmpxchgb(const Address& address, CpuRegister reg) { in LockCmpxchgb()
1000 void LockCmpxchgw(const Address& address, CpuRegister reg) { in LockCmpxchgw()
1012 void LockCmpxchgl(const Address& address, CpuRegister reg) { in LockCmpxchgl()
1016 void LockCmpxchgq(const Address& address, CpuRegister reg) { in LockCmpxchgq()
1020 void LockXaddb(const Address& address, CpuRegister reg) { in LockXaddb()
1024 void LockXaddw(const Address& address, CpuRegister reg) { in LockXaddw()
1036 void LockXaddl(const Address& address, CpuRegister reg) { in LockXaddl()
1040 void LockXaddq(const Address& address, CpuRegister reg) { in LockXaddq()
[all …]
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| D | managed_register_x86_64.cc | 40 RegisterPair reg; // Used to verify that the enum is in sync. member
52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) { in operator <<()
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| /art/libelffile/dwarf/ |
| D | debug_frame_opcode_writer.h | 73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset()
119 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset()
141 void ALWAYS_INLINE Restore(Reg reg) { in Restore()
153 void ALWAYS_INLINE Undefined(Reg reg) { in Undefined()
161 void ALWAYS_INLINE SameValue(Reg reg) { in SameValue()
170 void ALWAYS_INLINE Register(Reg reg, Reg new_reg) { in Register()
193 void ALWAYS_INLINE DefCFA(Reg reg, int offset) { in DefCFA()
210 void ALWAYS_INLINE DefCFARegister(Reg reg) { in DefCFARegister()
236 void ALWAYS_INLINE ValOffset(Reg reg, int offset) { in ValOffset()
263 void ALWAYS_INLINE Expression(Reg reg, uint8_t* expr, int expr_size) { in Expression()
[all …]
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| /art/runtime/arch/arm/ |
| D | context_arm.h | 57 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
62 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
67 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
75 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
80 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| D | context_arm.cc | 61 void ArmContext::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
68 void ArmContext::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
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| /art/runtime/arch/x86_64/ |
| D | context_x86_64.h | 56 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
61 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
66 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
74 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
79 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| D | asm_support_x86_64.S | 76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
78 #define CFI_RESTORE(reg) .cfi_restore reg argument
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
96 #define CFI_DEF_CFA(reg,size) argument
97 #define CFI_DEF_CFA_REGISTER(reg) argument
98 #define CFI_RESTORE(reg) argument
99 #define CFI_REL_OFFSET(reg,size) argument
127 #define CFI_REG(reg) CFI_REG_##reg argument
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| D | context_x86_64.cc | 89 void X86_64Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
96 void X86_64Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
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| /art/runtime/arch/riscv64/ |
| D | context_riscv64.h | 51 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
56 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
61 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
70 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
75 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| D | asm_support_riscv64.S | 99 .macro LOAD_RUNTIME_INSTANCE reg argument
194 .macro SETUP_CALLEE_SAVE_FRAME_COMMON_INTERNAL reg argument
452 .macro RETURN_OR_DELIVER_PENDING_EXCEPTION_REG reg argument
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| D | context_riscv64.cc | 70 void Riscv64Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
78 void Riscv64Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
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| /art/runtime/arch/arm64/ |
| D | context_arm64.h | 57 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
62 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
67 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
76 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
81 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| /art/compiler/utils/arm/ |
| D | managed_register_arm_test.cc | 26 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
32 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
70 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); in TEST() local
127 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); in TEST() local
228 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); in TEST() local
460 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
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| /art/compiler/utils/arm64/ |
| D | managed_register_arm64_test.cc | 28 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
35 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
108 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); in TEST() local
170 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); in TEST() local
221 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); in TEST() local
377 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
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| /art/runtime/arch/x86/ |
| D | context_x86.h | 56 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR()
61 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress()
66 uintptr_t GetGPR(uint32_t reg) override { in GetGPR()
74 bool IsAccessibleFPR(uint32_t reg) override { in IsAccessibleFPR()
79 uintptr_t GetFPR(uint32_t reg) override { in GetFPR()
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| D | asm_support_x86.S | 77 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
78 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
79 #define CFI_RESTORE(reg) .cfi_restore reg argument
80 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
98 #define CFI_DEF_CFA(reg,size) argument
99 #define CFI_DEF_CFA_REGISTER(reg) argument
100 #define CFI_RESTORE(reg) argument
101 #define CFI_REL_OFFSET(reg,size) argument
120 #define CFI_REG(reg) CFI_REG_##reg argument
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| D | context_x86.cc | 77 void X86Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR()
84 void X86Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR()
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| /art/compiler/utils/riscv64/ |
| D | managed_register_riscv64_test.cc | 26 Riscv64ManagedRegister reg = ManagedRegister::NoRegister().AsRiscv64(); in TEST() local
31 Riscv64ManagedRegister reg = Riscv64ManagedRegister::FromXRegister(Zero); in TEST() local
99 Riscv64ManagedRegister reg = Riscv64ManagedRegister::FromFRegister(FT0); in TEST() local
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| /art/runtime/interpreter/ |
| D | cfi_asm_support.h | 48 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(reg, offset, size) .cfi_escape \ argument
54 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(reg, offset, size) .cfi_escape \ argument
80 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(reg, offset, size) argument
81 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(reg, offset, size) argument
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| /art/runtime/verifier/ |
| D | register_line.h | 370 const uint32_t reg = pair.first; in IterateRegToLockDepths() local
391 bool IsSetLockDepth(size_t reg, size_t depth) { in IsSetLockDepth()
400 bool SetRegToLockDepth(size_t reg, size_t depth) { in SetRegToLockDepth()
416 void ClearAllRegToLockDepths(size_t reg) { in ClearAllRegToLockDepths()
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