| /external/llvm/lib/IR/ |
| D | ConstantRange.cpp | 783 ConstantRange::umin(const ConstantRange &Other) const { in umin() function in ConstantRange
831 APInt umin = APIntOps::umin(Other.getUnsignedMax(), getUnsignedMax()); in binaryAnd() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/IR/ |
| D | ConstantRange.cpp | 1021 ConstantRange::umin(const ConstantRange &Other) const { in umin() function in ConstantRange
1199 APInt umin = APIntOps::umin(Other.getUnsignedMax(), getUnsignedMax()); in binaryAnd() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ADT/ |
| D | APInt.h | 2172 inline const APInt &umin(const APInt &A, const APInt &B) { in umin() function
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| /external/llvm/include/llvm/ADT/ |
| D | APInt.h | 1766 inline const APInt &umin(const APInt &A, const APInt &B) { in umin() function
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| /external/swiftshader/third_party/llvm-subzero/include/llvm/ADT/ |
| D | APInt.h | 1793 inline const APInt &umin(const APInt &A, const APInt &B) { in umin() function
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| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2255 __ umin(v22.V16B(), v0.V16B(), v18.V16B()); in GenerateTestSequenceNEON() local
2256 __ umin(v1.V2S(), v21.V2S(), v16.V2S()); in GenerateTestSequenceNEON() local
2257 __ umin(v17.V4H(), v4.V4H(), v25.V4H()); in GenerateTestSequenceNEON() local
2258 __ umin(v24.V4S(), v26.V4S(), v13.V4S()); in GenerateTestSequenceNEON() local
2259 __ umin(v20.V8B(), v1.V8B(), v5.V8B()); in GenerateTestSequenceNEON() local
2260 __ umin(v26.V8H(), v25.V8H(), v23.V8H()); in GenerateTestSequenceNEON() local
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| D | test-api-movprfx-aarch64.cc | 313 __ umin(z0.VnS(), p2.Merging(), z0.VnS(), z0.VnS()); in TEST() local
855 __ umin(z1.VnS(), p0.Merging(), z1.VnS(), z28.VnS()); in TEST() local
1224 __ umin(z4.VnD(), z4.VnD(), 42); in TEST() local
1642 __ umin(z27.VnS(), p0.Merging(), z27.VnS(), z8.VnS()); in TEST() local
1645 __ umin(z0.VnH(), z0.VnH(), 42); in TEST() local
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_peephole.cpp | 1588 #define CASE(type, dst, fmin, fmax, imin, imax, umin, umax) \ in opnd() argument
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| /external/vixl/src/aarch64/ |
| D | assembler-sve-aarch64.cc | 2626 void Assembler::umin(const ZRegister& zd, in umin() function in vixl::aarch64::Assembler
3772 void Assembler::umin(const ZRegister& zd, const ZRegister& zn, int imm8) { in umin() function in vixl::aarch64::Assembler
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| D | logic-aarch64.cc | 1373 LogicVRegister Simulator::umin(VectorFormat vform, in umin() function in vixl::aarch64::Simulator
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