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Searched refs:S0 (Results 1 – 13 of 13) sorted by relevance

/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc70 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); in TEST()
77 EXPECT_EQ(S0, reg.AsSRegister()); in TEST()
135 EXPECT_EQ(S0, reg.AsOverlappingDRegisterLow()); in TEST()
137 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromSRegisterPair(S0))); in TEST()
295 EXPECT_TRUE(!no_reg.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
303 EXPECT_TRUE(!reg_R0.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
311 EXPECT_TRUE(!reg_R1.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
321 EXPECT_TRUE(!reg_R8.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
327 ArmManagedRegister reg_S0 = ArmManagedRegister::FromSRegister(S0); in TEST()
331 EXPECT_TRUE(reg_S0.Equals(ArmManagedRegister::FromSRegister(S0))); in TEST()
[all …]
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc171 Arm64ManagedRegister sreg = Arm64ManagedRegister::FromSRegister(S0); in TEST()
179 EXPECT_EQ(S0, reg.AsOverlappingSRegister()); in TEST()
221 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); in TEST()
229 EXPECT_EQ(S0, reg.AsSRegister()); in TEST()
231 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
278 EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
285 EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
294 EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
301 EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
310 EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S0))); in TEST()
[all …]
/art/runtime/arch/arm/
Dregisters_arm.cc38 if (rhs >= S0 && rhs < kNumberOfSRegisters) { in operator <<()
Dregisters_arm.h58 S0 = 0, enumerator
Dcontext_arm.cc82 fprs_[S0] = nullptr; in SmashCallerSaves()
Dcallee_save_frame_arm.h47 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
/art/runtime/arch/arm64/
Dregisters_arm64.cc66 if (rhs >= S0 && rhs < kNumberOfSRegisters) { in operator <<()
Dregisters_arm64.h154 S0 = 0, enumerator
/art/runtime/arch/riscv64/
Dregisters_riscv64.h38 S0 = 8, // X8/FP, callee-saved 0 / frame pointer enumerator
Dcallee_save_frame_riscv64.h36 (1 << art::riscv64::S0) | (1 << art::riscv64::S2) | (1 << art::riscv64::S3) |
/art/compiler/utils/riscv64/
Dmanaged_register_riscv64_test.cc67 reg = Riscv64ManagedRegister::FromXRegister(S0); in TEST()
71 EXPECT_EQ(S0, reg.AsXRegister()); in TEST()
/art/compiler/jni/quick/arm64/
Dcalling_convention_arm64.cc46 S0, S1, S2, S3, S4, S5, S6, S7
147 return Arm64ManagedRegister::FromSRegister(S0); in ReturnRegisterForShorty()
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc56 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
172 return ArmManagedRegister::FromSRegister(S0); in ReturnRegister()