Searched refs:TR (Results 1 – 16 of 16) sorted by relevance
| /art/disassembler/ |
| D | disassembler_arm64.cc | 39 TR = 19, enumerator
50 if (reg.GetCode() == TR) { in AppendRegisterNameToOutput()
129 if (instr->GetRn() == TR) { in VisitLoadStoreUnsignedOffsetInstr()
140 target->GetRn() == TR && in VisitUnconditionalBranchInstr()
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| D | disassembler_arm.cc | 40 static const vixl::aarch32::Register tr(TR);
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 66 ___ Mov(reg_x(dest.AsArm64().AsXRegister()), reg_x(TR)); in GetCurrentThread()
70 StoreToOffset(TR, SP, offset.Int32Value()); in GetCurrentThread()
208 ___ Str(scratch, MEM_OP(reg_x(TR), tr_offs.Int32Value())); in StoreStackPointerToThread()
312 LoadFromOffset(dst.AsXRegister(), TR, offs.Int32Value()); in LoadRawPtrFromThread()
643 ___ Ldr(lr, MEM_OP(reg_x(TR), offset.Int32Value())); in CallFromThread()
723 ___ Ldxr(scratch, MEM_OP(reg_x(TR))); in TryToTransitionFromRunnableToNative()
728 ___ Stlxr(scratch, scratch2, MEM_OP(reg_x(TR))); in TryToTransitionFromRunnableToNative()
732 ___ Str(xzr, MEM_OP(reg_x(TR), thread_held_mutex_mutator_lock_offset.Int32Value())); in TryToTransitionFromRunnableToNative()
755 ___ Ldaxr(scratch, MEM_OP(reg_x(TR))); in TryToTransitionFromNativeToRunnable()
763 ___ Stxr(scratch, wzr, MEM_OP(reg_x(TR))); in TryToTransitionFromNativeToRunnable()
[all …]
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| D | assembler_arm64.cc | 192 vixl::aarch64::Register tr = reg_x(TR); // Thread Register. in GenerateMarkingRegisterCheck()
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| D | managed_register_arm64_test.cc | 628 EXPECT_TRUE(vixl::aarch64::x19.Is(Arm64Assembler::reg_x(TR))); in TEST()
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| /art/cmdline/detail/ |
| D | cmdline_parser_detail.h | 54 template <typename TL, typename TR>
55 static std::true_type EqualityOperatorTest(const TL& left, const TR& right,
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| /art/runtime/arch/arm/ |
| D | registers_arm.h | 44 TR = 9, // ART Thread Register enumerator
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| D | context_arm.cc | 112 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]); in DoLongJump()
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| /art/runtime/arch/riscv64/ |
| D | registers_riscv64.h | 70 TR = S1, // ART Thread Register - managed runtime enumerator
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| D | context_riscv64.cc | 144 gprs[TR] = reinterpret_cast<uintptr_t>(Thread::Current()); in DoLongJump()
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| /art/runtime/arch/arm64/ |
| D | registers_arm64.h | 63 TR = X19, // ART Thread Register - Managed Runtime (Callee Saved Reg) enumerator
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| D | context_arm64.cc | 162 DCHECK_EQ(reinterpret_cast<uintptr_t>(Thread::Current()), gprs[TR]); in DoLongJump()
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| /art/compiler/trampolines/ |
| D | trampoline_compiler.cc | 113 __ JumpTo(Arm64ManagedRegister::FromXRegister(TR), Offset(offset.Int32Value()), in CreateTrampoline()
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.cc | 39 extern const vixl32::Register tr(TR);
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| /art/compiler/optimizing/ |
| D | code_generator_arm64.cc | 5315 assembler.JumpTo(ManagedRegister(arm64::TR), offset, ManagedRegister(arm64::IP0)); in EmitThunkCode()
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| D | code_generator_arm_vixl.cc | 2144 blocked_core_registers_[TR] = true; in SetupBlockedRegisters()
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