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Searched refs:imm (Results 1 – 17 of 17) sorted by relevance

/art/compiler/optimizing/
Dscheduler_arm64.cc94 int64_t imm = Int64FromConstant(instr->GetRight()->AsConstant()); in VisitDiv() local
95 if (imm == 0) { in VisitDiv()
98 } else if (imm == 1 || imm == -1) { in VisitDiv()
101 } else if (IsPowerOfTwo(AbsOrMin(imm))) { in VisitDiv()
105 DCHECK(imm <= -2 || imm >= 2); in VisitDiv()
162 int64_t imm = Int64FromConstant(instruction->GetRight()->AsConstant()); in VisitRem() local
163 if (imm == 0) { in VisitRem()
166 } else if (imm == 1 || imm == -1) { in VisitRem()
169 } else if (IsPowerOfTwo(AbsOrMin(imm))) { in VisitRem()
173 DCHECK(imm <= -2 || imm >= 2); in VisitRem()
Dscheduler_arm.cc815 void SchedulingLatencyVisitorARM::HandleDivRemConstantIntegralLatencies(int32_t imm) { in HandleDivRemConstantIntegralLatencies() argument
816 if (imm == 0) { in HandleDivRemConstantIntegralLatencies()
819 } else if (imm == 1 || imm == -1) { in HandleDivRemConstantIntegralLatencies()
821 } else if (IsPowerOfTwo(AbsOrMin(imm))) { in HandleDivRemConstantIntegralLatencies()
836 int32_t imm = Int32ConstantFrom(rhs->AsConstant()); in VisitDiv() local
837 HandleDivRemConstantIntegralLatencies(imm); in VisitDiv()
904 int32_t imm = Int32ConstantFrom(rhs->AsConstant()); in VisitRem() local
905 HandleDivRemConstantIntegralLatencies(imm); in VisitRem()
Dcode_generator_x86_64.cc3800 Immediate imm(second.GetConstant()->AsIntConstant()->GetValue()); in VisitSub() local
3801 __ subl(first.AsRegister<CpuRegister>(), imm); in VisitSub()
3903 Immediate imm(mul->InputAt(1)->AsIntConstant()->GetValue()); in VisitMul() local
3904 __ imull(out.AsRegister<CpuRegister>(), first.AsRegister<CpuRegister>(), imm); in VisitMul()
4061 int64_t imm = Int64FromConstant(second.GetConstant()); in DivRemOneOrMinusOne() local
4063 DCHECK(imm == 1 || imm == -1); in DivRemOneOrMinusOne()
4071 if (imm == -1) { in DivRemOneOrMinusOne()
4083 if (imm == -1) { in DivRemOneOrMinusOne()
4099 int64_t imm = Int64FromConstant(second.GetConstant()); in RemByPowerOfTwo() local
4100 DCHECK(IsPowerOfTwo(AbsOrMin(imm))); in RemByPowerOfTwo()
[all …]
Dscheduler_arm.h125 void HandleDivRemConstantIntegralLatencies(int32_t imm);
Dcode_generator_arm64.cc3261 int64_t imm = Int64FromLocation(instruction->GetLocations()->InAt(1)); in FOR_EACH_CONDITION_INSTRUCTION() local
3262 uint64_t abs_imm = static_cast<uint64_t>(AbsOrMin(imm)); in FOR_EACH_CONDITION_INSTRUCTION()
3308 if (imm > 0) { in FOR_EACH_CONDITION_INSTRUCTION()
3367 int64_t imm = Int64FromConstant(second.GetConstant()); in GenerateInt64UnsignedDivRemWithAnyPositiveConstant() local
3368 DCHECK_GT(imm, 0); in GenerateInt64UnsignedDivRemWithAnyPositiveConstant()
3372 CalculateMagicAndShiftForDivRem(imm, /* is_long= */ true, &magic, &shift); in GenerateInt64UnsignedDivRemWithAnyPositiveConstant()
3401 GenerateResultRemWithAnyConstant(out, dividend, temp, imm, &temps); in GenerateInt64UnsignedDivRemWithAnyPositiveConstant()
3418 int64_t imm = Int64FromConstant(second.GetConstant()); in GenerateInt64DivRemWithAnyConstant() local
3422 CalculateMagicAndShiftForDivRem(imm, /* is_long= */ true, &magic, &shift); in GenerateInt64DivRemWithAnyConstant()
3442 if (NeedToAddDividend(magic, imm)) { in GenerateInt64DivRemWithAnyConstant()
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Dcode_generator_x86.cc3760 Immediate imm(mul->InputAt(1)->AsIntConstant()->GetValue()); in VisitMul() local
3761 __ imull(out.AsRegister<Register>(), first.AsRegister<Register>(), imm); in VisitMul()
4002 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); in DivRemOneOrMinusOne() local
4004 DCHECK(imm == 1 || imm == -1); in DivRemOneOrMinusOne()
4010 if (imm == -1) { in DivRemOneOrMinusOne()
4023 int32_t imm = Int64FromConstant(second.GetConstant()); in RemByPowerOfTwo() local
4024 DCHECK(IsPowerOfTwo(AbsOrMin(imm))); in RemByPowerOfTwo()
4025 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm)); in RemByPowerOfTwo()
4043 int32_t imm = locations->InAt(1).GetConstant()->AsIntConstant()->GetValue(); in DivByPowerOfTwo() local
4044 DCHECK(IsPowerOfTwo(AbsOrMin(imm))); in DivByPowerOfTwo()
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Dcode_generator_arm_vixl.cc4404 int32_t imm = Int32ConstantFrom(second); in DivRemOneOrMinusOne() local
4405 DCHECK(imm == 1 || imm == -1); in DivRemOneOrMinusOne()
4410 if (imm == 1) { in DivRemOneOrMinusOne()
4428 int32_t imm = Int32ConstantFrom(second); in DivRemByPowerOfTwo() local
4429 uint32_t abs_imm = static_cast<uint32_t>(AbsOrMin(imm)); in DivRemByPowerOfTwo()
4432 auto generate_div_code = [this, imm, ctz_imm](vixl32::Register out, vixl32::Register in) { in DivRemByPowerOfTwo()
4434 if (imm < 0) { in DivRemByPowerOfTwo()
4510 int32_t imm = Int32ConstantFrom(second); in GenerateDivRemWithAnyConstant() local
4514 CalculateMagicAndShiftForDivRem(imm, /* is_long= */ false, &magic, &shift); in GenerateDivRemWithAnyConstant()
4548 if (imm > 0 && HasNonNegativeInputAt(instruction, 0)) { in GenerateDivRemWithAnyConstant()
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/art/test/442-checker-constant-folding/src/
DMain.java1392 long imm = 33L; in ReturnInt33() local
1393 return (int) imm; in ReturnInt33()
1409 float imm = 1.0e34f; in ReturnIntMax() local
1410 return (int) imm; in ReturnIntMax()
1426 double imm = Double.NaN; in ReturnInt0() local
1427 return (int) imm; in ReturnInt0()
1443 int imm = 33; in ReturnLong33() local
1444 return (long) imm; in ReturnLong33()
1460 float imm = 34.0f; in ReturnLong34() local
1461 return (long) imm; in ReturnLong34()
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/art/compiler/utils/x86_64/
Dassembler_x86_64.h439 void pushq(const Immediate& imm);
455 void movq(const Address& dst, const Immediate& imm);
457 void movl(const Address& dst, const Immediate& imm);
469 void movb(const Address& dst, const Immediate& imm);
477 void movw(const Address& dst, const Immediate& imm);
644 void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm);
645 void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm);
725 void shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm);
726 void shufps(XmmRegister dst, XmmRegister src, const Immediate& imm);
727 void pshufd(XmmRegister dst, XmmRegister src, const Immediate& imm);
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Dassembler_x86_64.cc114 void X86_64Assembler::pushq(const Immediate& imm) { in pushq() argument
116 CHECK(imm.is_int32()); // pushq only supports 32b immediate. in pushq()
117 if (imm.is_int8()) { in pushq()
119 EmitUint8(imm.value() & 0xFF); in pushq()
122 EmitImmediate(imm); in pushq()
142 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { in movq() argument
144 if (imm.is_int32()) { in movq()
149 EmitInt32(static_cast<int32_t>(imm.value())); in movq()
153 EmitInt64(imm.value()); in movq()
158 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { in movl() argument
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Dassembler_x86_64_test.cc114 x86_64::Immediate imm(value); in TEST() local
115 EXPECT_FALSE(imm.is_int8()); in TEST()
116 EXPECT_FALSE(imm.is_int16()); in TEST()
117 EXPECT_FALSE(imm.is_int32()); in TEST()
/art/compiler/utils/x86/
Dassembler_x86.cc115 void X86Assembler::pushl(const Immediate& imm) { in pushl() argument
117 if (imm.is_int8()) { in pushl()
119 EmitUint8(imm.value() & 0xFF); in pushl()
122 EmitImmediate(imm); in pushl()
140 void X86Assembler::movl(Register dst, const Immediate& imm) { in movl() argument
143 EmitImmediate(imm); in movl()
168 void X86Assembler::movl(const Address& dst, const Immediate& imm) { in movl() argument
172 EmitImmediate(imm); in movl()
325 void X86Assembler::movb(const Address& dst, const Immediate& imm) { in movb() argument
329 CHECK(imm.is_int8()); in movb()
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Dassembler_x86.h395 void pushl(const Immediate& imm);
405 void movl(const Address& dst, const Immediate& imm);
424 void rorl(Register reg, const Immediate& imm);
426 void roll(Register reg, const Immediate& imm);
435 void movb(const Address& dst, const Immediate& imm);
443 void movw(const Address& dst, const Immediate& imm);
605 void roundsd(XmmRegister dst, XmmRegister src, const Immediate& imm);
606 void roundss(XmmRegister dst, XmmRegister src, const Immediate& imm);
687 void shufpd(XmmRegister dst, XmmRegister src, const Immediate& imm);
688 void shufps(XmmRegister dst, XmmRegister src, const Immediate& imm);
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/art/compiler/utils/arm/
Dassembler_arm_vixl.h168 void Vmov(vixl32::DRegister rd, double imm) { in Vmov() argument
169 if (vixl::VFP::IsImmFP64(imm)) { in Vmov()
170 MacroAssembler::Vmov(rd, imm); in Vmov()
172 MacroAssembler::Vldr(rd, imm); in Vmov()
/art/compiler/utils/
Dassembler_test.h215 for (int64_t imm : imms) { variable
216 ImmType new_imm = CreateImmediate(imm);
237 sreg << imm * multiplier + bias;
271 for (int64_t imm : imms) { in RepeatTemplatedRegistersImmBits() local
272 ImmType new_imm = CreateImmediate(imm); in RepeatTemplatedRegistersImmBits()
299 sreg << imm + bias; in RepeatTemplatedRegistersImmBits()
332 for (int64_t imm : imms) { in RepeatTemplatedImmBitsRegisters() local
333 ImmType new_imm = CreateImmediate(imm); in RepeatTemplatedImmBitsRegisters()
354 sreg << imm; in RepeatTemplatedImmBitsRegisters()
382 for (int64_t imm : imms) { in RepeatTemplatedRegisterImmBits() local
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Dassembler_thumb_test_expected.cc.inc81 " f4: d16f bne 0x1d6 @ imm = #222\n"
137 " 1d2: f000 b803 b.w 0x1dc @ imm = #6\n"
138 " 1d6: f000 b81e b.w 0x216 @ imm = #60\n"
/art/dex2oat/linker/arm/
Drelative_patcher_thumb2.cc79 uint32_t imm = (diff16 >> 11) & 0x1u; in PatchPcRelativeReference() local
82 insn = (insn & 0xfbf08f00u) | (imm << 26) | (imm4 << 16) | (imm3 << 12) | imm8; in PatchPcRelativeReference()