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Searched refs:ADDVI_W (Results 1 – 12 of 12) sorted by relevance

/external/webp/src/dsp/
Dmsa_macro.h31 #define ADDVI_W(a, b) __msa_addvi_w((v4i32)a, b) macro
42 #define ADDVI_W(a, b) (a + b) macro
1150 out0 = (RTYPE)ADDVI_W(in0, in1); \
1151 out1 = (RTYPE)ADDVI_W(in2, in3); \
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsLegalizerInfo.cpp401 return SelectMSA3OpIntrinsic(MI, Mips::ADDVI_W, MIRBuilder, ST); in legalizeIntrinsic()
DMipsMSAInstrInfo.td2765 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc79 2281725637U, // ADDVI_W
1868 0U, // ADDVI_W
5043 // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, ANDI_B, BCLRI_B, BCLRI_D, BCLRI_H,...
DMipsGenDisassemblerTables.inc1553 /* 3977 */ MCD_OPC_Decode, 62, 124, // Opcode: ADDVI_W
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmWriter.inc1925 268460403U, // ADDVI_W
4679 4U, // ADDVI_W
7225 // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG...
DMipsGenMCCodeEmitter.inc697 UINT64_C(2017460230), // ADDVI_W
4073 case Mips::ADDVI_W:
10159 CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 684
DMipsGenDAGISel.inc15994 /* 29507*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_W), 0,
15997 … // Dst: (ADDVI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
16000 /* 29519*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::ADDVI_W), 0,
16003 … // Dst: (ADDVI_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, vsplati32_uimm5:{ *:[v4i32] }:$imm)
DMipsGenInstrInfo.inc699 ADDVI_W = 684,
5545 …, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #684 = ADDVI_W
DMipsGenDisassemblerTables.inc3880 /* 5328 */ MCD::OPC_Decode, 172, 5, 240, 1, // Opcode: ADDVI_W
DMipsGenAsmMatcher.inc5547 …{ 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,…
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td2739 def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;