1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Target Instruction Enum Values and Descriptors *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9#ifdef GET_INSTRINFO_ENUM 10#undef GET_INSTRINFO_ENUM 11namespace llvm { 12 13namespace Mips { 14 enum { 15 PHI = 0, 16 INLINEASM = 1, 17 INLINEASM_BR = 2, 18 CFI_INSTRUCTION = 3, 19 EH_LABEL = 4, 20 GC_LABEL = 5, 21 ANNOTATION_LABEL = 6, 22 KILL = 7, 23 EXTRACT_SUBREG = 8, 24 INSERT_SUBREG = 9, 25 IMPLICIT_DEF = 10, 26 SUBREG_TO_REG = 11, 27 COPY_TO_REGCLASS = 12, 28 DBG_VALUE = 13, 29 DBG_LABEL = 14, 30 REG_SEQUENCE = 15, 31 COPY = 16, 32 BUNDLE = 17, 33 LIFETIME_START = 18, 34 LIFETIME_END = 19, 35 STACKMAP = 20, 36 FENTRY_CALL = 21, 37 PATCHPOINT = 22, 38 LOAD_STACK_GUARD = 23, 39 STATEPOINT = 24, 40 LOCAL_ESCAPE = 25, 41 FAULTING_OP = 26, 42 PATCHABLE_OP = 27, 43 PATCHABLE_FUNCTION_ENTER = 28, 44 PATCHABLE_RET = 29, 45 PATCHABLE_FUNCTION_EXIT = 30, 46 PATCHABLE_TAIL_CALL = 31, 47 PATCHABLE_EVENT_CALL = 32, 48 PATCHABLE_TYPED_EVENT_CALL = 33, 49 ICALL_BRANCH_FUNNEL = 34, 50 G_ADD = 35, 51 G_SUB = 36, 52 G_MUL = 37, 53 G_SDIV = 38, 54 G_UDIV = 39, 55 G_SREM = 40, 56 G_UREM = 41, 57 G_AND = 42, 58 G_OR = 43, 59 G_XOR = 44, 60 G_IMPLICIT_DEF = 45, 61 G_PHI = 46, 62 G_FRAME_INDEX = 47, 63 G_GLOBAL_VALUE = 48, 64 G_EXTRACT = 49, 65 G_UNMERGE_VALUES = 50, 66 G_INSERT = 51, 67 G_MERGE_VALUES = 52, 68 G_BUILD_VECTOR = 53, 69 G_BUILD_VECTOR_TRUNC = 54, 70 G_CONCAT_VECTORS = 55, 71 G_PTRTOINT = 56, 72 G_INTTOPTR = 57, 73 G_BITCAST = 58, 74 G_INTRINSIC_TRUNC = 59, 75 G_INTRINSIC_ROUND = 60, 76 G_READCYCLECOUNTER = 61, 77 G_LOAD = 62, 78 G_SEXTLOAD = 63, 79 G_ZEXTLOAD = 64, 80 G_INDEXED_LOAD = 65, 81 G_INDEXED_SEXTLOAD = 66, 82 G_INDEXED_ZEXTLOAD = 67, 83 G_STORE = 68, 84 G_INDEXED_STORE = 69, 85 G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70, 86 G_ATOMIC_CMPXCHG = 71, 87 G_ATOMICRMW_XCHG = 72, 88 G_ATOMICRMW_ADD = 73, 89 G_ATOMICRMW_SUB = 74, 90 G_ATOMICRMW_AND = 75, 91 G_ATOMICRMW_NAND = 76, 92 G_ATOMICRMW_OR = 77, 93 G_ATOMICRMW_XOR = 78, 94 G_ATOMICRMW_MAX = 79, 95 G_ATOMICRMW_MIN = 80, 96 G_ATOMICRMW_UMAX = 81, 97 G_ATOMICRMW_UMIN = 82, 98 G_ATOMICRMW_FADD = 83, 99 G_ATOMICRMW_FSUB = 84, 100 G_FENCE = 85, 101 G_BRCOND = 86, 102 G_BRINDIRECT = 87, 103 G_INTRINSIC = 88, 104 G_INTRINSIC_W_SIDE_EFFECTS = 89, 105 G_ANYEXT = 90, 106 G_TRUNC = 91, 107 G_CONSTANT = 92, 108 G_FCONSTANT = 93, 109 G_VASTART = 94, 110 G_VAARG = 95, 111 G_SEXT = 96, 112 G_SEXT_INREG = 97, 113 G_ZEXT = 98, 114 G_SHL = 99, 115 G_LSHR = 100, 116 G_ASHR = 101, 117 G_ICMP = 102, 118 G_FCMP = 103, 119 G_SELECT = 104, 120 G_UADDO = 105, 121 G_UADDE = 106, 122 G_USUBO = 107, 123 G_USUBE = 108, 124 G_SADDO = 109, 125 G_SADDE = 110, 126 G_SSUBO = 111, 127 G_SSUBE = 112, 128 G_UMULO = 113, 129 G_SMULO = 114, 130 G_UMULH = 115, 131 G_SMULH = 116, 132 G_FADD = 117, 133 G_FSUB = 118, 134 G_FMUL = 119, 135 G_FMA = 120, 136 G_FMAD = 121, 137 G_FDIV = 122, 138 G_FREM = 123, 139 G_FPOW = 124, 140 G_FEXP = 125, 141 G_FEXP2 = 126, 142 G_FLOG = 127, 143 G_FLOG2 = 128, 144 G_FLOG10 = 129, 145 G_FNEG = 130, 146 G_FPEXT = 131, 147 G_FPTRUNC = 132, 148 G_FPTOSI = 133, 149 G_FPTOUI = 134, 150 G_SITOFP = 135, 151 G_UITOFP = 136, 152 G_FABS = 137, 153 G_FCOPYSIGN = 138, 154 G_FCANONICALIZE = 139, 155 G_FMINNUM = 140, 156 G_FMAXNUM = 141, 157 G_FMINNUM_IEEE = 142, 158 G_FMAXNUM_IEEE = 143, 159 G_FMINIMUM = 144, 160 G_FMAXIMUM = 145, 161 G_PTR_ADD = 146, 162 G_PTR_MASK = 147, 163 G_SMIN = 148, 164 G_SMAX = 149, 165 G_UMIN = 150, 166 G_UMAX = 151, 167 G_BR = 152, 168 G_BRJT = 153, 169 G_INSERT_VECTOR_ELT = 154, 170 G_EXTRACT_VECTOR_ELT = 155, 171 G_SHUFFLE_VECTOR = 156, 172 G_CTTZ = 157, 173 G_CTTZ_ZERO_UNDEF = 158, 174 G_CTLZ = 159, 175 G_CTLZ_ZERO_UNDEF = 160, 176 G_CTPOP = 161, 177 G_BSWAP = 162, 178 G_BITREVERSE = 163, 179 G_FCEIL = 164, 180 G_FCOS = 165, 181 G_FSIN = 166, 182 G_FSQRT = 167, 183 G_FFLOOR = 168, 184 G_FRINT = 169, 185 G_FNEARBYINT = 170, 186 G_ADDRSPACE_CAST = 171, 187 G_BLOCK_ADDR = 172, 188 G_JUMP_TABLE = 173, 189 G_DYN_STACKALLOC = 174, 190 G_READ_REGISTER = 175, 191 G_WRITE_REGISTER = 176, 192 ABSMacro = 177, 193 ADJCALLSTACKDOWN = 178, 194 ADJCALLSTACKUP = 179, 195 AND_V_D_PSEUDO = 180, 196 AND_V_H_PSEUDO = 181, 197 AND_V_W_PSEUDO = 182, 198 ATOMIC_CMP_SWAP_I16 = 183, 199 ATOMIC_CMP_SWAP_I16_POSTRA = 184, 200 ATOMIC_CMP_SWAP_I32 = 185, 201 ATOMIC_CMP_SWAP_I32_POSTRA = 186, 202 ATOMIC_CMP_SWAP_I64 = 187, 203 ATOMIC_CMP_SWAP_I64_POSTRA = 188, 204 ATOMIC_CMP_SWAP_I8 = 189, 205 ATOMIC_CMP_SWAP_I8_POSTRA = 190, 206 ATOMIC_LOAD_ADD_I16 = 191, 207 ATOMIC_LOAD_ADD_I16_POSTRA = 192, 208 ATOMIC_LOAD_ADD_I32 = 193, 209 ATOMIC_LOAD_ADD_I32_POSTRA = 194, 210 ATOMIC_LOAD_ADD_I64 = 195, 211 ATOMIC_LOAD_ADD_I64_POSTRA = 196, 212 ATOMIC_LOAD_ADD_I8 = 197, 213 ATOMIC_LOAD_ADD_I8_POSTRA = 198, 214 ATOMIC_LOAD_AND_I16 = 199, 215 ATOMIC_LOAD_AND_I16_POSTRA = 200, 216 ATOMIC_LOAD_AND_I32 = 201, 217 ATOMIC_LOAD_AND_I32_POSTRA = 202, 218 ATOMIC_LOAD_AND_I64 = 203, 219 ATOMIC_LOAD_AND_I64_POSTRA = 204, 220 ATOMIC_LOAD_AND_I8 = 205, 221 ATOMIC_LOAD_AND_I8_POSTRA = 206, 222 ATOMIC_LOAD_MAX_I16 = 207, 223 ATOMIC_LOAD_MAX_I16_POSTRA = 208, 224 ATOMIC_LOAD_MAX_I32 = 209, 225 ATOMIC_LOAD_MAX_I32_POSTRA = 210, 226 ATOMIC_LOAD_MAX_I64 = 211, 227 ATOMIC_LOAD_MAX_I64_POSTRA = 212, 228 ATOMIC_LOAD_MAX_I8 = 213, 229 ATOMIC_LOAD_MAX_I8_POSTRA = 214, 230 ATOMIC_LOAD_MIN_I16 = 215, 231 ATOMIC_LOAD_MIN_I16_POSTRA = 216, 232 ATOMIC_LOAD_MIN_I32 = 217, 233 ATOMIC_LOAD_MIN_I32_POSTRA = 218, 234 ATOMIC_LOAD_MIN_I64 = 219, 235 ATOMIC_LOAD_MIN_I64_POSTRA = 220, 236 ATOMIC_LOAD_MIN_I8 = 221, 237 ATOMIC_LOAD_MIN_I8_POSTRA = 222, 238 ATOMIC_LOAD_NAND_I16 = 223, 239 ATOMIC_LOAD_NAND_I16_POSTRA = 224, 240 ATOMIC_LOAD_NAND_I32 = 225, 241 ATOMIC_LOAD_NAND_I32_POSTRA = 226, 242 ATOMIC_LOAD_NAND_I64 = 227, 243 ATOMIC_LOAD_NAND_I64_POSTRA = 228, 244 ATOMIC_LOAD_NAND_I8 = 229, 245 ATOMIC_LOAD_NAND_I8_POSTRA = 230, 246 ATOMIC_LOAD_OR_I16 = 231, 247 ATOMIC_LOAD_OR_I16_POSTRA = 232, 248 ATOMIC_LOAD_OR_I32 = 233, 249 ATOMIC_LOAD_OR_I32_POSTRA = 234, 250 ATOMIC_LOAD_OR_I64 = 235, 251 ATOMIC_LOAD_OR_I64_POSTRA = 236, 252 ATOMIC_LOAD_OR_I8 = 237, 253 ATOMIC_LOAD_OR_I8_POSTRA = 238, 254 ATOMIC_LOAD_SUB_I16 = 239, 255 ATOMIC_LOAD_SUB_I16_POSTRA = 240, 256 ATOMIC_LOAD_SUB_I32 = 241, 257 ATOMIC_LOAD_SUB_I32_POSTRA = 242, 258 ATOMIC_LOAD_SUB_I64 = 243, 259 ATOMIC_LOAD_SUB_I64_POSTRA = 244, 260 ATOMIC_LOAD_SUB_I8 = 245, 261 ATOMIC_LOAD_SUB_I8_POSTRA = 246, 262 ATOMIC_LOAD_UMAX_I16 = 247, 263 ATOMIC_LOAD_UMAX_I16_POSTRA = 248, 264 ATOMIC_LOAD_UMAX_I32 = 249, 265 ATOMIC_LOAD_UMAX_I32_POSTRA = 250, 266 ATOMIC_LOAD_UMAX_I64 = 251, 267 ATOMIC_LOAD_UMAX_I64_POSTRA = 252, 268 ATOMIC_LOAD_UMAX_I8 = 253, 269 ATOMIC_LOAD_UMAX_I8_POSTRA = 254, 270 ATOMIC_LOAD_UMIN_I16 = 255, 271 ATOMIC_LOAD_UMIN_I16_POSTRA = 256, 272 ATOMIC_LOAD_UMIN_I32 = 257, 273 ATOMIC_LOAD_UMIN_I32_POSTRA = 258, 274 ATOMIC_LOAD_UMIN_I64 = 259, 275 ATOMIC_LOAD_UMIN_I64_POSTRA = 260, 276 ATOMIC_LOAD_UMIN_I8 = 261, 277 ATOMIC_LOAD_UMIN_I8_POSTRA = 262, 278 ATOMIC_LOAD_XOR_I16 = 263, 279 ATOMIC_LOAD_XOR_I16_POSTRA = 264, 280 ATOMIC_LOAD_XOR_I32 = 265, 281 ATOMIC_LOAD_XOR_I32_POSTRA = 266, 282 ATOMIC_LOAD_XOR_I64 = 267, 283 ATOMIC_LOAD_XOR_I64_POSTRA = 268, 284 ATOMIC_LOAD_XOR_I8 = 269, 285 ATOMIC_LOAD_XOR_I8_POSTRA = 270, 286 ATOMIC_SWAP_I16 = 271, 287 ATOMIC_SWAP_I16_POSTRA = 272, 288 ATOMIC_SWAP_I32 = 273, 289 ATOMIC_SWAP_I32_POSTRA = 274, 290 ATOMIC_SWAP_I64 = 275, 291 ATOMIC_SWAP_I64_POSTRA = 276, 292 ATOMIC_SWAP_I8 = 277, 293 ATOMIC_SWAP_I8_POSTRA = 278, 294 B = 279, 295 BAL_BR = 280, 296 BAL_BR_MM = 281, 297 BEQLImmMacro = 282, 298 BGE = 283, 299 BGEImmMacro = 284, 300 BGEL = 285, 301 BGELImmMacro = 286, 302 BGEU = 287, 303 BGEUImmMacro = 288, 304 BGEUL = 289, 305 BGEULImmMacro = 290, 306 BGT = 291, 307 BGTImmMacro = 292, 308 BGTL = 293, 309 BGTLImmMacro = 294, 310 BGTU = 295, 311 BGTUImmMacro = 296, 312 BGTUL = 297, 313 BGTULImmMacro = 298, 314 BLE = 299, 315 BLEImmMacro = 300, 316 BLEL = 301, 317 BLELImmMacro = 302, 318 BLEU = 303, 319 BLEUImmMacro = 304, 320 BLEUL = 305, 321 BLEULImmMacro = 306, 322 BLT = 307, 323 BLTImmMacro = 308, 324 BLTL = 309, 325 BLTLImmMacro = 310, 326 BLTU = 311, 327 BLTUImmMacro = 312, 328 BLTUL = 313, 329 BLTULImmMacro = 314, 330 BNELImmMacro = 315, 331 BPOSGE32_PSEUDO = 316, 332 BSEL_D_PSEUDO = 317, 333 BSEL_FD_PSEUDO = 318, 334 BSEL_FW_PSEUDO = 319, 335 BSEL_H_PSEUDO = 320, 336 BSEL_W_PSEUDO = 321, 337 B_MM = 322, 338 B_MMR6_Pseudo = 323, 339 B_MM_Pseudo = 324, 340 BeqImm = 325, 341 BneImm = 326, 342 BteqzT8CmpX16 = 327, 343 BteqzT8CmpiX16 = 328, 344 BteqzT8SltX16 = 329, 345 BteqzT8SltiX16 = 330, 346 BteqzT8SltiuX16 = 331, 347 BteqzT8SltuX16 = 332, 348 BtnezT8CmpX16 = 333, 349 BtnezT8CmpiX16 = 334, 350 BtnezT8SltX16 = 335, 351 BtnezT8SltiX16 = 336, 352 BtnezT8SltiuX16 = 337, 353 BtnezT8SltuX16 = 338, 354 BuildPairF64 = 339, 355 BuildPairF64_64 = 340, 356 CFTC1 = 341, 357 CONSTPOOL_ENTRY = 342, 358 COPY_FD_PSEUDO = 343, 359 COPY_FW_PSEUDO = 344, 360 CTTC1 = 345, 361 Constant32 = 346, 362 DMULImmMacro = 347, 363 DMULMacro = 348, 364 DMULOMacro = 349, 365 DMULOUMacro = 350, 366 DROL = 351, 367 DROLImm = 352, 368 DROR = 353, 369 DRORImm = 354, 370 DSDivIMacro = 355, 371 DSDivMacro = 356, 372 DSRemIMacro = 357, 373 DSRemMacro = 358, 374 DUDivIMacro = 359, 375 DUDivMacro = 360, 376 DURemIMacro = 361, 377 DURemMacro = 362, 378 ERet = 363, 379 ExtractElementF64 = 364, 380 ExtractElementF64_64 = 365, 381 FABS_D = 366, 382 FABS_W = 367, 383 FEXP2_D_1_PSEUDO = 368, 384 FEXP2_W_1_PSEUDO = 369, 385 FILL_FD_PSEUDO = 370, 386 FILL_FW_PSEUDO = 371, 387 GotPrologue16 = 372, 388 INSERT_B_VIDX64_PSEUDO = 373, 389 INSERT_B_VIDX_PSEUDO = 374, 390 INSERT_D_VIDX64_PSEUDO = 375, 391 INSERT_D_VIDX_PSEUDO = 376, 392 INSERT_FD_PSEUDO = 377, 393 INSERT_FD_VIDX64_PSEUDO = 378, 394 INSERT_FD_VIDX_PSEUDO = 379, 395 INSERT_FW_PSEUDO = 380, 396 INSERT_FW_VIDX64_PSEUDO = 381, 397 INSERT_FW_VIDX_PSEUDO = 382, 398 INSERT_H_VIDX64_PSEUDO = 383, 399 INSERT_H_VIDX_PSEUDO = 384, 400 INSERT_W_VIDX64_PSEUDO = 385, 401 INSERT_W_VIDX_PSEUDO = 386, 402 JALR64Pseudo = 387, 403 JALRHB64Pseudo = 388, 404 JALRHBPseudo = 389, 405 JALRPseudo = 390, 406 JAL_MMR6 = 391, 407 JalOneReg = 392, 408 JalTwoReg = 393, 409 LDMacro = 394, 410 LD_F16 = 395, 411 LOAD_ACC128 = 396, 412 LOAD_ACC64 = 397, 413 LOAD_ACC64DSP = 398, 414 LOAD_CCOND_DSP = 399, 415 LONG_BRANCH_ADDiu = 400, 416 LONG_BRANCH_ADDiu2Op = 401, 417 LONG_BRANCH_DADDiu = 402, 418 LONG_BRANCH_DADDiu2Op = 403, 419 LONG_BRANCH_LUi = 404, 420 LONG_BRANCH_LUi2Op = 405, 421 LONG_BRANCH_LUi2Op_64 = 406, 422 LWM_MM = 407, 423 LoadAddrImm32 = 408, 424 LoadAddrImm64 = 409, 425 LoadAddrReg32 = 410, 426 LoadAddrReg64 = 411, 427 LoadImm32 = 412, 428 LoadImm64 = 413, 429 LoadImmDoubleFGR = 414, 430 LoadImmDoubleFGR_32 = 415, 431 LoadImmDoubleGPR = 416, 432 LoadImmSingleFGR = 417, 433 LoadImmSingleGPR = 418, 434 LwConstant32 = 419, 435 MFTACX = 420, 436 MFTC0 = 421, 437 MFTC1 = 422, 438 MFTDSP = 423, 439 MFTGPR = 424, 440 MFTHC1 = 425, 441 MFTHI = 426, 442 MFTLO = 427, 443 MIPSeh_return32 = 428, 444 MIPSeh_return64 = 429, 445 MSA_FP_EXTEND_D_PSEUDO = 430, 446 MSA_FP_EXTEND_W_PSEUDO = 431, 447 MSA_FP_ROUND_D_PSEUDO = 432, 448 MSA_FP_ROUND_W_PSEUDO = 433, 449 MTTACX = 434, 450 MTTC0 = 435, 451 MTTC1 = 436, 452 MTTDSP = 437, 453 MTTGPR = 438, 454 MTTHC1 = 439, 455 MTTHI = 440, 456 MTTLO = 441, 457 MULImmMacro = 442, 458 MULOMacro = 443, 459 MULOUMacro = 444, 460 MultRxRy16 = 445, 461 MultRxRyRz16 = 446, 462 MultuRxRy16 = 447, 463 MultuRxRyRz16 = 448, 464 NOP = 449, 465 NORImm = 450, 466 NORImm64 = 451, 467 NOR_V_D_PSEUDO = 452, 468 NOR_V_H_PSEUDO = 453, 469 NOR_V_W_PSEUDO = 454, 470 OR_V_D_PSEUDO = 455, 471 OR_V_H_PSEUDO = 456, 472 OR_V_W_PSEUDO = 457, 473 PseudoCMPU_EQ_QB = 458, 474 PseudoCMPU_LE_QB = 459, 475 PseudoCMPU_LT_QB = 460, 476 PseudoCMP_EQ_PH = 461, 477 PseudoCMP_LE_PH = 462, 478 PseudoCMP_LT_PH = 463, 479 PseudoCVT_D32_W = 464, 480 PseudoCVT_D64_L = 465, 481 PseudoCVT_D64_W = 466, 482 PseudoCVT_S_L = 467, 483 PseudoCVT_S_W = 468, 484 PseudoDMULT = 469, 485 PseudoDMULTu = 470, 486 PseudoDSDIV = 471, 487 PseudoDUDIV = 472, 488 PseudoD_SELECT_I = 473, 489 PseudoD_SELECT_I64 = 474, 490 PseudoIndirectBranch = 475, 491 PseudoIndirectBranch64 = 476, 492 PseudoIndirectBranch64R6 = 477, 493 PseudoIndirectBranchR6 = 478, 494 PseudoIndirectBranch_MM = 479, 495 PseudoIndirectBranch_MMR6 = 480, 496 PseudoIndirectHazardBranch = 481, 497 PseudoIndirectHazardBranch64 = 482, 498 PseudoIndrectHazardBranch64R6 = 483, 499 PseudoIndrectHazardBranchR6 = 484, 500 PseudoMADD = 485, 501 PseudoMADDU = 486, 502 PseudoMADDU_MM = 487, 503 PseudoMADD_MM = 488, 504 PseudoMFHI = 489, 505 PseudoMFHI64 = 490, 506 PseudoMFHI_MM = 491, 507 PseudoMFLO = 492, 508 PseudoMFLO64 = 493, 509 PseudoMFLO_MM = 494, 510 PseudoMSUB = 495, 511 PseudoMSUBU = 496, 512 PseudoMSUBU_MM = 497, 513 PseudoMSUB_MM = 498, 514 PseudoMTLOHI = 499, 515 PseudoMTLOHI64 = 500, 516 PseudoMTLOHI_DSP = 501, 517 PseudoMTLOHI_MM = 502, 518 PseudoMULT = 503, 519 PseudoMULT_MM = 504, 520 PseudoMULTu = 505, 521 PseudoMULTu_MM = 506, 522 PseudoPICK_PH = 507, 523 PseudoPICK_QB = 508, 524 PseudoReturn = 509, 525 PseudoReturn64 = 510, 526 PseudoSDIV = 511, 527 PseudoSELECTFP_F_D32 = 512, 528 PseudoSELECTFP_F_D64 = 513, 529 PseudoSELECTFP_F_I = 514, 530 PseudoSELECTFP_F_I64 = 515, 531 PseudoSELECTFP_F_S = 516, 532 PseudoSELECTFP_T_D32 = 517, 533 PseudoSELECTFP_T_D64 = 518, 534 PseudoSELECTFP_T_I = 519, 535 PseudoSELECTFP_T_I64 = 520, 536 PseudoSELECTFP_T_S = 521, 537 PseudoSELECT_D32 = 522, 538 PseudoSELECT_D64 = 523, 539 PseudoSELECT_I = 524, 540 PseudoSELECT_I64 = 525, 541 PseudoSELECT_S = 526, 542 PseudoTRUNC_W_D = 527, 543 PseudoTRUNC_W_D32 = 528, 544 PseudoTRUNC_W_S = 529, 545 PseudoUDIV = 530, 546 ROL = 531, 547 ROLImm = 532, 548 ROR = 533, 549 RORImm = 534, 550 RetRA = 535, 551 RetRA16 = 536, 552 SDC1_M1 = 537, 553 SDIV_MM_Pseudo = 538, 554 SDMacro = 539, 555 SDivIMacro = 540, 556 SDivMacro = 541, 557 SEQIMacro = 542, 558 SEQMacro = 543, 559 SGE = 544, 560 SGEImm = 545, 561 SGEImm64 = 546, 562 SGEU = 547, 563 SGEUImm = 548, 564 SGEUImm64 = 549, 565 SGTImm = 550, 566 SGTImm64 = 551, 567 SGTUImm = 552, 568 SGTUImm64 = 553, 569 SLTImm64 = 554, 570 SLTUImm64 = 555, 571 SNZ_B_PSEUDO = 556, 572 SNZ_D_PSEUDO = 557, 573 SNZ_H_PSEUDO = 558, 574 SNZ_V_PSEUDO = 559, 575 SNZ_W_PSEUDO = 560, 576 SRemIMacro = 561, 577 SRemMacro = 562, 578 STORE_ACC128 = 563, 579 STORE_ACC64 = 564, 580 STORE_ACC64DSP = 565, 581 STORE_CCOND_DSP = 566, 582 ST_F16 = 567, 583 SWM_MM = 568, 584 SZ_B_PSEUDO = 569, 585 SZ_D_PSEUDO = 570, 586 SZ_H_PSEUDO = 571, 587 SZ_V_PSEUDO = 572, 588 SZ_W_PSEUDO = 573, 589 SaaAddr = 574, 590 SaadAddr = 575, 591 SelBeqZ = 576, 592 SelBneZ = 577, 593 SelTBteqZCmp = 578, 594 SelTBteqZCmpi = 579, 595 SelTBteqZSlt = 580, 596 SelTBteqZSlti = 581, 597 SelTBteqZSltiu = 582, 598 SelTBteqZSltu = 583, 599 SelTBtneZCmp = 584, 600 SelTBtneZCmpi = 585, 601 SelTBtneZSlt = 586, 602 SelTBtneZSlti = 587, 603 SelTBtneZSltiu = 588, 604 SelTBtneZSltu = 589, 605 SltCCRxRy16 = 590, 606 SltiCCRxImmX16 = 591, 607 SltiuCCRxImmX16 = 592, 608 SltuCCRxRy16 = 593, 609 SltuRxRyRz16 = 594, 610 TAILCALL = 595, 611 TAILCALL64R6REG = 596, 612 TAILCALLHB64R6REG = 597, 613 TAILCALLHBR6REG = 598, 614 TAILCALLR6REG = 599, 615 TAILCALLREG = 600, 616 TAILCALLREG64 = 601, 617 TAILCALLREGHB = 602, 618 TAILCALLREGHB64 = 603, 619 TAILCALLREG_MM = 604, 620 TAILCALLREG_MMR6 = 605, 621 TAILCALL_MM = 606, 622 TAILCALL_MMR6 = 607, 623 TRAP = 608, 624 TRAP_MM = 609, 625 UDIV_MM_Pseudo = 610, 626 UDivIMacro = 611, 627 UDivMacro = 612, 628 URemIMacro = 613, 629 URemMacro = 614, 630 Ulh = 615, 631 Ulhu = 616, 632 Ulw = 617, 633 Ush = 618, 634 Usw = 619, 635 XOR_V_D_PSEUDO = 620, 636 XOR_V_H_PSEUDO = 621, 637 XOR_V_W_PSEUDO = 622, 638 ABSQ_S_PH = 623, 639 ABSQ_S_PH_MM = 624, 640 ABSQ_S_QB = 625, 641 ABSQ_S_QB_MMR2 = 626, 642 ABSQ_S_W = 627, 643 ABSQ_S_W_MM = 628, 644 ADD = 629, 645 ADDIUPC = 630, 646 ADDIUPC_MM = 631, 647 ADDIUPC_MMR6 = 632, 648 ADDIUR1SP_MM = 633, 649 ADDIUR2_MM = 634, 650 ADDIUS5_MM = 635, 651 ADDIUSP_MM = 636, 652 ADDIU_MMR6 = 637, 653 ADDQH_PH = 638, 654 ADDQH_PH_MMR2 = 639, 655 ADDQH_R_PH = 640, 656 ADDQH_R_PH_MMR2 = 641, 657 ADDQH_R_W = 642, 658 ADDQH_R_W_MMR2 = 643, 659 ADDQH_W = 644, 660 ADDQH_W_MMR2 = 645, 661 ADDQ_PH = 646, 662 ADDQ_PH_MM = 647, 663 ADDQ_S_PH = 648, 664 ADDQ_S_PH_MM = 649, 665 ADDQ_S_W = 650, 666 ADDQ_S_W_MM = 651, 667 ADDSC = 652, 668 ADDSC_MM = 653, 669 ADDS_A_B = 654, 670 ADDS_A_D = 655, 671 ADDS_A_H = 656, 672 ADDS_A_W = 657, 673 ADDS_S_B = 658, 674 ADDS_S_D = 659, 675 ADDS_S_H = 660, 676 ADDS_S_W = 661, 677 ADDS_U_B = 662, 678 ADDS_U_D = 663, 679 ADDS_U_H = 664, 680 ADDS_U_W = 665, 681 ADDU16_MM = 666, 682 ADDU16_MMR6 = 667, 683 ADDUH_QB = 668, 684 ADDUH_QB_MMR2 = 669, 685 ADDUH_R_QB = 670, 686 ADDUH_R_QB_MMR2 = 671, 687 ADDU_MMR6 = 672, 688 ADDU_PH = 673, 689 ADDU_PH_MMR2 = 674, 690 ADDU_QB = 675, 691 ADDU_QB_MM = 676, 692 ADDU_S_PH = 677, 693 ADDU_S_PH_MMR2 = 678, 694 ADDU_S_QB = 679, 695 ADDU_S_QB_MM = 680, 696 ADDVI_B = 681, 697 ADDVI_D = 682, 698 ADDVI_H = 683, 699 ADDVI_W = 684, 700 ADDV_B = 685, 701 ADDV_D = 686, 702 ADDV_H = 687, 703 ADDV_W = 688, 704 ADDWC = 689, 705 ADDWC_MM = 690, 706 ADD_A_B = 691, 707 ADD_A_D = 692, 708 ADD_A_H = 693, 709 ADD_A_W = 694, 710 ADD_MM = 695, 711 ADD_MMR6 = 696, 712 ADDi = 697, 713 ADDi_MM = 698, 714 ADDiu = 699, 715 ADDiu_MM = 700, 716 ADDu = 701, 717 ADDu_MM = 702, 718 ALIGN = 703, 719 ALIGN_MMR6 = 704, 720 ALUIPC = 705, 721 ALUIPC_MMR6 = 706, 722 AND = 707, 723 AND16_MM = 708, 724 AND16_MMR6 = 709, 725 AND64 = 710, 726 ANDI16_MM = 711, 727 ANDI16_MMR6 = 712, 728 ANDI_B = 713, 729 ANDI_MMR6 = 714, 730 AND_MM = 715, 731 AND_MMR6 = 716, 732 AND_V = 717, 733 ANDi = 718, 734 ANDi64 = 719, 735 ANDi_MM = 720, 736 APPEND = 721, 737 APPEND_MMR2 = 722, 738 ASUB_S_B = 723, 739 ASUB_S_D = 724, 740 ASUB_S_H = 725, 741 ASUB_S_W = 726, 742 ASUB_U_B = 727, 743 ASUB_U_D = 728, 744 ASUB_U_H = 729, 745 ASUB_U_W = 730, 746 AUI = 731, 747 AUIPC = 732, 748 AUIPC_MMR6 = 733, 749 AUI_MMR6 = 734, 750 AVER_S_B = 735, 751 AVER_S_D = 736, 752 AVER_S_H = 737, 753 AVER_S_W = 738, 754 AVER_U_B = 739, 755 AVER_U_D = 740, 756 AVER_U_H = 741, 757 AVER_U_W = 742, 758 AVE_S_B = 743, 759 AVE_S_D = 744, 760 AVE_S_H = 745, 761 AVE_S_W = 746, 762 AVE_U_B = 747, 763 AVE_U_D = 748, 764 AVE_U_H = 749, 765 AVE_U_W = 750, 766 AddiuRxImmX16 = 751, 767 AddiuRxPcImmX16 = 752, 768 AddiuRxRxImm16 = 753, 769 AddiuRxRxImmX16 = 754, 770 AddiuRxRyOffMemX16 = 755, 771 AddiuSpImm16 = 756, 772 AddiuSpImmX16 = 757, 773 AdduRxRyRz16 = 758, 774 AndRxRxRy16 = 759, 775 B16_MM = 760, 776 BADDu = 761, 777 BAL = 762, 778 BALC = 763, 779 BALC_MMR6 = 764, 780 BALIGN = 765, 781 BALIGN_MMR2 = 766, 782 BBIT0 = 767, 783 BBIT032 = 768, 784 BBIT1 = 769, 785 BBIT132 = 770, 786 BC = 771, 787 BC16_MMR6 = 772, 788 BC1EQZ = 773, 789 BC1EQZC_MMR6 = 774, 790 BC1F = 775, 791 BC1FL = 776, 792 BC1F_MM = 777, 793 BC1NEZ = 778, 794 BC1NEZC_MMR6 = 779, 795 BC1T = 780, 796 BC1TL = 781, 797 BC1T_MM = 782, 798 BC2EQZ = 783, 799 BC2EQZC_MMR6 = 784, 800 BC2NEZ = 785, 801 BC2NEZC_MMR6 = 786, 802 BCLRI_B = 787, 803 BCLRI_D = 788, 804 BCLRI_H = 789, 805 BCLRI_W = 790, 806 BCLR_B = 791, 807 BCLR_D = 792, 808 BCLR_H = 793, 809 BCLR_W = 794, 810 BC_MMR6 = 795, 811 BEQ = 796, 812 BEQ64 = 797, 813 BEQC = 798, 814 BEQC64 = 799, 815 BEQC_MMR6 = 800, 816 BEQL = 801, 817 BEQZ16_MM = 802, 818 BEQZALC = 803, 819 BEQZALC_MMR6 = 804, 820 BEQZC = 805, 821 BEQZC16_MMR6 = 806, 822 BEQZC64 = 807, 823 BEQZC_MM = 808, 824 BEQZC_MMR6 = 809, 825 BEQ_MM = 810, 826 BGEC = 811, 827 BGEC64 = 812, 828 BGEC_MMR6 = 813, 829 BGEUC = 814, 830 BGEUC64 = 815, 831 BGEUC_MMR6 = 816, 832 BGEZ = 817, 833 BGEZ64 = 818, 834 BGEZAL = 819, 835 BGEZALC = 820, 836 BGEZALC_MMR6 = 821, 837 BGEZALL = 822, 838 BGEZALS_MM = 823, 839 BGEZAL_MM = 824, 840 BGEZC = 825, 841 BGEZC64 = 826, 842 BGEZC_MMR6 = 827, 843 BGEZL = 828, 844 BGEZ_MM = 829, 845 BGTZ = 830, 846 BGTZ64 = 831, 847 BGTZALC = 832, 848 BGTZALC_MMR6 = 833, 849 BGTZC = 834, 850 BGTZC64 = 835, 851 BGTZC_MMR6 = 836, 852 BGTZL = 837, 853 BGTZ_MM = 838, 854 BINSLI_B = 839, 855 BINSLI_D = 840, 856 BINSLI_H = 841, 857 BINSLI_W = 842, 858 BINSL_B = 843, 859 BINSL_D = 844, 860 BINSL_H = 845, 861 BINSL_W = 846, 862 BINSRI_B = 847, 863 BINSRI_D = 848, 864 BINSRI_H = 849, 865 BINSRI_W = 850, 866 BINSR_B = 851, 867 BINSR_D = 852, 868 BINSR_H = 853, 869 BINSR_W = 854, 870 BITREV = 855, 871 BITREV_MM = 856, 872 BITSWAP = 857, 873 BITSWAP_MMR6 = 858, 874 BLEZ = 859, 875 BLEZ64 = 860, 876 BLEZALC = 861, 877 BLEZALC_MMR6 = 862, 878 BLEZC = 863, 879 BLEZC64 = 864, 880 BLEZC_MMR6 = 865, 881 BLEZL = 866, 882 BLEZ_MM = 867, 883 BLTC = 868, 884 BLTC64 = 869, 885 BLTC_MMR6 = 870, 886 BLTUC = 871, 887 BLTUC64 = 872, 888 BLTUC_MMR6 = 873, 889 BLTZ = 874, 890 BLTZ64 = 875, 891 BLTZAL = 876, 892 BLTZALC = 877, 893 BLTZALC_MMR6 = 878, 894 BLTZALL = 879, 895 BLTZALS_MM = 880, 896 BLTZAL_MM = 881, 897 BLTZC = 882, 898 BLTZC64 = 883, 899 BLTZC_MMR6 = 884, 900 BLTZL = 885, 901 BLTZ_MM = 886, 902 BMNZI_B = 887, 903 BMNZ_V = 888, 904 BMZI_B = 889, 905 BMZ_V = 890, 906 BNE = 891, 907 BNE64 = 892, 908 BNEC = 893, 909 BNEC64 = 894, 910 BNEC_MMR6 = 895, 911 BNEGI_B = 896, 912 BNEGI_D = 897, 913 BNEGI_H = 898, 914 BNEGI_W = 899, 915 BNEG_B = 900, 916 BNEG_D = 901, 917 BNEG_H = 902, 918 BNEG_W = 903, 919 BNEL = 904, 920 BNEZ16_MM = 905, 921 BNEZALC = 906, 922 BNEZALC_MMR6 = 907, 923 BNEZC = 908, 924 BNEZC16_MMR6 = 909, 925 BNEZC64 = 910, 926 BNEZC_MM = 911, 927 BNEZC_MMR6 = 912, 928 BNE_MM = 913, 929 BNVC = 914, 930 BNVC_MMR6 = 915, 931 BNZ_B = 916, 932 BNZ_D = 917, 933 BNZ_H = 918, 934 BNZ_V = 919, 935 BNZ_W = 920, 936 BOVC = 921, 937 BOVC_MMR6 = 922, 938 BPOSGE32 = 923, 939 BPOSGE32C_MMR3 = 924, 940 BPOSGE32_MM = 925, 941 BREAK = 926, 942 BREAK16_MM = 927, 943 BREAK16_MMR6 = 928, 944 BREAK_MM = 929, 945 BREAK_MMR6 = 930, 946 BSELI_B = 931, 947 BSEL_V = 932, 948 BSETI_B = 933, 949 BSETI_D = 934, 950 BSETI_H = 935, 951 BSETI_W = 936, 952 BSET_B = 937, 953 BSET_D = 938, 954 BSET_H = 939, 955 BSET_W = 940, 956 BZ_B = 941, 957 BZ_D = 942, 958 BZ_H = 943, 959 BZ_V = 944, 960 BZ_W = 945, 961 BeqzRxImm16 = 946, 962 BeqzRxImmX16 = 947, 963 Bimm16 = 948, 964 BimmX16 = 949, 965 BnezRxImm16 = 950, 966 BnezRxImmX16 = 951, 967 Break16 = 952, 968 Bteqz16 = 953, 969 BteqzX16 = 954, 970 Btnez16 = 955, 971 BtnezX16 = 956, 972 CACHE = 957, 973 CACHEE = 958, 974 CACHEE_MM = 959, 975 CACHE_MM = 960, 976 CACHE_MMR6 = 961, 977 CACHE_R6 = 962, 978 CEIL_L_D64 = 963, 979 CEIL_L_D_MMR6 = 964, 980 CEIL_L_S = 965, 981 CEIL_L_S_MMR6 = 966, 982 CEIL_W_D32 = 967, 983 CEIL_W_D64 = 968, 984 CEIL_W_D_MMR6 = 969, 985 CEIL_W_MM = 970, 986 CEIL_W_S = 971, 987 CEIL_W_S_MM = 972, 988 CEIL_W_S_MMR6 = 973, 989 CEQI_B = 974, 990 CEQI_D = 975, 991 CEQI_H = 976, 992 CEQI_W = 977, 993 CEQ_B = 978, 994 CEQ_D = 979, 995 CEQ_H = 980, 996 CEQ_W = 981, 997 CFC1 = 982, 998 CFC1_MM = 983, 999 CFC2_MM = 984, 1000 CFCMSA = 985, 1001 CINS = 986, 1002 CINS32 = 987, 1003 CINS64_32 = 988, 1004 CINS_i32 = 989, 1005 CLASS_D = 990, 1006 CLASS_D_MMR6 = 991, 1007 CLASS_S = 992, 1008 CLASS_S_MMR6 = 993, 1009 CLEI_S_B = 994, 1010 CLEI_S_D = 995, 1011 CLEI_S_H = 996, 1012 CLEI_S_W = 997, 1013 CLEI_U_B = 998, 1014 CLEI_U_D = 999, 1015 CLEI_U_H = 1000, 1016 CLEI_U_W = 1001, 1017 CLE_S_B = 1002, 1018 CLE_S_D = 1003, 1019 CLE_S_H = 1004, 1020 CLE_S_W = 1005, 1021 CLE_U_B = 1006, 1022 CLE_U_D = 1007, 1023 CLE_U_H = 1008, 1024 CLE_U_W = 1009, 1025 CLO = 1010, 1026 CLO_MM = 1011, 1027 CLO_MMR6 = 1012, 1028 CLO_R6 = 1013, 1029 CLTI_S_B = 1014, 1030 CLTI_S_D = 1015, 1031 CLTI_S_H = 1016, 1032 CLTI_S_W = 1017, 1033 CLTI_U_B = 1018, 1034 CLTI_U_D = 1019, 1035 CLTI_U_H = 1020, 1036 CLTI_U_W = 1021, 1037 CLT_S_B = 1022, 1038 CLT_S_D = 1023, 1039 CLT_S_H = 1024, 1040 CLT_S_W = 1025, 1041 CLT_U_B = 1026, 1042 CLT_U_D = 1027, 1043 CLT_U_H = 1028, 1044 CLT_U_W = 1029, 1045 CLZ = 1030, 1046 CLZ_MM = 1031, 1047 CLZ_MMR6 = 1032, 1048 CLZ_R6 = 1033, 1049 CMPGDU_EQ_QB = 1034, 1050 CMPGDU_EQ_QB_MMR2 = 1035, 1051 CMPGDU_LE_QB = 1036, 1052 CMPGDU_LE_QB_MMR2 = 1037, 1053 CMPGDU_LT_QB = 1038, 1054 CMPGDU_LT_QB_MMR2 = 1039, 1055 CMPGU_EQ_QB = 1040, 1056 CMPGU_EQ_QB_MM = 1041, 1057 CMPGU_LE_QB = 1042, 1058 CMPGU_LE_QB_MM = 1043, 1059 CMPGU_LT_QB = 1044, 1060 CMPGU_LT_QB_MM = 1045, 1061 CMPU_EQ_QB = 1046, 1062 CMPU_EQ_QB_MM = 1047, 1063 CMPU_LE_QB = 1048, 1064 CMPU_LE_QB_MM = 1049, 1065 CMPU_LT_QB = 1050, 1066 CMPU_LT_QB_MM = 1051, 1067 CMP_AF_D_MMR6 = 1052, 1068 CMP_AF_S_MMR6 = 1053, 1069 CMP_EQ_D = 1054, 1070 CMP_EQ_D_MMR6 = 1055, 1071 CMP_EQ_PH = 1056, 1072 CMP_EQ_PH_MM = 1057, 1073 CMP_EQ_S = 1058, 1074 CMP_EQ_S_MMR6 = 1059, 1075 CMP_F_D = 1060, 1076 CMP_F_S = 1061, 1077 CMP_LE_D = 1062, 1078 CMP_LE_D_MMR6 = 1063, 1079 CMP_LE_PH = 1064, 1080 CMP_LE_PH_MM = 1065, 1081 CMP_LE_S = 1066, 1082 CMP_LE_S_MMR6 = 1067, 1083 CMP_LT_D = 1068, 1084 CMP_LT_D_MMR6 = 1069, 1085 CMP_LT_PH = 1070, 1086 CMP_LT_PH_MM = 1071, 1087 CMP_LT_S = 1072, 1088 CMP_LT_S_MMR6 = 1073, 1089 CMP_SAF_D = 1074, 1090 CMP_SAF_D_MMR6 = 1075, 1091 CMP_SAF_S = 1076, 1092 CMP_SAF_S_MMR6 = 1077, 1093 CMP_SEQ_D = 1078, 1094 CMP_SEQ_D_MMR6 = 1079, 1095 CMP_SEQ_S = 1080, 1096 CMP_SEQ_S_MMR6 = 1081, 1097 CMP_SLE_D = 1082, 1098 CMP_SLE_D_MMR6 = 1083, 1099 CMP_SLE_S = 1084, 1100 CMP_SLE_S_MMR6 = 1085, 1101 CMP_SLT_D = 1086, 1102 CMP_SLT_D_MMR6 = 1087, 1103 CMP_SLT_S = 1088, 1104 CMP_SLT_S_MMR6 = 1089, 1105 CMP_SUEQ_D = 1090, 1106 CMP_SUEQ_D_MMR6 = 1091, 1107 CMP_SUEQ_S = 1092, 1108 CMP_SUEQ_S_MMR6 = 1093, 1109 CMP_SULE_D = 1094, 1110 CMP_SULE_D_MMR6 = 1095, 1111 CMP_SULE_S = 1096, 1112 CMP_SULE_S_MMR6 = 1097, 1113 CMP_SULT_D = 1098, 1114 CMP_SULT_D_MMR6 = 1099, 1115 CMP_SULT_S = 1100, 1116 CMP_SULT_S_MMR6 = 1101, 1117 CMP_SUN_D = 1102, 1118 CMP_SUN_D_MMR6 = 1103, 1119 CMP_SUN_S = 1104, 1120 CMP_SUN_S_MMR6 = 1105, 1121 CMP_UEQ_D = 1106, 1122 CMP_UEQ_D_MMR6 = 1107, 1123 CMP_UEQ_S = 1108, 1124 CMP_UEQ_S_MMR6 = 1109, 1125 CMP_ULE_D = 1110, 1126 CMP_ULE_D_MMR6 = 1111, 1127 CMP_ULE_S = 1112, 1128 CMP_ULE_S_MMR6 = 1113, 1129 CMP_ULT_D = 1114, 1130 CMP_ULT_D_MMR6 = 1115, 1131 CMP_ULT_S = 1116, 1132 CMP_ULT_S_MMR6 = 1117, 1133 CMP_UN_D = 1118, 1134 CMP_UN_D_MMR6 = 1119, 1135 CMP_UN_S = 1120, 1136 CMP_UN_S_MMR6 = 1121, 1137 COPY_S_B = 1122, 1138 COPY_S_D = 1123, 1139 COPY_S_H = 1124, 1140 COPY_S_W = 1125, 1141 COPY_U_B = 1126, 1142 COPY_U_H = 1127, 1143 COPY_U_W = 1128, 1144 CRC32B = 1129, 1145 CRC32CB = 1130, 1146 CRC32CD = 1131, 1147 CRC32CH = 1132, 1148 CRC32CW = 1133, 1149 CRC32D = 1134, 1150 CRC32H = 1135, 1151 CRC32W = 1136, 1152 CTC1 = 1137, 1153 CTC1_MM = 1138, 1154 CTC2_MM = 1139, 1155 CTCMSA = 1140, 1156 CVT_D32_S = 1141, 1157 CVT_D32_S_MM = 1142, 1158 CVT_D32_W = 1143, 1159 CVT_D32_W_MM = 1144, 1160 CVT_D64_L = 1145, 1161 CVT_D64_S = 1146, 1162 CVT_D64_S_MM = 1147, 1163 CVT_D64_W = 1148, 1164 CVT_D64_W_MM = 1149, 1165 CVT_D_L_MMR6 = 1150, 1166 CVT_L_D64 = 1151, 1167 CVT_L_D64_MM = 1152, 1168 CVT_L_D_MMR6 = 1153, 1169 CVT_L_S = 1154, 1170 CVT_L_S_MM = 1155, 1171 CVT_L_S_MMR6 = 1156, 1172 CVT_PS_S64 = 1157, 1173 CVT_S_D32 = 1158, 1174 CVT_S_D32_MM = 1159, 1175 CVT_S_D64 = 1160, 1176 CVT_S_D64_MM = 1161, 1177 CVT_S_L = 1162, 1178 CVT_S_L_MMR6 = 1163, 1179 CVT_S_PL64 = 1164, 1180 CVT_S_PU64 = 1165, 1181 CVT_S_W = 1166, 1182 CVT_S_W_MM = 1167, 1183 CVT_S_W_MMR6 = 1168, 1184 CVT_W_D32 = 1169, 1185 CVT_W_D32_MM = 1170, 1186 CVT_W_D64 = 1171, 1187 CVT_W_D64_MM = 1172, 1188 CVT_W_S = 1173, 1189 CVT_W_S_MM = 1174, 1190 CVT_W_S_MMR6 = 1175, 1191 C_EQ_D32 = 1176, 1192 C_EQ_D32_MM = 1177, 1193 C_EQ_D64 = 1178, 1194 C_EQ_D64_MM = 1179, 1195 C_EQ_S = 1180, 1196 C_EQ_S_MM = 1181, 1197 C_F_D32 = 1182, 1198 C_F_D32_MM = 1183, 1199 C_F_D64 = 1184, 1200 C_F_D64_MM = 1185, 1201 C_F_S = 1186, 1202 C_F_S_MM = 1187, 1203 C_LE_D32 = 1188, 1204 C_LE_D32_MM = 1189, 1205 C_LE_D64 = 1190, 1206 C_LE_D64_MM = 1191, 1207 C_LE_S = 1192, 1208 C_LE_S_MM = 1193, 1209 C_LT_D32 = 1194, 1210 C_LT_D32_MM = 1195, 1211 C_LT_D64 = 1196, 1212 C_LT_D64_MM = 1197, 1213 C_LT_S = 1198, 1214 C_LT_S_MM = 1199, 1215 C_NGE_D32 = 1200, 1216 C_NGE_D32_MM = 1201, 1217 C_NGE_D64 = 1202, 1218 C_NGE_D64_MM = 1203, 1219 C_NGE_S = 1204, 1220 C_NGE_S_MM = 1205, 1221 C_NGLE_D32 = 1206, 1222 C_NGLE_D32_MM = 1207, 1223 C_NGLE_D64 = 1208, 1224 C_NGLE_D64_MM = 1209, 1225 C_NGLE_S = 1210, 1226 C_NGLE_S_MM = 1211, 1227 C_NGL_D32 = 1212, 1228 C_NGL_D32_MM = 1213, 1229 C_NGL_D64 = 1214, 1230 C_NGL_D64_MM = 1215, 1231 C_NGL_S = 1216, 1232 C_NGL_S_MM = 1217, 1233 C_NGT_D32 = 1218, 1234 C_NGT_D32_MM = 1219, 1235 C_NGT_D64 = 1220, 1236 C_NGT_D64_MM = 1221, 1237 C_NGT_S = 1222, 1238 C_NGT_S_MM = 1223, 1239 C_OLE_D32 = 1224, 1240 C_OLE_D32_MM = 1225, 1241 C_OLE_D64 = 1226, 1242 C_OLE_D64_MM = 1227, 1243 C_OLE_S = 1228, 1244 C_OLE_S_MM = 1229, 1245 C_OLT_D32 = 1230, 1246 C_OLT_D32_MM = 1231, 1247 C_OLT_D64 = 1232, 1248 C_OLT_D64_MM = 1233, 1249 C_OLT_S = 1234, 1250 C_OLT_S_MM = 1235, 1251 C_SEQ_D32 = 1236, 1252 C_SEQ_D32_MM = 1237, 1253 C_SEQ_D64 = 1238, 1254 C_SEQ_D64_MM = 1239, 1255 C_SEQ_S = 1240, 1256 C_SEQ_S_MM = 1241, 1257 C_SF_D32 = 1242, 1258 C_SF_D32_MM = 1243, 1259 C_SF_D64 = 1244, 1260 C_SF_D64_MM = 1245, 1261 C_SF_S = 1246, 1262 C_SF_S_MM = 1247, 1263 C_UEQ_D32 = 1248, 1264 C_UEQ_D32_MM = 1249, 1265 C_UEQ_D64 = 1250, 1266 C_UEQ_D64_MM = 1251, 1267 C_UEQ_S = 1252, 1268 C_UEQ_S_MM = 1253, 1269 C_ULE_D32 = 1254, 1270 C_ULE_D32_MM = 1255, 1271 C_ULE_D64 = 1256, 1272 C_ULE_D64_MM = 1257, 1273 C_ULE_S = 1258, 1274 C_ULE_S_MM = 1259, 1275 C_ULT_D32 = 1260, 1276 C_ULT_D32_MM = 1261, 1277 C_ULT_D64 = 1262, 1278 C_ULT_D64_MM = 1263, 1279 C_ULT_S = 1264, 1280 C_ULT_S_MM = 1265, 1281 C_UN_D32 = 1266, 1282 C_UN_D32_MM = 1267, 1283 C_UN_D64 = 1268, 1284 C_UN_D64_MM = 1269, 1285 C_UN_S = 1270, 1286 C_UN_S_MM = 1271, 1287 CmpRxRy16 = 1272, 1288 CmpiRxImm16 = 1273, 1289 CmpiRxImmX16 = 1274, 1290 DADD = 1275, 1291 DADDi = 1276, 1292 DADDiu = 1277, 1293 DADDu = 1278, 1294 DAHI = 1279, 1295 DALIGN = 1280, 1296 DATI = 1281, 1297 DAUI = 1282, 1298 DBITSWAP = 1283, 1299 DCLO = 1284, 1300 DCLO_R6 = 1285, 1301 DCLZ = 1286, 1302 DCLZ_R6 = 1287, 1303 DDIV = 1288, 1304 DDIVU = 1289, 1305 DERET = 1290, 1306 DERET_MM = 1291, 1307 DERET_MMR6 = 1292, 1308 DEXT = 1293, 1309 DEXT64_32 = 1294, 1310 DEXTM = 1295, 1311 DEXTU = 1296, 1312 DI = 1297, 1313 DINS = 1298, 1314 DINSM = 1299, 1315 DINSU = 1300, 1316 DIV = 1301, 1317 DIVU = 1302, 1318 DIVU_MMR6 = 1303, 1319 DIV_MMR6 = 1304, 1320 DIV_S_B = 1305, 1321 DIV_S_D = 1306, 1322 DIV_S_H = 1307, 1323 DIV_S_W = 1308, 1324 DIV_U_B = 1309, 1325 DIV_U_D = 1310, 1326 DIV_U_H = 1311, 1327 DIV_U_W = 1312, 1328 DI_MM = 1313, 1329 DI_MMR6 = 1314, 1330 DLSA = 1315, 1331 DLSA_R6 = 1316, 1332 DMFC0 = 1317, 1333 DMFC1 = 1318, 1334 DMFC2 = 1319, 1335 DMFC2_OCTEON = 1320, 1336 DMFGC0 = 1321, 1337 DMOD = 1322, 1338 DMODU = 1323, 1339 DMT = 1324, 1340 DMTC0 = 1325, 1341 DMTC1 = 1326, 1342 DMTC2 = 1327, 1343 DMTC2_OCTEON = 1328, 1344 DMTGC0 = 1329, 1345 DMUH = 1330, 1346 DMUHU = 1331, 1347 DMUL = 1332, 1348 DMULT = 1333, 1349 DMULTu = 1334, 1350 DMULU = 1335, 1351 DMUL_R6 = 1336, 1352 DOTP_S_D = 1337, 1353 DOTP_S_H = 1338, 1354 DOTP_S_W = 1339, 1355 DOTP_U_D = 1340, 1356 DOTP_U_H = 1341, 1357 DOTP_U_W = 1342, 1358 DPADD_S_D = 1343, 1359 DPADD_S_H = 1344, 1360 DPADD_S_W = 1345, 1361 DPADD_U_D = 1346, 1362 DPADD_U_H = 1347, 1363 DPADD_U_W = 1348, 1364 DPAQX_SA_W_PH = 1349, 1365 DPAQX_SA_W_PH_MMR2 = 1350, 1366 DPAQX_S_W_PH = 1351, 1367 DPAQX_S_W_PH_MMR2 = 1352, 1368 DPAQ_SA_L_W = 1353, 1369 DPAQ_SA_L_W_MM = 1354, 1370 DPAQ_S_W_PH = 1355, 1371 DPAQ_S_W_PH_MM = 1356, 1372 DPAU_H_QBL = 1357, 1373 DPAU_H_QBL_MM = 1358, 1374 DPAU_H_QBR = 1359, 1375 DPAU_H_QBR_MM = 1360, 1376 DPAX_W_PH = 1361, 1377 DPAX_W_PH_MMR2 = 1362, 1378 DPA_W_PH = 1363, 1379 DPA_W_PH_MMR2 = 1364, 1380 DPOP = 1365, 1381 DPSQX_SA_W_PH = 1366, 1382 DPSQX_SA_W_PH_MMR2 = 1367, 1383 DPSQX_S_W_PH = 1368, 1384 DPSQX_S_W_PH_MMR2 = 1369, 1385 DPSQ_SA_L_W = 1370, 1386 DPSQ_SA_L_W_MM = 1371, 1387 DPSQ_S_W_PH = 1372, 1388 DPSQ_S_W_PH_MM = 1373, 1389 DPSUB_S_D = 1374, 1390 DPSUB_S_H = 1375, 1391 DPSUB_S_W = 1376, 1392 DPSUB_U_D = 1377, 1393 DPSUB_U_H = 1378, 1394 DPSUB_U_W = 1379, 1395 DPSU_H_QBL = 1380, 1396 DPSU_H_QBL_MM = 1381, 1397 DPSU_H_QBR = 1382, 1398 DPSU_H_QBR_MM = 1383, 1399 DPSX_W_PH = 1384, 1400 DPSX_W_PH_MMR2 = 1385, 1401 DPS_W_PH = 1386, 1402 DPS_W_PH_MMR2 = 1387, 1403 DROTR = 1388, 1404 DROTR32 = 1389, 1405 DROTRV = 1390, 1406 DSBH = 1391, 1407 DSDIV = 1392, 1408 DSHD = 1393, 1409 DSLL = 1394, 1410 DSLL32 = 1395, 1411 DSLL64_32 = 1396, 1412 DSLLV = 1397, 1413 DSRA = 1398, 1414 DSRA32 = 1399, 1415 DSRAV = 1400, 1416 DSRL = 1401, 1417 DSRL32 = 1402, 1418 DSRLV = 1403, 1419 DSUB = 1404, 1420 DSUBu = 1405, 1421 DUDIV = 1406, 1422 DVP = 1407, 1423 DVPE = 1408, 1424 DVP_MMR6 = 1409, 1425 DivRxRy16 = 1410, 1426 DivuRxRy16 = 1411, 1427 EHB = 1412, 1428 EHB_MM = 1413, 1429 EHB_MMR6 = 1414, 1430 EI = 1415, 1431 EI_MM = 1416, 1432 EI_MMR6 = 1417, 1433 EMT = 1418, 1434 ERET = 1419, 1435 ERETNC = 1420, 1436 ERETNC_MMR6 = 1421, 1437 ERET_MM = 1422, 1438 ERET_MMR6 = 1423, 1439 EVP = 1424, 1440 EVPE = 1425, 1441 EVP_MMR6 = 1426, 1442 EXT = 1427, 1443 EXTP = 1428, 1444 EXTPDP = 1429, 1445 EXTPDPV = 1430, 1446 EXTPDPV_MM = 1431, 1447 EXTPDP_MM = 1432, 1448 EXTPV = 1433, 1449 EXTPV_MM = 1434, 1450 EXTP_MM = 1435, 1451 EXTRV_RS_W = 1436, 1452 EXTRV_RS_W_MM = 1437, 1453 EXTRV_R_W = 1438, 1454 EXTRV_R_W_MM = 1439, 1455 EXTRV_S_H = 1440, 1456 EXTRV_S_H_MM = 1441, 1457 EXTRV_W = 1442, 1458 EXTRV_W_MM = 1443, 1459 EXTR_RS_W = 1444, 1460 EXTR_RS_W_MM = 1445, 1461 EXTR_R_W = 1446, 1462 EXTR_R_W_MM = 1447, 1463 EXTR_S_H = 1448, 1464 EXTR_S_H_MM = 1449, 1465 EXTR_W = 1450, 1466 EXTR_W_MM = 1451, 1467 EXTS = 1452, 1468 EXTS32 = 1453, 1469 EXT_MM = 1454, 1470 EXT_MMR6 = 1455, 1471 FABS_D32 = 1456, 1472 FABS_D32_MM = 1457, 1473 FABS_D64 = 1458, 1474 FABS_D64_MM = 1459, 1475 FABS_S = 1460, 1476 FABS_S_MM = 1461, 1477 FADD_D = 1462, 1478 FADD_D32 = 1463, 1479 FADD_D32_MM = 1464, 1480 FADD_D64 = 1465, 1481 FADD_D64_MM = 1466, 1482 FADD_S = 1467, 1483 FADD_S_MM = 1468, 1484 FADD_S_MMR6 = 1469, 1485 FADD_W = 1470, 1486 FCAF_D = 1471, 1487 FCAF_W = 1472, 1488 FCEQ_D = 1473, 1489 FCEQ_W = 1474, 1490 FCLASS_D = 1475, 1491 FCLASS_W = 1476, 1492 FCLE_D = 1477, 1493 FCLE_W = 1478, 1494 FCLT_D = 1479, 1495 FCLT_W = 1480, 1496 FCMP_D32 = 1481, 1497 FCMP_D32_MM = 1482, 1498 FCMP_D64 = 1483, 1499 FCMP_S32 = 1484, 1500 FCMP_S32_MM = 1485, 1501 FCNE_D = 1486, 1502 FCNE_W = 1487, 1503 FCOR_D = 1488, 1504 FCOR_W = 1489, 1505 FCUEQ_D = 1490, 1506 FCUEQ_W = 1491, 1507 FCULE_D = 1492, 1508 FCULE_W = 1493, 1509 FCULT_D = 1494, 1510 FCULT_W = 1495, 1511 FCUNE_D = 1496, 1512 FCUNE_W = 1497, 1513 FCUN_D = 1498, 1514 FCUN_W = 1499, 1515 FDIV_D = 1500, 1516 FDIV_D32 = 1501, 1517 FDIV_D32_MM = 1502, 1518 FDIV_D64 = 1503, 1519 FDIV_D64_MM = 1504, 1520 FDIV_S = 1505, 1521 FDIV_S_MM = 1506, 1522 FDIV_S_MMR6 = 1507, 1523 FDIV_W = 1508, 1524 FEXDO_H = 1509, 1525 FEXDO_W = 1510, 1526 FEXP2_D = 1511, 1527 FEXP2_W = 1512, 1528 FEXUPL_D = 1513, 1529 FEXUPL_W = 1514, 1530 FEXUPR_D = 1515, 1531 FEXUPR_W = 1516, 1532 FFINT_S_D = 1517, 1533 FFINT_S_W = 1518, 1534 FFINT_U_D = 1519, 1535 FFINT_U_W = 1520, 1536 FFQL_D = 1521, 1537 FFQL_W = 1522, 1538 FFQR_D = 1523, 1539 FFQR_W = 1524, 1540 FILL_B = 1525, 1541 FILL_D = 1526, 1542 FILL_H = 1527, 1543 FILL_W = 1528, 1544 FLOG2_D = 1529, 1545 FLOG2_W = 1530, 1546 FLOOR_L_D64 = 1531, 1547 FLOOR_L_D_MMR6 = 1532, 1548 FLOOR_L_S = 1533, 1549 FLOOR_L_S_MMR6 = 1534, 1550 FLOOR_W_D32 = 1535, 1551 FLOOR_W_D64 = 1536, 1552 FLOOR_W_D_MMR6 = 1537, 1553 FLOOR_W_MM = 1538, 1554 FLOOR_W_S = 1539, 1555 FLOOR_W_S_MM = 1540, 1556 FLOOR_W_S_MMR6 = 1541, 1557 FMADD_D = 1542, 1558 FMADD_W = 1543, 1559 FMAX_A_D = 1544, 1560 FMAX_A_W = 1545, 1561 FMAX_D = 1546, 1562 FMAX_W = 1547, 1563 FMIN_A_D = 1548, 1564 FMIN_A_W = 1549, 1565 FMIN_D = 1550, 1566 FMIN_W = 1551, 1567 FMOV_D32 = 1552, 1568 FMOV_D32_MM = 1553, 1569 FMOV_D64 = 1554, 1570 FMOV_D64_MM = 1555, 1571 FMOV_D_MMR6 = 1556, 1572 FMOV_S = 1557, 1573 FMOV_S_MM = 1558, 1574 FMOV_S_MMR6 = 1559, 1575 FMSUB_D = 1560, 1576 FMSUB_W = 1561, 1577 FMUL_D = 1562, 1578 FMUL_D32 = 1563, 1579 FMUL_D32_MM = 1564, 1580 FMUL_D64 = 1565, 1581 FMUL_D64_MM = 1566, 1582 FMUL_S = 1567, 1583 FMUL_S_MM = 1568, 1584 FMUL_S_MMR6 = 1569, 1585 FMUL_W = 1570, 1586 FNEG_D32 = 1571, 1587 FNEG_D32_MM = 1572, 1588 FNEG_D64 = 1573, 1589 FNEG_D64_MM = 1574, 1590 FNEG_S = 1575, 1591 FNEG_S_MM = 1576, 1592 FNEG_S_MMR6 = 1577, 1593 FORK = 1578, 1594 FRCP_D = 1579, 1595 FRCP_W = 1580, 1596 FRINT_D = 1581, 1597 FRINT_W = 1582, 1598 FRSQRT_D = 1583, 1599 FRSQRT_W = 1584, 1600 FSAF_D = 1585, 1601 FSAF_W = 1586, 1602 FSEQ_D = 1587, 1603 FSEQ_W = 1588, 1604 FSLE_D = 1589, 1605 FSLE_W = 1590, 1606 FSLT_D = 1591, 1607 FSLT_W = 1592, 1608 FSNE_D = 1593, 1609 FSNE_W = 1594, 1610 FSOR_D = 1595, 1611 FSOR_W = 1596, 1612 FSQRT_D = 1597, 1613 FSQRT_D32 = 1598, 1614 FSQRT_D32_MM = 1599, 1615 FSQRT_D64 = 1600, 1616 FSQRT_D64_MM = 1601, 1617 FSQRT_S = 1602, 1618 FSQRT_S_MM = 1603, 1619 FSQRT_W = 1604, 1620 FSUB_D = 1605, 1621 FSUB_D32 = 1606, 1622 FSUB_D32_MM = 1607, 1623 FSUB_D64 = 1608, 1624 FSUB_D64_MM = 1609, 1625 FSUB_S = 1610, 1626 FSUB_S_MM = 1611, 1627 FSUB_S_MMR6 = 1612, 1628 FSUB_W = 1613, 1629 FSUEQ_D = 1614, 1630 FSUEQ_W = 1615, 1631 FSULE_D = 1616, 1632 FSULE_W = 1617, 1633 FSULT_D = 1618, 1634 FSULT_W = 1619, 1635 FSUNE_D = 1620, 1636 FSUNE_W = 1621, 1637 FSUN_D = 1622, 1638 FSUN_W = 1623, 1639 FTINT_S_D = 1624, 1640 FTINT_S_W = 1625, 1641 FTINT_U_D = 1626, 1642 FTINT_U_W = 1627, 1643 FTQ_H = 1628, 1644 FTQ_W = 1629, 1645 FTRUNC_S_D = 1630, 1646 FTRUNC_S_W = 1631, 1647 FTRUNC_U_D = 1632, 1648 FTRUNC_U_W = 1633, 1649 GINVI = 1634, 1650 GINVI_MMR6 = 1635, 1651 GINVT = 1636, 1652 GINVT_MMR6 = 1637, 1653 HADD_S_D = 1638, 1654 HADD_S_H = 1639, 1655 HADD_S_W = 1640, 1656 HADD_U_D = 1641, 1657 HADD_U_H = 1642, 1658 HADD_U_W = 1643, 1659 HSUB_S_D = 1644, 1660 HSUB_S_H = 1645, 1661 HSUB_S_W = 1646, 1662 HSUB_U_D = 1647, 1663 HSUB_U_H = 1648, 1664 HSUB_U_W = 1649, 1665 HYPCALL = 1650, 1666 HYPCALL_MM = 1651, 1667 ILVEV_B = 1652, 1668 ILVEV_D = 1653, 1669 ILVEV_H = 1654, 1670 ILVEV_W = 1655, 1671 ILVL_B = 1656, 1672 ILVL_D = 1657, 1673 ILVL_H = 1658, 1674 ILVL_W = 1659, 1675 ILVOD_B = 1660, 1676 ILVOD_D = 1661, 1677 ILVOD_H = 1662, 1678 ILVOD_W = 1663, 1679 ILVR_B = 1664, 1680 ILVR_D = 1665, 1681 ILVR_H = 1666, 1682 ILVR_W = 1667, 1683 INS = 1668, 1684 INSERT_B = 1669, 1685 INSERT_D = 1670, 1686 INSERT_H = 1671, 1687 INSERT_W = 1672, 1688 INSV = 1673, 1689 INSVE_B = 1674, 1690 INSVE_D = 1675, 1691 INSVE_H = 1676, 1692 INSVE_W = 1677, 1693 INSV_MM = 1678, 1694 INS_MM = 1679, 1695 INS_MMR6 = 1680, 1696 J = 1681, 1697 JAL = 1682, 1698 JALR = 1683, 1699 JALR16_MM = 1684, 1700 JALR64 = 1685, 1701 JALRC16_MMR6 = 1686, 1702 JALRC_HB_MMR6 = 1687, 1703 JALRC_MMR6 = 1688, 1704 JALRS16_MM = 1689, 1705 JALRS_MM = 1690, 1706 JALR_HB = 1691, 1707 JALR_HB64 = 1692, 1708 JALR_MM = 1693, 1709 JALS_MM = 1694, 1710 JALX = 1695, 1711 JALX_MM = 1696, 1712 JAL_MM = 1697, 1713 JIALC = 1698, 1714 JIALC64 = 1699, 1715 JIALC_MMR6 = 1700, 1716 JIC = 1701, 1717 JIC64 = 1702, 1718 JIC_MMR6 = 1703, 1719 JR = 1704, 1720 JR16_MM = 1705, 1721 JR64 = 1706, 1722 JRADDIUSP = 1707, 1723 JRC16_MM = 1708, 1724 JRC16_MMR6 = 1709, 1725 JRCADDIUSP_MMR6 = 1710, 1726 JR_HB = 1711, 1727 JR_HB64 = 1712, 1728 JR_HB64_R6 = 1713, 1729 JR_HB_R6 = 1714, 1730 JR_MM = 1715, 1731 J_MM = 1716, 1732 Jal16 = 1717, 1733 JalB16 = 1718, 1734 JrRa16 = 1719, 1735 JrcRa16 = 1720, 1736 JrcRx16 = 1721, 1737 JumpLinkReg16 = 1722, 1738 LB = 1723, 1739 LB64 = 1724, 1740 LBE = 1725, 1741 LBE_MM = 1726, 1742 LBU16_MM = 1727, 1743 LBUX = 1728, 1744 LBUX_MM = 1729, 1745 LBU_MMR6 = 1730, 1746 LB_MM = 1731, 1747 LB_MMR6 = 1732, 1748 LBu = 1733, 1749 LBu64 = 1734, 1750 LBuE = 1735, 1751 LBuE_MM = 1736, 1752 LBu_MM = 1737, 1753 LD = 1738, 1754 LDC1 = 1739, 1755 LDC164 = 1740, 1756 LDC1_D64_MMR6 = 1741, 1757 LDC1_MM = 1742, 1758 LDC2 = 1743, 1759 LDC2_MMR6 = 1744, 1760 LDC2_R6 = 1745, 1761 LDC3 = 1746, 1762 LDI_B = 1747, 1763 LDI_D = 1748, 1764 LDI_H = 1749, 1765 LDI_W = 1750, 1766 LDL = 1751, 1767 LDPC = 1752, 1768 LDR = 1753, 1769 LDXC1 = 1754, 1770 LDXC164 = 1755, 1771 LD_B = 1756, 1772 LD_D = 1757, 1773 LD_H = 1758, 1774 LD_W = 1759, 1775 LEA_ADDiu = 1760, 1776 LEA_ADDiu64 = 1761, 1777 LEA_ADDiu_MM = 1762, 1778 LH = 1763, 1779 LH64 = 1764, 1780 LHE = 1765, 1781 LHE_MM = 1766, 1782 LHU16_MM = 1767, 1783 LHX = 1768, 1784 LHX_MM = 1769, 1785 LH_MM = 1770, 1786 LHu = 1771, 1787 LHu64 = 1772, 1788 LHuE = 1773, 1789 LHuE_MM = 1774, 1790 LHu_MM = 1775, 1791 LI16_MM = 1776, 1792 LI16_MMR6 = 1777, 1793 LL = 1778, 1794 LL64 = 1779, 1795 LL64_R6 = 1780, 1796 LLD = 1781, 1797 LLD_R6 = 1782, 1798 LLE = 1783, 1799 LLE_MM = 1784, 1800 LL_MM = 1785, 1801 LL_MMR6 = 1786, 1802 LL_R6 = 1787, 1803 LSA = 1788, 1804 LSA_MMR6 = 1789, 1805 LSA_R6 = 1790, 1806 LUI_MMR6 = 1791, 1807 LUXC1 = 1792, 1808 LUXC164 = 1793, 1809 LUXC1_MM = 1794, 1810 LUi = 1795, 1811 LUi64 = 1796, 1812 LUi_MM = 1797, 1813 LW = 1798, 1814 LW16_MM = 1799, 1815 LW64 = 1800, 1816 LWC1 = 1801, 1817 LWC1_MM = 1802, 1818 LWC2 = 1803, 1819 LWC2_MMR6 = 1804, 1820 LWC2_R6 = 1805, 1821 LWC3 = 1806, 1822 LWDSP = 1807, 1823 LWDSP_MM = 1808, 1824 LWE = 1809, 1825 LWE_MM = 1810, 1826 LWGP_MM = 1811, 1827 LWL = 1812, 1828 LWL64 = 1813, 1829 LWLE = 1814, 1830 LWLE_MM = 1815, 1831 LWL_MM = 1816, 1832 LWM16_MM = 1817, 1833 LWM16_MMR6 = 1818, 1834 LWM32_MM = 1819, 1835 LWPC = 1820, 1836 LWPC_MMR6 = 1821, 1837 LWP_MM = 1822, 1838 LWR = 1823, 1839 LWR64 = 1824, 1840 LWRE = 1825, 1841 LWRE_MM = 1826, 1842 LWR_MM = 1827, 1843 LWSP_MM = 1828, 1844 LWUPC = 1829, 1845 LWU_MM = 1830, 1846 LWX = 1831, 1847 LWXC1 = 1832, 1848 LWXC1_MM = 1833, 1849 LWXS_MM = 1834, 1850 LWX_MM = 1835, 1851 LW_MM = 1836, 1852 LW_MMR6 = 1837, 1853 LWu = 1838, 1854 LbRxRyOffMemX16 = 1839, 1855 LbuRxRyOffMemX16 = 1840, 1856 LhRxRyOffMemX16 = 1841, 1857 LhuRxRyOffMemX16 = 1842, 1858 LiRxImm16 = 1843, 1859 LiRxImmAlignX16 = 1844, 1860 LiRxImmX16 = 1845, 1861 LwRxPcTcp16 = 1846, 1862 LwRxPcTcpX16 = 1847, 1863 LwRxRyOffMemX16 = 1848, 1864 LwRxSpImmX16 = 1849, 1865 MADD = 1850, 1866 MADDF_D = 1851, 1867 MADDF_D_MMR6 = 1852, 1868 MADDF_S = 1853, 1869 MADDF_S_MMR6 = 1854, 1870 MADDR_Q_H = 1855, 1871 MADDR_Q_W = 1856, 1872 MADDU = 1857, 1873 MADDU_DSP = 1858, 1874 MADDU_DSP_MM = 1859, 1875 MADDU_MM = 1860, 1876 MADDV_B = 1861, 1877 MADDV_D = 1862, 1878 MADDV_H = 1863, 1879 MADDV_W = 1864, 1880 MADD_D32 = 1865, 1881 MADD_D32_MM = 1866, 1882 MADD_D64 = 1867, 1883 MADD_DSP = 1868, 1884 MADD_DSP_MM = 1869, 1885 MADD_MM = 1870, 1886 MADD_Q_H = 1871, 1887 MADD_Q_W = 1872, 1888 MADD_S = 1873, 1889 MADD_S_MM = 1874, 1890 MAQ_SA_W_PHL = 1875, 1891 MAQ_SA_W_PHL_MM = 1876, 1892 MAQ_SA_W_PHR = 1877, 1893 MAQ_SA_W_PHR_MM = 1878, 1894 MAQ_S_W_PHL = 1879, 1895 MAQ_S_W_PHL_MM = 1880, 1896 MAQ_S_W_PHR = 1881, 1897 MAQ_S_W_PHR_MM = 1882, 1898 MAXA_D = 1883, 1899 MAXA_D_MMR6 = 1884, 1900 MAXA_S = 1885, 1901 MAXA_S_MMR6 = 1886, 1902 MAXI_S_B = 1887, 1903 MAXI_S_D = 1888, 1904 MAXI_S_H = 1889, 1905 MAXI_S_W = 1890, 1906 MAXI_U_B = 1891, 1907 MAXI_U_D = 1892, 1908 MAXI_U_H = 1893, 1909 MAXI_U_W = 1894, 1910 MAX_A_B = 1895, 1911 MAX_A_D = 1896, 1912 MAX_A_H = 1897, 1913 MAX_A_W = 1898, 1914 MAX_D = 1899, 1915 MAX_D_MMR6 = 1900, 1916 MAX_S = 1901, 1917 MAX_S_B = 1902, 1918 MAX_S_D = 1903, 1919 MAX_S_H = 1904, 1920 MAX_S_MMR6 = 1905, 1921 MAX_S_W = 1906, 1922 MAX_U_B = 1907, 1923 MAX_U_D = 1908, 1924 MAX_U_H = 1909, 1925 MAX_U_W = 1910, 1926 MFC0 = 1911, 1927 MFC0_MMR6 = 1912, 1928 MFC1 = 1913, 1929 MFC1_D64 = 1914, 1930 MFC1_MM = 1915, 1931 MFC1_MMR6 = 1916, 1932 MFC2 = 1917, 1933 MFC2_MMR6 = 1918, 1934 MFGC0 = 1919, 1935 MFGC0_MM = 1920, 1936 MFHC0_MMR6 = 1921, 1937 MFHC1_D32 = 1922, 1938 MFHC1_D32_MM = 1923, 1939 MFHC1_D64 = 1924, 1940 MFHC1_D64_MM = 1925, 1941 MFHC2_MMR6 = 1926, 1942 MFHGC0 = 1927, 1943 MFHGC0_MM = 1928, 1944 MFHI = 1929, 1945 MFHI16_MM = 1930, 1946 MFHI64 = 1931, 1947 MFHI_DSP = 1932, 1948 MFHI_DSP_MM = 1933, 1949 MFHI_MM = 1934, 1950 MFLO = 1935, 1951 MFLO16_MM = 1936, 1952 MFLO64 = 1937, 1953 MFLO_DSP = 1938, 1954 MFLO_DSP_MM = 1939, 1955 MFLO_MM = 1940, 1956 MFTR = 1941, 1957 MINA_D = 1942, 1958 MINA_D_MMR6 = 1943, 1959 MINA_S = 1944, 1960 MINA_S_MMR6 = 1945, 1961 MINI_S_B = 1946, 1962 MINI_S_D = 1947, 1963 MINI_S_H = 1948, 1964 MINI_S_W = 1949, 1965 MINI_U_B = 1950, 1966 MINI_U_D = 1951, 1967 MINI_U_H = 1952, 1968 MINI_U_W = 1953, 1969 MIN_A_B = 1954, 1970 MIN_A_D = 1955, 1971 MIN_A_H = 1956, 1972 MIN_A_W = 1957, 1973 MIN_D = 1958, 1974 MIN_D_MMR6 = 1959, 1975 MIN_S = 1960, 1976 MIN_S_B = 1961, 1977 MIN_S_D = 1962, 1978 MIN_S_H = 1963, 1979 MIN_S_MMR6 = 1964, 1980 MIN_S_W = 1965, 1981 MIN_U_B = 1966, 1982 MIN_U_D = 1967, 1983 MIN_U_H = 1968, 1984 MIN_U_W = 1969, 1985 MOD = 1970, 1986 MODSUB = 1971, 1987 MODSUB_MM = 1972, 1988 MODU = 1973, 1989 MODU_MMR6 = 1974, 1990 MOD_MMR6 = 1975, 1991 MOD_S_B = 1976, 1992 MOD_S_D = 1977, 1993 MOD_S_H = 1978, 1994 MOD_S_W = 1979, 1995 MOD_U_B = 1980, 1996 MOD_U_D = 1981, 1997 MOD_U_H = 1982, 1998 MOD_U_W = 1983, 1999 MOVE16_MM = 1984, 2000 MOVE16_MMR6 = 1985, 2001 MOVEP_MM = 1986, 2002 MOVEP_MMR6 = 1987, 2003 MOVE_V = 1988, 2004 MOVF_D32 = 1989, 2005 MOVF_D32_MM = 1990, 2006 MOVF_D64 = 1991, 2007 MOVF_I = 1992, 2008 MOVF_I64 = 1993, 2009 MOVF_I_MM = 1994, 2010 MOVF_S = 1995, 2011 MOVF_S_MM = 1996, 2012 MOVN_I64_D64 = 1997, 2013 MOVN_I64_I = 1998, 2014 MOVN_I64_I64 = 1999, 2015 MOVN_I64_S = 2000, 2016 MOVN_I_D32 = 2001, 2017 MOVN_I_D32_MM = 2002, 2018 MOVN_I_D64 = 2003, 2019 MOVN_I_I = 2004, 2020 MOVN_I_I64 = 2005, 2021 MOVN_I_MM = 2006, 2022 MOVN_I_S = 2007, 2023 MOVN_I_S_MM = 2008, 2024 MOVT_D32 = 2009, 2025 MOVT_D32_MM = 2010, 2026 MOVT_D64 = 2011, 2027 MOVT_I = 2012, 2028 MOVT_I64 = 2013, 2029 MOVT_I_MM = 2014, 2030 MOVT_S = 2015, 2031 MOVT_S_MM = 2016, 2032 MOVZ_I64_D64 = 2017, 2033 MOVZ_I64_I = 2018, 2034 MOVZ_I64_I64 = 2019, 2035 MOVZ_I64_S = 2020, 2036 MOVZ_I_D32 = 2021, 2037 MOVZ_I_D32_MM = 2022, 2038 MOVZ_I_D64 = 2023, 2039 MOVZ_I_I = 2024, 2040 MOVZ_I_I64 = 2025, 2041 MOVZ_I_MM = 2026, 2042 MOVZ_I_S = 2027, 2043 MOVZ_I_S_MM = 2028, 2044 MSUB = 2029, 2045 MSUBF_D = 2030, 2046 MSUBF_D_MMR6 = 2031, 2047 MSUBF_S = 2032, 2048 MSUBF_S_MMR6 = 2033, 2049 MSUBR_Q_H = 2034, 2050 MSUBR_Q_W = 2035, 2051 MSUBU = 2036, 2052 MSUBU_DSP = 2037, 2053 MSUBU_DSP_MM = 2038, 2054 MSUBU_MM = 2039, 2055 MSUBV_B = 2040, 2056 MSUBV_D = 2041, 2057 MSUBV_H = 2042, 2058 MSUBV_W = 2043, 2059 MSUB_D32 = 2044, 2060 MSUB_D32_MM = 2045, 2061 MSUB_D64 = 2046, 2062 MSUB_DSP = 2047, 2063 MSUB_DSP_MM = 2048, 2064 MSUB_MM = 2049, 2065 MSUB_Q_H = 2050, 2066 MSUB_Q_W = 2051, 2067 MSUB_S = 2052, 2068 MSUB_S_MM = 2053, 2069 MTC0 = 2054, 2070 MTC0_MMR6 = 2055, 2071 MTC1 = 2056, 2072 MTC1_D64 = 2057, 2073 MTC1_D64_MM = 2058, 2074 MTC1_MM = 2059, 2075 MTC1_MMR6 = 2060, 2076 MTC2 = 2061, 2077 MTC2_MMR6 = 2062, 2078 MTGC0 = 2063, 2079 MTGC0_MM = 2064, 2080 MTHC0_MMR6 = 2065, 2081 MTHC1_D32 = 2066, 2082 MTHC1_D32_MM = 2067, 2083 MTHC1_D64 = 2068, 2084 MTHC1_D64_MM = 2069, 2085 MTHC2_MMR6 = 2070, 2086 MTHGC0 = 2071, 2087 MTHGC0_MM = 2072, 2088 MTHI = 2073, 2089 MTHI64 = 2074, 2090 MTHI_DSP = 2075, 2091 MTHI_DSP_MM = 2076, 2092 MTHI_MM = 2077, 2093 MTHLIP = 2078, 2094 MTHLIP_MM = 2079, 2095 MTLO = 2080, 2096 MTLO64 = 2081, 2097 MTLO_DSP = 2082, 2098 MTLO_DSP_MM = 2083, 2099 MTLO_MM = 2084, 2100 MTM0 = 2085, 2101 MTM1 = 2086, 2102 MTM2 = 2087, 2103 MTP0 = 2088, 2104 MTP1 = 2089, 2105 MTP2 = 2090, 2106 MTTR = 2091, 2107 MUH = 2092, 2108 MUHU = 2093, 2109 MUHU_MMR6 = 2094, 2110 MUH_MMR6 = 2095, 2111 MUL = 2096, 2112 MULEQ_S_W_PHL = 2097, 2113 MULEQ_S_W_PHL_MM = 2098, 2114 MULEQ_S_W_PHR = 2099, 2115 MULEQ_S_W_PHR_MM = 2100, 2116 MULEU_S_PH_QBL = 2101, 2117 MULEU_S_PH_QBL_MM = 2102, 2118 MULEU_S_PH_QBR = 2103, 2119 MULEU_S_PH_QBR_MM = 2104, 2120 MULQ_RS_PH = 2105, 2121 MULQ_RS_PH_MM = 2106, 2122 MULQ_RS_W = 2107, 2123 MULQ_RS_W_MMR2 = 2108, 2124 MULQ_S_PH = 2109, 2125 MULQ_S_PH_MMR2 = 2110, 2126 MULQ_S_W = 2111, 2127 MULQ_S_W_MMR2 = 2112, 2128 MULR_Q_H = 2113, 2129 MULR_Q_W = 2114, 2130 MULSAQ_S_W_PH = 2115, 2131 MULSAQ_S_W_PH_MM = 2116, 2132 MULSA_W_PH = 2117, 2133 MULSA_W_PH_MMR2 = 2118, 2134 MULT = 2119, 2135 MULTU_DSP = 2120, 2136 MULTU_DSP_MM = 2121, 2137 MULT_DSP = 2122, 2138 MULT_DSP_MM = 2123, 2139 MULT_MM = 2124, 2140 MULTu = 2125, 2141 MULTu_MM = 2126, 2142 MULU = 2127, 2143 MULU_MMR6 = 2128, 2144 MULV_B = 2129, 2145 MULV_D = 2130, 2146 MULV_H = 2131, 2147 MULV_W = 2132, 2148 MUL_MM = 2133, 2149 MUL_MMR6 = 2134, 2150 MUL_PH = 2135, 2151 MUL_PH_MMR2 = 2136, 2152 MUL_Q_H = 2137, 2153 MUL_Q_W = 2138, 2154 MUL_R6 = 2139, 2155 MUL_S_PH = 2140, 2156 MUL_S_PH_MMR2 = 2141, 2157 Mfhi16 = 2142, 2158 Mflo16 = 2143, 2159 Move32R16 = 2144, 2160 MoveR3216 = 2145, 2161 NLOC_B = 2146, 2162 NLOC_D = 2147, 2163 NLOC_H = 2148, 2164 NLOC_W = 2149, 2165 NLZC_B = 2150, 2166 NLZC_D = 2151, 2167 NLZC_H = 2152, 2168 NLZC_W = 2153, 2169 NMADD_D32 = 2154, 2170 NMADD_D32_MM = 2155, 2171 NMADD_D64 = 2156, 2172 NMADD_S = 2157, 2173 NMADD_S_MM = 2158, 2174 NMSUB_D32 = 2159, 2175 NMSUB_D32_MM = 2160, 2176 NMSUB_D64 = 2161, 2177 NMSUB_S = 2162, 2178 NMSUB_S_MM = 2163, 2179 NOR = 2164, 2180 NOR64 = 2165, 2181 NORI_B = 2166, 2182 NOR_MM = 2167, 2183 NOR_MMR6 = 2168, 2184 NOR_V = 2169, 2185 NOT16_MM = 2170, 2186 NOT16_MMR6 = 2171, 2187 NegRxRy16 = 2172, 2188 NotRxRy16 = 2173, 2189 OR = 2174, 2190 OR16_MM = 2175, 2191 OR16_MMR6 = 2176, 2192 OR64 = 2177, 2193 ORI_B = 2178, 2194 ORI_MMR6 = 2179, 2195 OR_MM = 2180, 2196 OR_MMR6 = 2181, 2197 OR_V = 2182, 2198 ORi = 2183, 2199 ORi64 = 2184, 2200 ORi_MM = 2185, 2201 OrRxRxRy16 = 2186, 2202 PACKRL_PH = 2187, 2203 PACKRL_PH_MM = 2188, 2204 PAUSE = 2189, 2205 PAUSE_MM = 2190, 2206 PAUSE_MMR6 = 2191, 2207 PCKEV_B = 2192, 2208 PCKEV_D = 2193, 2209 PCKEV_H = 2194, 2210 PCKEV_W = 2195, 2211 PCKOD_B = 2196, 2212 PCKOD_D = 2197, 2213 PCKOD_H = 2198, 2214 PCKOD_W = 2199, 2215 PCNT_B = 2200, 2216 PCNT_D = 2201, 2217 PCNT_H = 2202, 2218 PCNT_W = 2203, 2219 PICK_PH = 2204, 2220 PICK_PH_MM = 2205, 2221 PICK_QB = 2206, 2222 PICK_QB_MM = 2207, 2223 PLL_PS64 = 2208, 2224 PLU_PS64 = 2209, 2225 POP = 2210, 2226 PRECEQU_PH_QBL = 2211, 2227 PRECEQU_PH_QBLA = 2212, 2228 PRECEQU_PH_QBLA_MM = 2213, 2229 PRECEQU_PH_QBL_MM = 2214, 2230 PRECEQU_PH_QBR = 2215, 2231 PRECEQU_PH_QBRA = 2216, 2232 PRECEQU_PH_QBRA_MM = 2217, 2233 PRECEQU_PH_QBR_MM = 2218, 2234 PRECEQ_W_PHL = 2219, 2235 PRECEQ_W_PHL_MM = 2220, 2236 PRECEQ_W_PHR = 2221, 2237 PRECEQ_W_PHR_MM = 2222, 2238 PRECEU_PH_QBL = 2223, 2239 PRECEU_PH_QBLA = 2224, 2240 PRECEU_PH_QBLA_MM = 2225, 2241 PRECEU_PH_QBL_MM = 2226, 2242 PRECEU_PH_QBR = 2227, 2243 PRECEU_PH_QBRA = 2228, 2244 PRECEU_PH_QBRA_MM = 2229, 2245 PRECEU_PH_QBR_MM = 2230, 2246 PRECRQU_S_QB_PH = 2231, 2247 PRECRQU_S_QB_PH_MM = 2232, 2248 PRECRQ_PH_W = 2233, 2249 PRECRQ_PH_W_MM = 2234, 2250 PRECRQ_QB_PH = 2235, 2251 PRECRQ_QB_PH_MM = 2236, 2252 PRECRQ_RS_PH_W = 2237, 2253 PRECRQ_RS_PH_W_MM = 2238, 2254 PRECR_QB_PH = 2239, 2255 PRECR_QB_PH_MMR2 = 2240, 2256 PRECR_SRA_PH_W = 2241, 2257 PRECR_SRA_PH_W_MMR2 = 2242, 2258 PRECR_SRA_R_PH_W = 2243, 2259 PRECR_SRA_R_PH_W_MMR2 = 2244, 2260 PREF = 2245, 2261 PREFE = 2246, 2262 PREFE_MM = 2247, 2263 PREFX_MM = 2248, 2264 PREF_MM = 2249, 2265 PREF_MMR6 = 2250, 2266 PREF_R6 = 2251, 2267 PREPEND = 2252, 2268 PREPEND_MMR2 = 2253, 2269 RADDU_W_QB = 2254, 2270 RADDU_W_QB_MM = 2255, 2271 RDDSP = 2256, 2272 RDDSP_MM = 2257, 2273 RDHWR = 2258, 2274 RDHWR64 = 2259, 2275 RDHWR_MM = 2260, 2276 RDHWR_MMR6 = 2261, 2277 RDPGPR_MMR6 = 2262, 2278 RECIP_D32 = 2263, 2279 RECIP_D32_MM = 2264, 2280 RECIP_D64 = 2265, 2281 RECIP_D64_MM = 2266, 2282 RECIP_S = 2267, 2283 RECIP_S_MM = 2268, 2284 REPLV_PH = 2269, 2285 REPLV_PH_MM = 2270, 2286 REPLV_QB = 2271, 2287 REPLV_QB_MM = 2272, 2288 REPL_PH = 2273, 2289 REPL_PH_MM = 2274, 2290 REPL_QB = 2275, 2291 REPL_QB_MM = 2276, 2292 RINT_D = 2277, 2293 RINT_D_MMR6 = 2278, 2294 RINT_S = 2279, 2295 RINT_S_MMR6 = 2280, 2296 ROTR = 2281, 2297 ROTRV = 2282, 2298 ROTRV_MM = 2283, 2299 ROTR_MM = 2284, 2300 ROUND_L_D64 = 2285, 2301 ROUND_L_D_MMR6 = 2286, 2302 ROUND_L_S = 2287, 2303 ROUND_L_S_MMR6 = 2288, 2304 ROUND_W_D32 = 2289, 2305 ROUND_W_D64 = 2290, 2306 ROUND_W_D_MMR6 = 2291, 2307 ROUND_W_MM = 2292, 2308 ROUND_W_S = 2293, 2309 ROUND_W_S_MM = 2294, 2310 ROUND_W_S_MMR6 = 2295, 2311 RSQRT_D32 = 2296, 2312 RSQRT_D32_MM = 2297, 2313 RSQRT_D64 = 2298, 2314 RSQRT_D64_MM = 2299, 2315 RSQRT_S = 2300, 2316 RSQRT_S_MM = 2301, 2317 Restore16 = 2302, 2318 RestoreX16 = 2303, 2319 SAA = 2304, 2320 SAAD = 2305, 2321 SAT_S_B = 2306, 2322 SAT_S_D = 2307, 2323 SAT_S_H = 2308, 2324 SAT_S_W = 2309, 2325 SAT_U_B = 2310, 2326 SAT_U_D = 2311, 2327 SAT_U_H = 2312, 2328 SAT_U_W = 2313, 2329 SB = 2314, 2330 SB16_MM = 2315, 2331 SB16_MMR6 = 2316, 2332 SB64 = 2317, 2333 SBE = 2318, 2334 SBE_MM = 2319, 2335 SB_MM = 2320, 2336 SB_MMR6 = 2321, 2337 SC = 2322, 2338 SC64 = 2323, 2339 SC64_R6 = 2324, 2340 SCD = 2325, 2341 SCD_R6 = 2326, 2342 SCE = 2327, 2343 SCE_MM = 2328, 2344 SC_MM = 2329, 2345 SC_MMR6 = 2330, 2346 SC_R6 = 2331, 2347 SD = 2332, 2348 SDBBP = 2333, 2349 SDBBP16_MM = 2334, 2350 SDBBP16_MMR6 = 2335, 2351 SDBBP_MM = 2336, 2352 SDBBP_MMR6 = 2337, 2353 SDBBP_R6 = 2338, 2354 SDC1 = 2339, 2355 SDC164 = 2340, 2356 SDC1_D64_MMR6 = 2341, 2357 SDC1_MM = 2342, 2358 SDC2 = 2343, 2359 SDC2_MMR6 = 2344, 2360 SDC2_R6 = 2345, 2361 SDC3 = 2346, 2362 SDIV = 2347, 2363 SDIV_MM = 2348, 2364 SDL = 2349, 2365 SDR = 2350, 2366 SDXC1 = 2351, 2367 SDXC164 = 2352, 2368 SEB = 2353, 2369 SEB64 = 2354, 2370 SEB_MM = 2355, 2371 SEH = 2356, 2372 SEH64 = 2357, 2373 SEH_MM = 2358, 2374 SELEQZ = 2359, 2375 SELEQZ64 = 2360, 2376 SELEQZ_D = 2361, 2377 SELEQZ_D_MMR6 = 2362, 2378 SELEQZ_MMR6 = 2363, 2379 SELEQZ_S = 2364, 2380 SELEQZ_S_MMR6 = 2365, 2381 SELNEZ = 2366, 2382 SELNEZ64 = 2367, 2383 SELNEZ_D = 2368, 2384 SELNEZ_D_MMR6 = 2369, 2385 SELNEZ_MMR6 = 2370, 2386 SELNEZ_S = 2371, 2387 SELNEZ_S_MMR6 = 2372, 2388 SEL_D = 2373, 2389 SEL_D_MMR6 = 2374, 2390 SEL_S = 2375, 2391 SEL_S_MMR6 = 2376, 2392 SEQ = 2377, 2393 SEQi = 2378, 2394 SH = 2379, 2395 SH16_MM = 2380, 2396 SH16_MMR6 = 2381, 2397 SH64 = 2382, 2398 SHE = 2383, 2399 SHE_MM = 2384, 2400 SHF_B = 2385, 2401 SHF_H = 2386, 2402 SHF_W = 2387, 2403 SHILO = 2388, 2404 SHILOV = 2389, 2405 SHILOV_MM = 2390, 2406 SHILO_MM = 2391, 2407 SHLLV_PH = 2392, 2408 SHLLV_PH_MM = 2393, 2409 SHLLV_QB = 2394, 2410 SHLLV_QB_MM = 2395, 2411 SHLLV_S_PH = 2396, 2412 SHLLV_S_PH_MM = 2397, 2413 SHLLV_S_W = 2398, 2414 SHLLV_S_W_MM = 2399, 2415 SHLL_PH = 2400, 2416 SHLL_PH_MM = 2401, 2417 SHLL_QB = 2402, 2418 SHLL_QB_MM = 2403, 2419 SHLL_S_PH = 2404, 2420 SHLL_S_PH_MM = 2405, 2421 SHLL_S_W = 2406, 2422 SHLL_S_W_MM = 2407, 2423 SHRAV_PH = 2408, 2424 SHRAV_PH_MM = 2409, 2425 SHRAV_QB = 2410, 2426 SHRAV_QB_MMR2 = 2411, 2427 SHRAV_R_PH = 2412, 2428 SHRAV_R_PH_MM = 2413, 2429 SHRAV_R_QB = 2414, 2430 SHRAV_R_QB_MMR2 = 2415, 2431 SHRAV_R_W = 2416, 2432 SHRAV_R_W_MM = 2417, 2433 SHRA_PH = 2418, 2434 SHRA_PH_MM = 2419, 2435 SHRA_QB = 2420, 2436 SHRA_QB_MMR2 = 2421, 2437 SHRA_R_PH = 2422, 2438 SHRA_R_PH_MM = 2423, 2439 SHRA_R_QB = 2424, 2440 SHRA_R_QB_MMR2 = 2425, 2441 SHRA_R_W = 2426, 2442 SHRA_R_W_MM = 2427, 2443 SHRLV_PH = 2428, 2444 SHRLV_PH_MMR2 = 2429, 2445 SHRLV_QB = 2430, 2446 SHRLV_QB_MM = 2431, 2447 SHRL_PH = 2432, 2448 SHRL_PH_MMR2 = 2433, 2449 SHRL_QB = 2434, 2450 SHRL_QB_MM = 2435, 2451 SH_MM = 2436, 2452 SH_MMR6 = 2437, 2453 SIGRIE = 2438, 2454 SIGRIE_MMR6 = 2439, 2455 SLDI_B = 2440, 2456 SLDI_D = 2441, 2457 SLDI_H = 2442, 2458 SLDI_W = 2443, 2459 SLD_B = 2444, 2460 SLD_D = 2445, 2461 SLD_H = 2446, 2462 SLD_W = 2447, 2463 SLL = 2448, 2464 SLL16_MM = 2449, 2465 SLL16_MMR6 = 2450, 2466 SLL64_32 = 2451, 2467 SLL64_64 = 2452, 2468 SLLI_B = 2453, 2469 SLLI_D = 2454, 2470 SLLI_H = 2455, 2471 SLLI_W = 2456, 2472 SLLV = 2457, 2473 SLLV_MM = 2458, 2474 SLL_B = 2459, 2475 SLL_D = 2460, 2476 SLL_H = 2461, 2477 SLL_MM = 2462, 2478 SLL_MMR6 = 2463, 2479 SLL_W = 2464, 2480 SLT = 2465, 2481 SLT64 = 2466, 2482 SLT_MM = 2467, 2483 SLTi = 2468, 2484 SLTi64 = 2469, 2485 SLTi_MM = 2470, 2486 SLTiu = 2471, 2487 SLTiu64 = 2472, 2488 SLTiu_MM = 2473, 2489 SLTu = 2474, 2490 SLTu64 = 2475, 2491 SLTu_MM = 2476, 2492 SNE = 2477, 2493 SNEi = 2478, 2494 SPLATI_B = 2479, 2495 SPLATI_D = 2480, 2496 SPLATI_H = 2481, 2497 SPLATI_W = 2482, 2498 SPLAT_B = 2483, 2499 SPLAT_D = 2484, 2500 SPLAT_H = 2485, 2501 SPLAT_W = 2486, 2502 SRA = 2487, 2503 SRAI_B = 2488, 2504 SRAI_D = 2489, 2505 SRAI_H = 2490, 2506 SRAI_W = 2491, 2507 SRARI_B = 2492, 2508 SRARI_D = 2493, 2509 SRARI_H = 2494, 2510 SRARI_W = 2495, 2511 SRAR_B = 2496, 2512 SRAR_D = 2497, 2513 SRAR_H = 2498, 2514 SRAR_W = 2499, 2515 SRAV = 2500, 2516 SRAV_MM = 2501, 2517 SRA_B = 2502, 2518 SRA_D = 2503, 2519 SRA_H = 2504, 2520 SRA_MM = 2505, 2521 SRA_W = 2506, 2522 SRL = 2507, 2523 SRL16_MM = 2508, 2524 SRL16_MMR6 = 2509, 2525 SRLI_B = 2510, 2526 SRLI_D = 2511, 2527 SRLI_H = 2512, 2528 SRLI_W = 2513, 2529 SRLRI_B = 2514, 2530 SRLRI_D = 2515, 2531 SRLRI_H = 2516, 2532 SRLRI_W = 2517, 2533 SRLR_B = 2518, 2534 SRLR_D = 2519, 2535 SRLR_H = 2520, 2536 SRLR_W = 2521, 2537 SRLV = 2522, 2538 SRLV_MM = 2523, 2539 SRL_B = 2524, 2540 SRL_D = 2525, 2541 SRL_H = 2526, 2542 SRL_MM = 2527, 2543 SRL_W = 2528, 2544 SSNOP = 2529, 2545 SSNOP_MM = 2530, 2546 SSNOP_MMR6 = 2531, 2547 ST_B = 2532, 2548 ST_D = 2533, 2549 ST_H = 2534, 2550 ST_W = 2535, 2551 SUB = 2536, 2552 SUBQH_PH = 2537, 2553 SUBQH_PH_MMR2 = 2538, 2554 SUBQH_R_PH = 2539, 2555 SUBQH_R_PH_MMR2 = 2540, 2556 SUBQH_R_W = 2541, 2557 SUBQH_R_W_MMR2 = 2542, 2558 SUBQH_W = 2543, 2559 SUBQH_W_MMR2 = 2544, 2560 SUBQ_PH = 2545, 2561 SUBQ_PH_MM = 2546, 2562 SUBQ_S_PH = 2547, 2563 SUBQ_S_PH_MM = 2548, 2564 SUBQ_S_W = 2549, 2565 SUBQ_S_W_MM = 2550, 2566 SUBSUS_U_B = 2551, 2567 SUBSUS_U_D = 2552, 2568 SUBSUS_U_H = 2553, 2569 SUBSUS_U_W = 2554, 2570 SUBSUU_S_B = 2555, 2571 SUBSUU_S_D = 2556, 2572 SUBSUU_S_H = 2557, 2573 SUBSUU_S_W = 2558, 2574 SUBS_S_B = 2559, 2575 SUBS_S_D = 2560, 2576 SUBS_S_H = 2561, 2577 SUBS_S_W = 2562, 2578 SUBS_U_B = 2563, 2579 SUBS_U_D = 2564, 2580 SUBS_U_H = 2565, 2581 SUBS_U_W = 2566, 2582 SUBU16_MM = 2567, 2583 SUBU16_MMR6 = 2568, 2584 SUBUH_QB = 2569, 2585 SUBUH_QB_MMR2 = 2570, 2586 SUBUH_R_QB = 2571, 2587 SUBUH_R_QB_MMR2 = 2572, 2588 SUBU_MMR6 = 2573, 2589 SUBU_PH = 2574, 2590 SUBU_PH_MMR2 = 2575, 2591 SUBU_QB = 2576, 2592 SUBU_QB_MM = 2577, 2593 SUBU_S_PH = 2578, 2594 SUBU_S_PH_MMR2 = 2579, 2595 SUBU_S_QB = 2580, 2596 SUBU_S_QB_MM = 2581, 2597 SUBVI_B = 2582, 2598 SUBVI_D = 2583, 2599 SUBVI_H = 2584, 2600 SUBVI_W = 2585, 2601 SUBV_B = 2586, 2602 SUBV_D = 2587, 2603 SUBV_H = 2588, 2604 SUBV_W = 2589, 2605 SUB_MM = 2590, 2606 SUB_MMR6 = 2591, 2607 SUBu = 2592, 2608 SUBu_MM = 2593, 2609 SUXC1 = 2594, 2610 SUXC164 = 2595, 2611 SUXC1_MM = 2596, 2612 SW = 2597, 2613 SW16_MM = 2598, 2614 SW16_MMR6 = 2599, 2615 SW64 = 2600, 2616 SWC1 = 2601, 2617 SWC1_MM = 2602, 2618 SWC2 = 2603, 2619 SWC2_MMR6 = 2604, 2620 SWC2_R6 = 2605, 2621 SWC3 = 2606, 2622 SWDSP = 2607, 2623 SWDSP_MM = 2608, 2624 SWE = 2609, 2625 SWE_MM = 2610, 2626 SWL = 2611, 2627 SWL64 = 2612, 2628 SWLE = 2613, 2629 SWLE_MM = 2614, 2630 SWL_MM = 2615, 2631 SWM16_MM = 2616, 2632 SWM16_MMR6 = 2617, 2633 SWM32_MM = 2618, 2634 SWP_MM = 2619, 2635 SWR = 2620, 2636 SWR64 = 2621, 2637 SWRE = 2622, 2638 SWRE_MM = 2623, 2639 SWR_MM = 2624, 2640 SWSP_MM = 2625, 2641 SWSP_MMR6 = 2626, 2642 SWXC1 = 2627, 2643 SWXC1_MM = 2628, 2644 SW_MM = 2629, 2645 SW_MMR6 = 2630, 2646 SYNC = 2631, 2647 SYNCI = 2632, 2648 SYNCI_MM = 2633, 2649 SYNCI_MMR6 = 2634, 2650 SYNC_MM = 2635, 2651 SYNC_MMR6 = 2636, 2652 SYSCALL = 2637, 2653 SYSCALL_MM = 2638, 2654 Save16 = 2639, 2655 SaveX16 = 2640, 2656 SbRxRyOffMemX16 = 2641, 2657 SebRx16 = 2642, 2658 SehRx16 = 2643, 2659 ShRxRyOffMemX16 = 2644, 2660 SllX16 = 2645, 2661 SllvRxRy16 = 2646, 2662 SltRxRy16 = 2647, 2663 SltiRxImm16 = 2648, 2664 SltiRxImmX16 = 2649, 2665 SltiuRxImm16 = 2650, 2666 SltiuRxImmX16 = 2651, 2667 SltuRxRy16 = 2652, 2668 SraX16 = 2653, 2669 SravRxRy16 = 2654, 2670 SrlX16 = 2655, 2671 SrlvRxRy16 = 2656, 2672 SubuRxRyRz16 = 2657, 2673 SwRxRyOffMemX16 = 2658, 2674 SwRxSpImmX16 = 2659, 2675 TEQ = 2660, 2676 TEQI = 2661, 2677 TEQI_MM = 2662, 2678 TEQ_MM = 2663, 2679 TGE = 2664, 2680 TGEI = 2665, 2681 TGEIU = 2666, 2682 TGEIU_MM = 2667, 2683 TGEI_MM = 2668, 2684 TGEU = 2669, 2685 TGEU_MM = 2670, 2686 TGE_MM = 2671, 2687 TLBGINV = 2672, 2688 TLBGINVF = 2673, 2689 TLBGINVF_MM = 2674, 2690 TLBGINV_MM = 2675, 2691 TLBGP = 2676, 2692 TLBGP_MM = 2677, 2693 TLBGR = 2678, 2694 TLBGR_MM = 2679, 2695 TLBGWI = 2680, 2696 TLBGWI_MM = 2681, 2697 TLBGWR = 2682, 2698 TLBGWR_MM = 2683, 2699 TLBINV = 2684, 2700 TLBINVF = 2685, 2701 TLBINVF_MMR6 = 2686, 2702 TLBINV_MMR6 = 2687, 2703 TLBP = 2688, 2704 TLBP_MM = 2689, 2705 TLBR = 2690, 2706 TLBR_MM = 2691, 2707 TLBWI = 2692, 2708 TLBWI_MM = 2693, 2709 TLBWR = 2694, 2710 TLBWR_MM = 2695, 2711 TLT = 2696, 2712 TLTI = 2697, 2713 TLTIU_MM = 2698, 2714 TLTI_MM = 2699, 2715 TLTU = 2700, 2716 TLTU_MM = 2701, 2717 TLT_MM = 2702, 2718 TNE = 2703, 2719 TNEI = 2704, 2720 TNEI_MM = 2705, 2721 TNE_MM = 2706, 2722 TRUNC_L_D64 = 2707, 2723 TRUNC_L_D_MMR6 = 2708, 2724 TRUNC_L_S = 2709, 2725 TRUNC_L_S_MMR6 = 2710, 2726 TRUNC_W_D32 = 2711, 2727 TRUNC_W_D64 = 2712, 2728 TRUNC_W_D_MMR6 = 2713, 2729 TRUNC_W_MM = 2714, 2730 TRUNC_W_S = 2715, 2731 TRUNC_W_S_MM = 2716, 2732 TRUNC_W_S_MMR6 = 2717, 2733 TTLTIU = 2718, 2734 UDIV = 2719, 2735 UDIV_MM = 2720, 2736 V3MULU = 2721, 2737 VMM0 = 2722, 2738 VMULU = 2723, 2739 VSHF_B = 2724, 2740 VSHF_D = 2725, 2741 VSHF_H = 2726, 2742 VSHF_W = 2727, 2743 WAIT = 2728, 2744 WAIT_MM = 2729, 2745 WAIT_MMR6 = 2730, 2746 WRDSP = 2731, 2747 WRDSP_MM = 2732, 2748 WRPGPR_MMR6 = 2733, 2749 WSBH = 2734, 2750 WSBH_MM = 2735, 2751 WSBH_MMR6 = 2736, 2752 XOR = 2737, 2753 XOR16_MM = 2738, 2754 XOR16_MMR6 = 2739, 2755 XOR64 = 2740, 2756 XORI_B = 2741, 2757 XORI_MMR6 = 2742, 2758 XOR_MM = 2743, 2759 XOR_MMR6 = 2744, 2760 XOR_V = 2745, 2761 XORi = 2746, 2762 XORi64 = 2747, 2763 XORi_MM = 2748, 2764 XorRxRxRy16 = 2749, 2765 YIELD = 2750, 2766 INSTRUCTION_LIST_END = 2751 2767 }; 2768 2769} // end namespace Mips 2770} // end namespace llvm 2771#endif // GET_INSTRINFO_ENUM 2772 2773#ifdef GET_INSTRINFO_SCHED_ENUM 2774#undef GET_INSTRINFO_SCHED_ENUM 2775namespace llvm { 2776 2777namespace Mips { 2778namespace Sched { 2779 enum { 2780 NoInstrModel = 0, 2781 IIPseudo = 1, 2782 II_B = 2, 2783 II_BCCZAL = 3, 2784 II_MTC1 = 4, 2785 II_MFC1 = 5, 2786 II_JALR = 6, 2787 II_JAL = 7, 2788 II_CVT = 8, 2789 II_DMULT = 9, 2790 II_DMULTU = 10, 2791 II_DDIV = 11, 2792 II_DDIVU = 12, 2793 II_IndirectBranchPseudo = 13, 2794 II_MADD = 14, 2795 II_MADDU = 15, 2796 II_MFHI_MFLO = 16, 2797 II_MSUB = 17, 2798 II_MSUBU = 18, 2799 II_MTHI_MTLO = 19, 2800 II_MULT = 20, 2801 II_MULTU = 21, 2802 II_ReturnPseudo = 22, 2803 II_DIV = 23, 2804 II_DIVU = 24, 2805 II_J = 25, 2806 II_JR = 26, 2807 II_TRAP = 27, 2808 II_ADD = 28, 2809 II_ADDIUPC = 29, 2810 II_ADDIU = 30, 2811 II_ADDU = 31, 2812 II_ADDI = 32, 2813 II_ALIGN = 33, 2814 II_ALUIPC = 34, 2815 II_AND = 35, 2816 II_ANDI = 36, 2817 II_AUI = 37, 2818 II_AUIPC = 38, 2819 IIM16Alu = 39, 2820 II_BADDU = 40, 2821 II_BC = 41, 2822 II_BALC = 42, 2823 II_BBIT = 43, 2824 II_BC1CCZ = 44, 2825 II_BC1F = 45, 2826 II_BC1FL = 46, 2827 II_BC1T = 47, 2828 II_BC1TL = 48, 2829 II_BC2CCZ = 49, 2830 II_BCC = 50, 2831 II_BCCC = 51, 2832 II_BCCZ = 52, 2833 II_BCCZC = 53, 2834 II_BCCZALS = 54, 2835 II_BITSWAP = 55, 2836 II_BREAK = 56, 2837 II_CACHE = 57, 2838 II_CACHEE = 58, 2839 II_CEIL = 59, 2840 II_CFC1 = 60, 2841 II_CFC2 = 61, 2842 II_INS = 62, 2843 II_CLASS_D = 63, 2844 II_CLASS_S = 64, 2845 II_CLO = 65, 2846 II_CLZ = 66, 2847 II_CMP_CC_D = 67, 2848 II_CMP_CC_S = 68, 2849 II_CRC32B = 69, 2850 II_CRC32CB = 70, 2851 II_CRC32CD = 71, 2852 II_CRC32CH = 72, 2853 II_CRC32CW = 73, 2854 II_CRC32D = 74, 2855 II_CRC32H = 75, 2856 II_CRC32W = 76, 2857 II_CTC1 = 77, 2858 II_CTC2 = 78, 2859 II_C_CC_D = 79, 2860 II_C_CC_S = 80, 2861 II_DADD = 81, 2862 II_DADDI = 82, 2863 II_DADDIU = 83, 2864 II_DADDU = 84, 2865 II_DAHI = 85, 2866 II_DALIGN = 86, 2867 II_DATI = 87, 2868 II_DAUI = 88, 2869 II_DBITSWAP = 89, 2870 II_DCLO = 90, 2871 II_DCLZ = 91, 2872 II_DERET = 92, 2873 II_EXT = 93, 2874 II_DI = 94, 2875 II_DLSA = 95, 2876 II_DMFC0 = 96, 2877 II_DMFC1 = 97, 2878 II_DMFC2 = 98, 2879 II_DMFGC0 = 99, 2880 II_DMOD = 100, 2881 II_DMODU = 101, 2882 II_DMT = 102, 2883 II_DMTC0 = 103, 2884 II_DMTC1 = 104, 2885 II_DMTC2 = 105, 2886 II_DMTGC0 = 106, 2887 II_DMUH = 107, 2888 II_DMUHU = 108, 2889 II_DMUL = 109, 2890 II_POP = 110, 2891 II_DROTR = 111, 2892 II_DROTR32 = 112, 2893 II_DROTRV = 113, 2894 II_DSBH = 114, 2895 II_DSHD = 115, 2896 II_DSLL = 116, 2897 II_DSLL32 = 117, 2898 II_DSLLV = 118, 2899 II_DSRA = 119, 2900 II_DSRA32 = 120, 2901 II_DSRAV = 121, 2902 II_DSRL = 122, 2903 II_DSRL32 = 123, 2904 II_DSRLV = 124, 2905 II_DSUB = 125, 2906 II_DSUBU = 126, 2907 II_DVP = 127, 2908 II_DVPE = 128, 2909 II_EHB = 129, 2910 II_EI = 130, 2911 II_EMT = 131, 2912 II_ERET = 132, 2913 II_ERETNC = 133, 2914 II_EVP = 134, 2915 II_EVPE = 135, 2916 II_ABS = 136, 2917 II_SQRT_D = 137, 2918 II_ADD_D = 138, 2919 II_ADD_S = 139, 2920 II_DIV_D = 140, 2921 II_DIV_S = 141, 2922 II_FLOOR = 142, 2923 II_MOV_D = 143, 2924 II_MOV_S = 144, 2925 II_MUL_D = 145, 2926 II_MUL_S = 146, 2927 II_NEG = 147, 2928 II_FORK = 148, 2929 II_SQRT_S = 149, 2930 II_SUB_D = 150, 2931 II_SUB_S = 151, 2932 II_GINVI = 152, 2933 II_GINVT = 153, 2934 II_HYPCALL = 154, 2935 II_JALR_HB = 155, 2936 II_JALRC = 156, 2937 II_JALRS = 157, 2938 II_JALS = 158, 2939 II_JIALC = 159, 2940 II_JIC = 160, 2941 II_JRADDIUSP = 161, 2942 II_JRC = 162, 2943 II_JR_HB = 163, 2944 II_LB = 164, 2945 II_LBE = 165, 2946 II_LBU = 166, 2947 II_LBUE = 167, 2948 II_LD = 168, 2949 II_LDC1 = 169, 2950 II_LDC2 = 170, 2951 II_LDC3 = 171, 2952 II_LDL = 172, 2953 II_LDPC = 173, 2954 II_LDR = 174, 2955 II_LDXC1 = 175, 2956 II_LH = 176, 2957 II_LHE = 177, 2958 II_LHU = 178, 2959 II_LHUE = 179, 2960 II_LI = 180, 2961 II_LL = 181, 2962 II_LLD = 182, 2963 II_LLE = 183, 2964 II_LSA = 184, 2965 II_LUI = 185, 2966 II_LUXC1 = 186, 2967 II_LW = 187, 2968 II_LWC1 = 188, 2969 II_LWC2 = 189, 2970 II_LWC3 = 190, 2971 II_LWE = 191, 2972 II_LWL = 192, 2973 II_LWLE = 193, 2974 II_LWM = 194, 2975 II_LWPC = 195, 2976 II_LWP = 196, 2977 II_LWR = 197, 2978 II_LWRE = 198, 2979 II_LWUPC = 199, 2980 II_LWU = 200, 2981 II_LWXC1 = 201, 2982 II_LWXS = 202, 2983 II_MADDF_D = 203, 2984 II_MADDF_S = 204, 2985 II_MADD_D = 205, 2986 II_MADD_S = 206, 2987 II_MAX_D = 207, 2988 II_MAXA_D = 208, 2989 II_MAX_S = 209, 2990 II_MAXA_S = 210, 2991 II_MFC0 = 211, 2992 II_MFC2 = 212, 2993 II_MFGC0 = 213, 2994 II_MFHC0 = 214, 2995 II_MFHC1 = 215, 2996 II_MFHGC0 = 216, 2997 II_MFTR = 217, 2998 II_MIN_S = 218, 2999 II_MINA_D = 219, 3000 II_MIN_D = 220, 3001 II_MINA_S = 221, 3002 II_MOD = 222, 3003 II_MODU = 223, 3004 II_MOVE = 224, 3005 II_MOVF_D = 225, 3006 II_MOVF = 226, 3007 II_MOVF_S = 227, 3008 II_MOVN_D = 228, 3009 II_MOVN = 229, 3010 II_MOVN_S = 230, 3011 II_MOVT_D = 231, 3012 II_MOVT = 232, 3013 II_MOVT_S = 233, 3014 II_MOVZ_D = 234, 3015 II_MOVZ = 235, 3016 II_MOVZ_S = 236, 3017 II_MSUBF_D = 237, 3018 II_MSUBF_S = 238, 3019 II_MSUB_D = 239, 3020 II_MSUB_S = 240, 3021 II_MTC0 = 241, 3022 II_MTC2 = 242, 3023 II_MTGC0 = 243, 3024 II_MTHC0 = 244, 3025 II_MTHC1 = 245, 3026 II_MTHGC0 = 246, 3027 II_MTTR = 247, 3028 II_MUH = 248, 3029 II_MUHU = 249, 3030 II_MUL = 250, 3031 II_MULU = 251, 3032 II_NMADD_D = 252, 3033 II_NMADD_S = 253, 3034 II_NMSUB_D = 254, 3035 II_NMSUB_S = 255, 3036 II_NOR = 256, 3037 II_NOT = 257, 3038 II_OR = 258, 3039 II_ORI = 259, 3040 II_PAUSE = 260, 3041 II_PREF = 261, 3042 II_PREFE = 262, 3043 II_RDHWR = 263, 3044 II_RDPGPR = 264, 3045 II_RECIP_D = 265, 3046 II_RECIP_S = 266, 3047 II_RINT_D = 267, 3048 II_RINT_S = 268, 3049 II_ROTR = 269, 3050 II_ROTRV = 270, 3051 II_ROUND = 271, 3052 II_RSQRT_D = 272, 3053 II_RSQRT_S = 273, 3054 II_RESTORE = 274, 3055 II_SB = 275, 3056 II_SBE = 276, 3057 II_SC = 277, 3058 II_SCD = 278, 3059 II_SCE = 279, 3060 II_SD = 280, 3061 II_SDBBP = 281, 3062 II_SDC1 = 282, 3063 II_SDC2 = 283, 3064 II_SDC3 = 284, 3065 II_SDL = 285, 3066 II_SDR = 286, 3067 II_SDXC1 = 287, 3068 II_SEB = 288, 3069 II_SEH = 289, 3070 II_SELCCZ = 290, 3071 II_SELCCZ_D = 291, 3072 II_SELCCZ_S = 292, 3073 II_SEL_D = 293, 3074 II_SEL_S = 294, 3075 II_SEQ_SNE = 295, 3076 II_SEQI_SNEI = 296, 3077 II_SH = 297, 3078 II_SHE = 298, 3079 II_SIGRIE = 299, 3080 II_SLL = 300, 3081 II_SLLV = 301, 3082 II_SLT_SLTU = 302, 3083 II_SLTI_SLTIU = 303, 3084 II_SRA = 304, 3085 II_SRAV = 305, 3086 II_SRL = 306, 3087 II_SRLV = 307, 3088 II_SSNOP = 308, 3089 II_SUB = 309, 3090 II_SUBU = 310, 3091 II_SUXC1 = 311, 3092 II_SW = 312, 3093 II_SWC1 = 313, 3094 II_SWC2 = 314, 3095 II_SWC3 = 315, 3096 II_SWE = 316, 3097 II_SWL = 317, 3098 II_SWLE = 318, 3099 II_SWM = 319, 3100 II_SWP = 320, 3101 II_SWR = 321, 3102 II_SWRE = 322, 3103 II_SWXC1 = 323, 3104 II_SYNC = 324, 3105 II_SYNCI = 325, 3106 II_SYSCALL = 326, 3107 II_SAVE = 327, 3108 II_TEQ = 328, 3109 II_TEQI = 329, 3110 II_TGE = 330, 3111 II_TGEI = 331, 3112 II_TGEIU = 332, 3113 II_TGEU = 333, 3114 II_TLBGINV = 334, 3115 II_TLBGINVF = 335, 3116 II_TLBGP = 336, 3117 II_TLBGR = 337, 3118 II_TLBGWI = 338, 3119 II_TLBGWR = 339, 3120 II_TLBINV = 340, 3121 II_TLBINVF = 341, 3122 II_TLBP = 342, 3123 II_TLBR = 343, 3124 II_TLBWI = 344, 3125 II_TLBWR = 345, 3126 II_TLT = 346, 3127 II_TLTI = 347, 3128 II_TTLTIU = 348, 3129 II_TLTU = 349, 3130 II_TNE = 350, 3131 II_TNEI = 351, 3132 II_TRUNC = 352, 3133 II_WAIT = 353, 3134 II_WRPGPR = 354, 3135 II_WSBH = 355, 3136 II_XOR = 356, 3137 II_XORI = 357, 3138 II_YIELD = 358, 3139 AND = 359, 3140 LUi = 360, 3141 NOR = 361, 3142 OR = 362, 3143 SLTi_SLTiu = 363, 3144 SUB = 364, 3145 SUBu = 365, 3146 XOR = 366, 3147 SSNOP = 367, 3148 NOP = 368, 3149 B = 369, 3150 BAL = 370, 3151 BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 371, 3152 BEQ_BEQL_BNE_BNEL = 372, 3153 BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 373, 3154 BREAK = 374, 3155 DERET = 375, 3156 ERET = 376, 3157 ERet_RetRA = 377, 3158 ERETNC = 378, 3159 J_TAILCALL = 379, 3160 JR_TAILCALLREG_TAILCALLREGHB = 380, 3161 JR_HB = 381, 3162 PseudoIndirectBranch_PseudoIndirectHazardBranch = 382, 3163 PseudoReturn = 383, 3164 SDBBP = 384, 3165 SYSCALL = 385, 3166 TEQ = 386, 3167 TEQI = 387, 3168 TGE = 388, 3169 TGEI = 389, 3170 TGEIU = 390, 3171 TGEU = 391, 3172 TLT = 392, 3173 TLTI = 393, 3174 TLTU = 394, 3175 TNE = 395, 3176 TNEI = 396, 3177 TRAP = 397, 3178 TTLTIU = 398, 3179 WAIT = 399, 3180 PAUSE = 400, 3181 JAL = 401, 3182 JALR_JALRHBPseudo_JALRPseudo = 402, 3183 JALR_HB = 403, 3184 JALX = 404, 3185 TLBINV = 405, 3186 TLBINVF = 406, 3187 TLBP = 407, 3188 TLBR = 408, 3189 TLBWI = 409, 3190 TLBWR = 410, 3191 MFC0 = 411, 3192 MTC0 = 412, 3193 MFC2 = 413, 3194 MTC2 = 414, 3195 HYPCALL = 415, 3196 MFGC0 = 416, 3197 MFHGC0 = 417, 3198 MTGC0 = 418, 3199 MTHGC0 = 419, 3200 TLBGINV = 420, 3201 TLBGINVF = 421, 3202 TLBGP = 422, 3203 TLBGR = 423, 3204 TLBGWI = 424, 3205 TLBGWR = 425, 3206 LB = 426, 3207 LBu = 427, 3208 LH = 428, 3209 LHu = 429, 3210 LW = 430, 3211 LL = 431, 3212 LWC2 = 432, 3213 LWC3 = 433, 3214 LDC2 = 434, 3215 LDC3 = 435, 3216 LBE = 436, 3217 LBuE = 437, 3218 LHE = 438, 3219 LHuE = 439, 3220 LWE = 440, 3221 LLE = 441, 3222 LWPC = 442, 3223 LWL = 443, 3224 LWR = 444, 3225 LWLE = 445, 3226 LWRE = 446, 3227 SB = 447, 3228 SH = 448, 3229 SW = 449, 3230 SWC2 = 450, 3231 SWC3 = 451, 3232 SDC2 = 452, 3233 SDC3 = 453, 3234 SC = 454, 3235 SBE = 455, 3236 SHE = 456, 3237 SWE = 457, 3238 SCE = 458, 3239 SWL = 459, 3240 SWR = 460, 3241 SWLE = 461, 3242 SWRE = 462, 3243 PREF = 463, 3244 PREFE = 464, 3245 CACHE = 465, 3246 CACHEE = 466, 3247 SYNC = 467, 3248 SYNCI = 468, 3249 CLO = 469, 3250 CLZ = 470, 3251 DI = 471, 3252 EI = 472, 3253 MFHI_MFLO_PseudoMFHI_PseudoMFLO = 473, 3254 EHB = 474, 3255 RDHWR = 475, 3256 WSBH = 476, 3257 MOVN_I_I = 477, 3258 MOVZ_I_I = 478, 3259 DIV_PseudoSDIV_SDIV = 479, 3260 DIVU_PseudoUDIV_UDIV = 480, 3261 MUL = 481, 3262 MULT_PseudoMULT = 482, 3263 MULTu_PseudoMULTu = 483, 3264 MADD_PseudoMADD = 484, 3265 MADDU_PseudoMADDU = 485, 3266 MSUB_PseudoMSUB = 486, 3267 MSUBU_PseudoMSUBU = 487, 3268 MTHI_MTLO_PseudoMTLOHI = 488, 3269 EXT = 489, 3270 INS = 490, 3271 ADD = 491, 3272 ADDi = 492, 3273 ADDiu = 493, 3274 ANDi = 494, 3275 ORi = 495, 3276 ROTR = 496, 3277 SEB = 497, 3278 SEH = 498, 3279 SLT_SLTu = 499, 3280 SLL = 500, 3281 SRA = 501, 3282 SRL = 502, 3283 XORi = 503, 3284 ADDu = 504, 3285 SLLV = 505, 3286 SRAV = 506, 3287 SRLV = 507, 3288 LSA = 508, 3289 COPY = 509, 3290 VSHF_B_VSHF_D_VSHF_H_VSHF_W = 510, 3291 BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 511, 3292 BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 512, 3293 INSERT_B_INSERT_D_INSERT_H_INSERT_W = 513, 3294 SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 514, 3295 BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 515, 3296 BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 516, 3297 BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 517, 3298 BSELI_B_BSEL_V = 518, 3299 BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 519, 3300 BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 520, 3301 PCNT_B_PCNT_D_PCNT_H_PCNT_W = 521, 3302 SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 522, 3303 BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 523, 3304 CFCMSA_CTCMSA = 524, 3305 FABS_S_FABS_D32_FABS_D64 = 525, 3306 MOVF_D32_MOVF_D64 = 526, 3307 MOVF_S = 527, 3308 MOVT_D32_MOVT_D64 = 528, 3309 MOVT_S = 529, 3310 FMOV_D32_FMOV_D64 = 530, 3311 FMOV_S = 531, 3312 FNEG_S_FNEG_D32_FNEG_D64 = 532, 3313 ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 533, 3314 ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 534, 3315 ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 535, 3316 ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 536, 3317 AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 537, 3318 SHF_B_SHF_H_SHF_W = 538, 3319 FILL_B_FILL_D_FILL_H_FILL_W = 539, 3320 SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 540, 3321 MOVE_V = 541, 3322 LDI_B_LDI_D_LDI_H_LDI_W = 542, 3323 AND_V_NOR_V_OR_V_XOR_V = 543, 3324 ANDI_B_NORI_B_ORI_B_XORI_B = 544, 3325 AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 545, 3326 FILL_FD_PSEUDO_FILL_FW_PSEUDO = 546, 3327 INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 547, 3328 FEXP2_D_FEXP2_W = 548, 3329 CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 549, 3330 CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 550, 3331 CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 551, 3332 CMP_UN_D = 552, 3333 CMP_UN_S = 553, 3334 CMP_UEQ_D = 554, 3335 CMP_UEQ_S = 555, 3336 CMP_EQ_D = 556, 3337 CMP_EQ_S = 557, 3338 CMP_LT_D = 558, 3339 CMP_LT_S = 559, 3340 CMP_ULT_D = 560, 3341 CMP_ULT_S = 561, 3342 CMP_LE_D = 562, 3343 CMP_LE_S = 563, 3344 CMP_ULE_D = 564, 3345 CMP_ULE_S = 565, 3346 FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 566, 3347 FSUEQ_D_FSUEQ_W = 567, 3348 FSULE_D_FSULE_W = 568, 3349 FSULT_D_FSULT_W = 569, 3350 FSUNE_D_FSUNE_W = 570, 3351 FSUN_D_FSUN_W = 571, 3352 FCAF_D_FCAF_W = 572, 3353 FCEQ_D_FCEQ_W = 573, 3354 FCLE_D_FCLE_W = 574, 3355 FCLT_D_FCLT_W = 575, 3356 FCNE_D_FCNE_W = 576, 3357 FCOR_D_FCOR_W = 577, 3358 FCUEQ_D_FCUEQ_W = 578, 3359 FCULE_D_FCULE_W = 579, 3360 FCULT_D_FCULT_W = 580, 3361 FCUNE_D_FCUNE_W = 581, 3362 FCUN_D_FCUN_W = 582, 3363 FABS_D_FABS_W = 583, 3364 FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 584, 3365 FFQL_D_FFQL_W = 585, 3366 FFQR_D_FFQR_W = 586, 3367 FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 587, 3368 FRINT_D_FRINT_W = 588, 3369 FTQ_H_FTQ_W = 589, 3370 FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 590, 3371 FEXDO_H_FEXDO_W = 591, 3372 FEXUPL_D_FEXUPL_W = 592, 3373 FEXUPR_D_FEXUPR_W = 593, 3374 FCLASS_D_FCLASS_W = 594, 3375 FMAX_A_D_FMAX_A_W = 595, 3376 FMAX_D_FMAX_W = 596, 3377 FMIN_A_D_FMIN_A_W = 597, 3378 FMIN_D_FMIN_W = 598, 3379 FLOG2_D_FLOG2_W = 599, 3380 ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 600, 3381 ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 601, 3382 INSVE_B_INSVE_D_INSVE_H_INSVE_W = 602, 3383 SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 603, 3384 SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 604, 3385 SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 605, 3386 SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 606, 3387 SUBV_B_SUBV_D_SUBV_H_SUBV_W = 607, 3388 MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 608, 3389 DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 609, 3390 HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 610, 3391 HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 611, 3392 MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 612, 3393 MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 613, 3394 MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 614, 3395 MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 615, 3396 SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 616, 3397 SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 617, 3398 SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 618, 3399 SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 619, 3400 SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 620, 3401 PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 621, 3402 NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 622, 3403 FADD_D32_FADD_D64 = 623, 3404 FADD_S = 624, 3405 FMUL_D32_FMUL_D64 = 625, 3406 FMUL_S = 626, 3407 FSUB_D32_FSUB_D64 = 627, 3408 FSUB_S = 628, 3409 TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 629, 3410 CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 630, 3411 CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 631, 3412 C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 632, 3413 C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 633, 3414 FCMP_D32_FCMP_D64 = 634, 3415 FCMP_S32 = 635, 3416 PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 636, 3417 PLL_PS64_PLU_PS64 = 637, 3418 FDIV_S = 638, 3419 FDIV_D32_FDIV_D64 = 639, 3420 FSQRT_S = 640, 3421 FSQRT_D32_FSQRT_D64 = 641, 3422 FRCP_D_FRCP_W = 642, 3423 FRSQRT_D_FRSQRT_W = 643, 3424 RECIP_D32_RECIP_D64 = 644, 3425 RSQRT_D32_RSQRT_D64 = 645, 3426 RECIP_S = 646, 3427 RSQRT_S = 647, 3428 FMADD_D_FMADD_W = 648, 3429 FMSUB_D_FMSUB_W = 649, 3430 FDIV_W = 650, 3431 FDIV_D = 651, 3432 FSQRT_W = 652, 3433 FSQRT_D = 653, 3434 FMUL_D_FMUL_W = 654, 3435 FADD_D_FADD_W = 655, 3436 FSUB_D_FSUB_W = 656, 3437 DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 657, 3438 DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 658, 3439 DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 659, 3440 MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 660, 3441 MADDV_B_MADDV_D_MADDV_H_MADDV_W = 661, 3442 MULV_B_MULV_D_MULV_H_MULV_W = 662, 3443 MADDR_Q_H_MADDR_Q_W = 663, 3444 MADD_Q_H_MADD_Q_W = 664, 3445 MSUBR_Q_H_MSUBR_Q_W = 665, 3446 MSUB_Q_H_MSUB_Q_W = 666, 3447 MULR_Q_H_MULR_Q_W = 667, 3448 MUL_Q_H_MUL_Q_W = 668, 3449 MADD_D32_MADD_D64 = 669, 3450 MADD_S = 670, 3451 MSUB_D32_MSUB_D64 = 671, 3452 MSUB_S = 672, 3453 NMADD_D32_NMADD_D64 = 673, 3454 NMADD_S = 674, 3455 NMSUB_D32_NMSUB_D64 = 675, 3456 NMSUB_S = 676, 3457 CTC1 = 677, 3458 MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 678, 3459 MTHC1_D32_MTHC1_D64 = 679, 3460 COPY_U_B_COPY_U_H_COPY_U_W = 680, 3461 COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 681, 3462 BC1F = 682, 3463 BC1FL = 683, 3464 BC1T = 684, 3465 BC1TL = 685, 3466 CFC1 = 686, 3467 MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 687, 3468 MFHC1_D32_MFHC1_D64 = 688, 3469 MOVF_I = 689, 3470 MOVT_I = 690, 3471 SDC1_SDC164 = 691, 3472 SDXC1_SDXC164 = 692, 3473 SWC1 = 693, 3474 SWXC1 = 694, 3475 SUXC1_SUXC164 = 695, 3476 ST_B_ST_D_ST_H_ST_W = 696, 3477 ST_F16 = 697, 3478 MOVN_I_D32_MOVN_I_D64 = 698, 3479 MOVN_I_S = 699, 3480 MOVZ_I_D32_MOVZ_I_D64 = 700, 3481 MOVZ_I_S = 701, 3482 LDC1_LDC164 = 702, 3483 LDXC1_LDXC164 = 703, 3484 LWC1 = 704, 3485 LWXC1 = 705, 3486 LUXC1_LUXC164 = 706, 3487 LD_B_LD_D_LD_H_LD_W = 707, 3488 LD_F16 = 708, 3489 CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 709, 3490 FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 710, 3491 ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 711, 3492 ROTRV = 712, 3493 ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 713, 3494 ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 714, 3495 ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 715, 3496 LEA_ADDiu = 716, 3497 ADDIUPC = 717, 3498 ALIGN = 718, 3499 ALUIPC = 719, 3500 AUI = 720, 3501 AUIPC = 721, 3502 BITSWAP = 722, 3503 CLO_R6 = 723, 3504 CLZ_R6 = 724, 3505 LSA_R6 = 725, 3506 SELEQZ_SELNEZ = 726, 3507 AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 727, 3508 SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 728, 3509 Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 729, 3510 ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 730, 3511 ADDU16_MM_ADDu_MM = 731, 3512 ADD_MM = 732, 3513 ADDi_MM = 733, 3514 AND16_MM_ANDI16_MM_AND_MM = 734, 3515 ANDi_MM = 735, 3516 CLO_MM = 736, 3517 CLZ_MM = 737, 3518 EXT_MM = 738, 3519 INS_MM = 739, 3520 LI16_MM = 740, 3521 LUi_MM = 741, 3522 MOVE16_MM = 742, 3523 MOVEP_MM = 743, 3524 NOR_MM = 744, 3525 NOT16_MM = 745, 3526 OR16_MM_OR_MM = 746, 3527 ORi_MM = 747, 3528 ROTRV_MM = 748, 3529 ROTR_MM = 749, 3530 SEB_MM = 750, 3531 SEH_MM = 751, 3532 SLL16_MM_SLL_MM = 752, 3533 SLLV_MM = 753, 3534 SLT_MM_SLTu_MM = 754, 3535 SLTi_MM_SLTiu_MM = 755, 3536 SRAV_MM = 756, 3537 SRA_MM = 757, 3538 SRL16_MM_SRL_MM = 758, 3539 SRLV_MM = 759, 3540 SSNOP_MM = 760, 3541 SUBU16_MM_SUBu_MM = 761, 3542 SUB_MM = 762, 3543 WSBH_MM = 763, 3544 XOR16_MM_XOR_MM = 764, 3545 XORi_MM = 765, 3546 ADDIUPC_MMR6 = 766, 3547 ADDIU_MMR6 = 767, 3548 ADDU16_MMR6_ADDU_MMR6 = 768, 3549 ADD_MMR6 = 769, 3550 ALIGN_MMR6 = 770, 3551 ALUIPC_MMR6 = 771, 3552 AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 772, 3553 ANDI_MMR6 = 773, 3554 AUIPC_MMR6 = 774, 3555 AUI_MMR6 = 775, 3556 BITSWAP_MMR6 = 776, 3557 CLO_MMR6 = 777, 3558 CLZ_MMR6 = 778, 3559 EXT_MMR6 = 779, 3560 INS_MMR6 = 780, 3561 LI16_MMR6 = 781, 3562 LSA_MMR6 = 782, 3563 LUI_MMR6 = 783, 3564 MOVE16_MMR6 = 784, 3565 NOR_MMR6 = 785, 3566 NOT16_MMR6 = 786, 3567 OR16_MMR6_OR_MMR6 = 787, 3568 ORI_MMR6 = 788, 3569 SELEQZ_MMR6_SELNEZ_MMR6 = 789, 3570 SLL16_MMR6_SLL_MMR6 = 790, 3571 SRL16_MMR6 = 791, 3572 SSNOP_MMR6 = 792, 3573 SUBU16_MMR6_SUBU_MMR6 = 793, 3574 SUB_MMR6 = 794, 3575 WSBH_MMR6 = 795, 3576 XOR16_MMR6_XOR_MMR6 = 796, 3577 XORI_MMR6 = 797, 3578 AND64_ANDi64 = 798, 3579 DEXT64_32 = 799, 3580 DSLL64_32 = 800, 3581 ORi64 = 801, 3582 SEB64 = 802, 3583 SEH64 = 803, 3584 SLL64_32_SLL64_64 = 804, 3585 SLT64_SLTu64 = 805, 3586 SLTi64_SLTiu64 = 806, 3587 XOR64_XORi64 = 807, 3588 DADD = 808, 3589 DADDi = 809, 3590 DADDiu = 810, 3591 DADDu = 811, 3592 DCLO = 812, 3593 DCLZ = 813, 3594 DEXT_DEXTM_DEXTU = 814, 3595 DINS_DINSM_DINSU = 815, 3596 DROTR = 816, 3597 DROTR32 = 817, 3598 DROTRV = 818, 3599 DSBH = 819, 3600 DSHD = 820, 3601 DSLL = 821, 3602 DSLL32 = 822, 3603 DSLLV = 823, 3604 DSRA = 824, 3605 DSRA32 = 825, 3606 DSRAV = 826, 3607 DSRL = 827, 3608 DSRL32 = 828, 3609 DSRLV = 829, 3610 DSUB = 830, 3611 DSUBu = 831, 3612 LEA_ADDiu64 = 832, 3613 LUi64 = 833, 3614 NOR64 = 834, 3615 OR64 = 835, 3616 DALIGN = 836, 3617 DAHI = 837, 3618 DATI = 838, 3619 DAUI = 839, 3620 DCLO_R6 = 840, 3621 DCLZ_R6 = 841, 3622 DBITSWAP = 842, 3623 DLSA_DLSA_R6 = 843, 3624 SELEQZ64_SELNEZ64 = 844, 3625 MADD = 845, 3626 MADDU = 846, 3627 MSUB = 847, 3628 MSUBU = 848, 3629 PseudoMADD_MM = 849, 3630 PseudoMADDU_MM = 850, 3631 PseudoMSUB_MM = 851, 3632 PseudoMSUBU_MM = 852, 3633 PseudoMULT_MM = 853, 3634 PseudoMULTu_MM = 854, 3635 PseudoMULT = 855, 3636 PseudoMULTu = 856, 3637 PseudoSDIV_SDIV = 857, 3638 PseudoUDIV_UDIV = 858, 3639 PseudoMFHI_MM_PseudoMFLO_MM = 859, 3640 PseudoMTLOHI_MM = 860, 3641 MUH = 861, 3642 MUHU = 862, 3643 MULU = 863, 3644 MUL_R6 = 864, 3645 MOD = 865, 3646 MODU = 866, 3647 MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 867, 3648 DivRxRy16 = 868, 3649 DivuRxRy16 = 869, 3650 MULT_MM = 870, 3651 MULTu_MM = 871, 3652 MADD_MM = 872, 3653 MADDU_MM = 873, 3654 MSUB_MM = 874, 3655 MSUBU_MM = 875, 3656 MUL_MM = 876, 3657 SDIV_MM_SDIV_MM_Pseudo = 877, 3658 UDIV_MM_UDIV_MM_Pseudo = 878, 3659 MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 879, 3660 MOVF_I_MM = 880, 3661 MOVT_I_MM = 881, 3662 MTHI_MM_MTLO_MM = 882, 3663 RDHWR_MM = 883, 3664 MUHU_MMR6 = 884, 3665 MUH_MMR6 = 885, 3666 MULU_MMR6 = 886, 3667 MUL_MMR6 = 887, 3668 MODU_MMR6 = 888, 3669 MOD_MMR6 = 889, 3670 DIVU_MMR6 = 890, 3671 DIV_MMR6 = 891, 3672 RDHWR_MMR6 = 892, 3673 DMULU = 893, 3674 DMULT_PseudoDMULT = 894, 3675 DMULTu_PseudoDMULTu = 895, 3676 DSDIV_PseudoDSDIV = 896, 3677 DUDIV_PseudoDUDIV = 897, 3678 MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 898, 3679 PseudoMTLOHI64 = 899, 3680 MTHI64_MTLO64 = 900, 3681 RDHWR64 = 901, 3682 MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 902, 3683 MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 903, 3684 DMUH = 904, 3685 DMUHU = 905, 3686 DMUL_R6 = 906, 3687 DDIV = 907, 3688 DMOD = 908, 3689 DDIVU = 909, 3690 DMODU = 910, 3691 BAL_BR_BLTZAL = 911, 3692 BEQ_BNE = 912, 3693 BGTZ_BGEZ_BLEZ_BLTZ = 913, 3694 J = 914, 3695 JR = 915, 3696 ERet = 916, 3697 BGEZAL = 917, 3698 BALC = 918, 3699 BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 919, 3700 JIALC = 920, 3701 BC = 921, 3702 BC2EQZ_BC2NEZ = 922, 3703 BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 923, 3704 BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 924, 3705 JIC = 925, 3706 JR_HB_R6 = 926, 3707 SIGRIE = 927, 3708 PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 928, 3709 TAILCALLR6REG_TAILCALLHBR6REG = 929, 3710 SDBBP_R6 = 930, 3711 Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 931, 3712 BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 932, 3713 Jal16_JalB16 = 933, 3714 JumpLinkReg16 = 934, 3715 Break16 = 935, 3716 SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 936, 3717 B16_MM_B_MM = 937, 3718 BAL_BR_MM = 938, 3719 BC1F_MM = 939, 3720 BC1T_MM = 940, 3721 BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 941, 3722 BEQZC_MM_BNEZC_MM = 942, 3723 BEQ_MM_BNE_MM = 943, 3724 DERET_MM = 944, 3725 ERET_MM = 945, 3726 JR16_MM_JR_MM = 946, 3727 J_MM = 947, 3728 B_MM_Pseudo = 948, 3729 BGEZALS_MM_BLTZALS_MM = 949, 3730 BGEZAL_MM_BLTZAL_MM = 950, 3731 JALR16_MM_JALR_MM = 951, 3732 JALRS16_MM_JALRS_MM = 952, 3733 JALS_MM = 953, 3734 JALX_MM_JAL_MM = 954, 3735 TAILCALLREG_MM = 955, 3736 TAILCALL_MM = 956, 3737 PseudoIndirectBranch_MM = 957, 3738 BREAK16_MM_BREAK_MM = 958, 3739 SDBBP16_MM_SDBBP_MM = 959, 3740 SYSCALL_MM = 960, 3741 TEQI_MM = 961, 3742 TEQ_MM = 962, 3743 TGEIU_MM = 963, 3744 TGEI_MM = 964, 3745 TGEU_MM = 965, 3746 TGE_MM = 966, 3747 TLTIU_MM = 967, 3748 TLTI_MM = 968, 3749 TLTU_MM = 969, 3750 TLT_MM = 970, 3751 TNEI_MM = 971, 3752 TNE_MM = 972, 3753 TRAP_MM = 973, 3754 BC16_MMR6_BC_MMR6 = 974, 3755 BC1EQZC_MMR6_BC1NEZC_MMR6 = 975, 3756 BC2EQZC_MMR6_BC2NEZC_MMR6 = 976, 3757 BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 977, 3758 BEQZC16_MMR6_BNEZC16_MMR6 = 978, 3759 BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 979, 3760 DERET_MMR6 = 980, 3761 ERETNC_MMR6 = 981, 3762 JAL_MMR6 = 982, 3763 ERET_MMR6 = 983, 3764 JIC_MMR6 = 984, 3765 JRADDIUSP_JRCADDIUSP_MMR6 = 985, 3766 JRC16_MM = 986, 3767 JRC16_MMR6 = 987, 3768 SIGRIE_MMR6 = 988, 3769 B_MMR6_Pseudo = 989, 3770 PseudoIndirectBranch_MMR6 = 990, 3771 BALC_MMR6 = 991, 3772 BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 992, 3773 JALRC16_MMR6 = 993, 3774 JALRC_HB_MMR6 = 994, 3775 JALRC_MMR6 = 995, 3776 JIALC_MMR6 = 996, 3777 TAILCALLREG_MMR6 = 997, 3778 TAILCALL_MMR6 = 998, 3779 BREAK16_MMR6_BREAK_MMR6 = 999, 3780 SDBBP_MMR6_SDBBP16_MMR6 = 1000, 3781 BEQ64_BNE64 = 1001, 3782 BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1002, 3783 JR64 = 1003, 3784 JALR64_JALR64Pseudo_JALRHB64Pseudo = 1004, 3785 JALR_HB64 = 1005, 3786 JR_HB64 = 1006, 3787 TAILCALLREG64_TAILCALLREGHB64 = 1007, 3788 PseudoReturn64 = 1008, 3789 BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1009, 3790 BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1010, 3791 JIC64 = 1011, 3792 PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1012, 3793 JIALC64 = 1013, 3794 JR_HB64_R6 = 1014, 3795 TAILCALL64R6REG_TAILCALLHB64R6REG = 1015, 3796 PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1016, 3797 EVP = 1017, 3798 DVP = 1018, 3799 TLBP_MM = 1019, 3800 TLBR_MM = 1020, 3801 TLBWI_MM = 1021, 3802 TLBWR_MM = 1022, 3803 DI_MM = 1023, 3804 EI_MM = 1024, 3805 EHB_MM = 1025, 3806 PAUSE_MM = 1026, 3807 WAIT_MM = 1027, 3808 RDPGPR_MMR6 = 1028, 3809 WRPGPR_MMR6 = 1029, 3810 TLBINV_MMR6 = 1030, 3811 TLBINVF_MMR6 = 1031, 3812 MFHC0_MMR6 = 1032, 3813 MFC0_MMR6 = 1033, 3814 MFHC2_MMR6_MFC2_MMR6 = 1034, 3815 MTHC0_MMR6 = 1035, 3816 MTC0_MMR6 = 1036, 3817 MTHC2_MMR6_MTC2_MMR6 = 1037, 3818 EVP_MMR6 = 1038, 3819 DVP_MMR6 = 1039, 3820 DI_MMR6 = 1040, 3821 EI_MMR6 = 1041, 3822 EHB_MMR6 = 1042, 3823 PAUSE_MMR6 = 1043, 3824 WAIT_MMR6 = 1044, 3825 DMFC0 = 1045, 3826 DMTC0 = 1046, 3827 DMFC2 = 1047, 3828 DMTC2 = 1048, 3829 CFC2_MM = 1049, 3830 CTC2_MM = 1050, 3831 DMT = 1051, 3832 DVPE = 1052, 3833 EMT = 1053, 3834 EVPE = 1054, 3835 MFTR = 1055, 3836 MTTR = 1056, 3837 YIELD = 1057, 3838 FORK = 1058, 3839 DMFGC0 = 1059, 3840 DMTGC0 = 1060, 3841 HYPCALL_MM = 1061, 3842 TLBGINVF_MM = 1062, 3843 TLBGINV_MM = 1063, 3844 TLBGP_MM = 1064, 3845 TLBGR_MM = 1065, 3846 TLBGWI_MM = 1066, 3847 TLBGWR_MM = 1067, 3848 MFGC0_MM = 1068, 3849 MFHGC0_MM = 1069, 3850 MTGC0_MM = 1070, 3851 MTHGC0_MM = 1071, 3852 SC_MMR6 = 1072, 3853 LDC2_R6 = 1073, 3854 LL_R6 = 1074, 3855 LWC2_R6 = 1075, 3856 SWC2_R6 = 1076, 3857 SDC2_R6 = 1077, 3858 SC_R6 = 1078, 3859 PREF_R6 = 1079, 3860 CACHE_R6 = 1080, 3861 GINVI = 1081, 3862 GINVT = 1082, 3863 LBE_MM = 1083, 3864 LBuE_MM = 1084, 3865 LHE_MM = 1085, 3866 LHuE_MM = 1086, 3867 LWE_MM = 1087, 3868 LWLE_MM = 1088, 3869 LWRE_MM = 1089, 3870 LLE_MM = 1090, 3871 SBE_MM = 1091, 3872 SB_MM = 1092, 3873 SHE_MM = 1093, 3874 SWE_MM = 1094, 3875 SWLE_MM = 1095, 3876 SWRE_MM = 1096, 3877 SCE_MM = 1097, 3878 PREFE_MM = 1098, 3879 CACHEE_MM = 1099, 3880 Restore16_RestoreX16 = 1100, 3881 LbRxRyOffMemX16 = 1101, 3882 LbuRxRyOffMemX16 = 1102, 3883 LhRxRyOffMemX16 = 1103, 3884 LhuRxRyOffMemX16 = 1104, 3885 LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1105, 3886 Save16_SaveX16 = 1106, 3887 SbRxRyOffMemX16 = 1107, 3888 ShRxRyOffMemX16 = 1108, 3889 SwRxRyOffMemX16_SwRxSpImmX16 = 1109, 3890 LBU16_MM_LBu_MM = 1110, 3891 LB_MM = 1111, 3892 LHU16_MM_LHu_MM = 1112, 3893 LH_MM = 1113, 3894 LL_MM = 1114, 3895 LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1115, 3896 LWL_MM = 1116, 3897 LWM16_MM_LWM32_MM = 1117, 3898 LWP_MM = 1118, 3899 LWR_MM = 1119, 3900 LWU_MM = 1120, 3901 LWXS_MM = 1121, 3902 SB16_MM = 1122, 3903 SC_MM = 1123, 3904 SH16_MM_SH_MM = 1124, 3905 SW16_MM_SWSP_MM_SW_MM = 1125, 3906 SWL_MM = 1126, 3907 SWM16_MM_SWM32_MM = 1127, 3908 SWM_MM = 1128, 3909 SWP_MM = 1129, 3910 SWR_MM = 1130, 3911 PREF_MM_PREFX_MM = 1131, 3912 CACHE_MM = 1132, 3913 SYNC_MM = 1133, 3914 SYNCI_MM = 1134, 3915 GINVI_MMR6 = 1135, 3916 GINVT_MMR6 = 1136, 3917 LBU_MMR6 = 1137, 3918 LB_MMR6 = 1138, 3919 LDC2_MMR6 = 1139, 3920 LL_MMR6 = 1140, 3921 LWM16_MMR6 = 1141, 3922 LWC2_MMR6 = 1142, 3923 LWPC_MMR6 = 1143, 3924 LW_MMR6 = 1144, 3925 SB16_MMR6_SB_MMR6 = 1145, 3926 SDC2_MMR6 = 1146, 3927 SH16_MMR6_SH_MMR6 = 1147, 3928 SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1148, 3929 SWC2_MMR6 = 1149, 3930 SWM16_MMR6 = 1150, 3931 SYNC_MMR6 = 1151, 3932 SYNCI_MMR6 = 1152, 3933 PREF_MMR6 = 1153, 3934 CACHE_MMR6 = 1154, 3935 LD = 1155, 3936 LL64_LLD = 1156, 3937 LWu = 1157, 3938 LB64 = 1158, 3939 LBu64 = 1159, 3940 LH64 = 1160, 3941 LHu64 = 1161, 3942 LW64 = 1162, 3943 LWL64 = 1163, 3944 LWR64 = 1164, 3945 LDL = 1165, 3946 LDR = 1166, 3947 SD = 1167, 3948 SC64_SCD = 1168, 3949 SB64 = 1169, 3950 SH64 = 1170, 3951 SW64 = 1171, 3952 SWL64 = 1172, 3953 SWR64 = 1173, 3954 SDL = 1174, 3955 SDR = 1175, 3956 LWUPC = 1176, 3957 LDPC = 1177, 3958 LLD_R6 = 1178, 3959 LL64_R6 = 1179, 3960 SC64_R6 = 1180, 3961 SCD_R6 = 1181, 3962 CRC32B = 1182, 3963 CRC32H = 1183, 3964 CRC32W = 1184, 3965 CRC32CB = 1185, 3966 CRC32CH = 1186, 3967 CRC32CW = 1187, 3968 CRC32D = 1188, 3969 CRC32CD = 1189, 3970 BADDu = 1190, 3971 BBIT0_BBIT032_BBIT1_BBIT132 = 1191, 3972 CINS_CINS32_CINS64_32_CINS_i32 = 1192, 3973 DMFC2_OCTEON = 1193, 3974 DMTC2_OCTEON = 1194, 3975 DPOP_POP = 1195, 3976 EXTS_EXTS32 = 1196, 3977 MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1197, 3978 SEQ_SNE = 1198, 3979 SEQi_SNEi = 1199, 3980 V3MULU_VMM0_VMULU = 1200, 3981 DMUL = 1201, 3982 SAA_SAAD = 1202, 3983 PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1203, 3984 MOVT_I64 = 1204, 3985 MOVF_I64 = 1205, 3986 MOVZ_I64_S = 1206, 3987 MOVN_I64_D64 = 1207, 3988 MOVN_I64_S = 1208, 3989 MOVZ_I64_D64 = 1209, 3990 SELEQZ_S_SELNEZ_S = 1210, 3991 SELEQZ_D_SELNEZ_D = 1211, 3992 MAX_S_MAXA_S = 1212, 3993 MAX_D_MAXA_D = 1213, 3994 MIN_S_MINA_D = 1214, 3995 MIN_D_MINA_S = 1215, 3996 CLASS_S = 1216, 3997 CLASS_D = 1217, 3998 RINT_S = 1218, 3999 RINT_D = 1219, 4000 BC1EQZ_BC1NEZ = 1220, 4001 SEL_D = 1221, 4002 SEL_S = 1222, 4003 MADDF_S = 1223, 4004 MSUBF_S = 1224, 4005 MADDF_D = 1225, 4006 MSUBF_D = 1226, 4007 MOVF_D32_MM = 1227, 4008 MOVF_S_MM = 1228, 4009 MOVN_I_D32_MM = 1229, 4010 MOVN_I_S_MM = 1230, 4011 MOVT_D32_MM = 1231, 4012 MOVT_S_MM = 1232, 4013 MOVZ_I_D32_MM = 1233, 4014 MOVZ_I_S_MM = 1234, 4015 CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1235, 4016 CEIL_W_MM_CEIL_W_S_MM = 1236, 4017 FLOOR_W_MM_FLOOR_W_S_MM = 1237, 4018 NMADD_S_MM = 1238, 4019 NMADD_D32_MM = 1239, 4020 NMSUB_S_MM = 1240, 4021 NMSUB_D32_MM = 1241, 4022 MADD_S_MM = 1242, 4023 MADD_D32_MM = 1243, 4024 ROUND_W_MM_ROUND_W_S_MM = 1244, 4025 TRUNC_W_MM_TRUNC_W_S_MM = 1245, 4026 C_F_D32_MM_C_F_D64_MM = 1246, 4027 C_F_S_MM = 1247, 4028 C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1248, 4029 C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1249, 4030 C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1250, 4031 C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1251, 4032 C_NGLE_D32_MM_C_NGLE_D64_MM = 1252, 4033 C_NGLE_S_MM = 1253, 4034 FCMP_S32_MM = 1254, 4035 FCMP_D32_MM = 1255, 4036 MFC1_MM = 1256, 4037 MFHC1_D32_MM_MFHC1_D64_MM = 1257, 4038 MTC1_MM_MTC1_D64_MM = 1258, 4039 MTHC1_D32_MM_MTHC1_D64_MM = 1259, 4040 FABS_D32_MM_FABS_D64_MM = 1260, 4041 FABS_S_MM = 1261, 4042 FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1262, 4043 FADD_D32_MM_FADD_D64_MM = 1263, 4044 FADD_S_MM = 1264, 4045 FMOV_D32_MM_FMOV_D64_MM = 1265, 4046 FMOV_S_MM = 1266, 4047 FMUL_D32_MM_FMUL_D64_MM = 1267, 4048 FMUL_S_MM = 1268, 4049 FSUB_D32_MM_FSUB_D64_MM = 1269, 4050 FSUB_S_MM = 1270, 4051 MSUB_S_MM = 1271, 4052 MSUB_D32_MM = 1272, 4053 FDIV_S_MM = 1273, 4054 FDIV_D32_MM_FDIV_D64_MM = 1274, 4055 FSQRT_S_MM = 1275, 4056 FSQRT_D32_MM_FSQRT_D64_MM = 1276, 4057 RECIP_S_MM_RSQRT_S_MM = 1277, 4058 RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1278, 4059 SDC1_MM = 1279, 4060 SWC1_MM = 1280, 4061 SUXC1_MM = 1281, 4062 SWXC1_MM = 1282, 4063 CFC1_MM = 1283, 4064 CTC1_MM = 1284, 4065 LDC1_MM = 1285, 4066 LUXC1_MM = 1286, 4067 LWC1_MM = 1287, 4068 LWXC1_MM = 1288, 4069 FNEG_S_MMR6 = 1289, 4070 CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1290, 4071 CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1291, 4072 CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1292, 4073 CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1293, 4074 CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1294, 4075 CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1295, 4076 CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1296, 4077 TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1297, 4078 ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1298, 4079 FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1299, 4080 CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1300, 4081 MFC1_MMR6 = 1301, 4082 MTC1_MMR6 = 1302, 4083 CLASS_S_MMR6_CLASS_D_MMR6 = 1303, 4084 FADD_S_MMR6 = 1304, 4085 MAX_D_MMR6 = 1305, 4086 MAX_S_MMR6 = 1306, 4087 MIN_D_MMR6 = 1307, 4088 MIN_S_MMR6 = 1308, 4089 MAXA_D_MMR6 = 1309, 4090 MAXA_S_MMR6 = 1310, 4091 MINA_D_MMR6 = 1311, 4092 MINA_S_MMR6 = 1312, 4093 SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1313, 4094 SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1314, 4095 SEL_D_MMR6 = 1315, 4096 SEL_S_MMR6 = 1316, 4097 RINT_S_MMR6_RINT_D_MMR6 = 1317, 4098 MADDF_D_MMR6 = 1318, 4099 MADDF_S_MMR6 = 1319, 4100 MSUBF_D_MMR6 = 1320, 4101 MSUBF_S_MMR6 = 1321, 4102 FMOV_S_MMR6 = 1322, 4103 FMUL_S_MMR6 = 1323, 4104 FSUB_S_MMR6 = 1324, 4105 FMOV_D_MMR6 = 1325, 4106 FDIV_S_MMR6 = 1326, 4107 SDC1_D64_MMR6 = 1327, 4108 LDC1_D64_MMR6 = 1328, 4109 DMFC1 = 1329, 4110 DMTC1 = 1330, 4111 SWDSP = 1331, 4112 LWDSP = 1332, 4113 PseudoMTLOHI_DSP = 1333, 4114 EXTRV_RS_W = 1334, 4115 EXTRV_R_W = 1335, 4116 EXTRV_S_H = 1336, 4117 EXTRV_W = 1337, 4118 EXTR_RS_W = 1338, 4119 EXTR_R_W = 1339, 4120 EXTR_S_H = 1340, 4121 EXTR_W = 1341, 4122 INSV = 1342, 4123 MTHLIP = 1343, 4124 MTHI_DSP = 1344, 4125 MTLO_DSP = 1345, 4126 ABSQ_S_PH = 1346, 4127 ABSQ_S_W = 1347, 4128 ADDQ_PH = 1348, 4129 ADDQ_S_PH = 1349, 4130 ADDQ_S_W = 1350, 4131 ADDSC = 1351, 4132 ADDU_QB = 1352, 4133 ADDU_S_QB = 1353, 4134 ADDWC = 1354, 4135 BITREV = 1355, 4136 BPOSGE32 = 1356, 4137 CMPGU_EQ_QB = 1357, 4138 CMPGU_LE_QB = 1358, 4139 CMPGU_LT_QB = 1359, 4140 CMPU_EQ_QB = 1360, 4141 CMPU_LE_QB = 1361, 4142 CMPU_LT_QB = 1362, 4143 CMP_EQ_PH = 1363, 4144 CMP_LE_PH = 1364, 4145 CMP_LT_PH = 1365, 4146 DPAQ_SA_L_W = 1366, 4147 DPAQ_S_W_PH = 1367, 4148 DPAU_H_QBL = 1368, 4149 DPAU_H_QBR = 1369, 4150 DPSQ_SA_L_W = 1370, 4151 DPSQ_S_W_PH = 1371, 4152 DPSU_H_QBL = 1372, 4153 DPSU_H_QBR = 1373, 4154 EXTPDPV = 1374, 4155 EXTPDP = 1375, 4156 EXTPV = 1376, 4157 EXTP = 1377, 4158 LBUX = 1378, 4159 LHX = 1379, 4160 LWX = 1380, 4161 MADDU_DSP = 1381, 4162 MADD_DSP = 1382, 4163 MAQ_SA_W_PHL = 1383, 4164 MAQ_SA_W_PHR = 1384, 4165 MAQ_S_W_PHL = 1385, 4166 MAQ_S_W_PHR = 1386, 4167 MFHI_DSP = 1387, 4168 MFLO_DSP = 1388, 4169 MODSUB = 1389, 4170 MSUBU_DSP = 1390, 4171 MSUB_DSP = 1391, 4172 MULEQ_S_W_PHL = 1392, 4173 MULEQ_S_W_PHR = 1393, 4174 MULEU_S_PH_QBL = 1394, 4175 MULEU_S_PH_QBR = 1395, 4176 MULQ_RS_PH = 1396, 4177 MULSAQ_S_W_PH = 1397, 4178 MULTU_DSP = 1398, 4179 MULT_DSP = 1399, 4180 PACKRL_PH = 1400, 4181 PICK_PH = 1401, 4182 PICK_QB = 1402, 4183 PRECEQU_PH_QBLA = 1403, 4184 PRECEQU_PH_QBL = 1404, 4185 PRECEQU_PH_QBRA = 1405, 4186 PRECEQU_PH_QBR = 1406, 4187 PRECEQ_W_PHL = 1407, 4188 PRECEQ_W_PHR = 1408, 4189 PRECEU_PH_QBLA = 1409, 4190 PRECEU_PH_QBL = 1410, 4191 PRECEU_PH_QBRA = 1411, 4192 PRECEU_PH_QBR = 1412, 4193 PRECRQU_S_QB_PH = 1413, 4194 PRECRQ_PH_W = 1414, 4195 PRECRQ_QB_PH = 1415, 4196 PRECRQ_RS_PH_W = 1416, 4197 RADDU_W_QB = 1417, 4198 RDDSP = 1418, 4199 REPLV_PH = 1419, 4200 REPLV_QB = 1420, 4201 REPL_PH = 1421, 4202 REPL_QB = 1422, 4203 SHILOV = 1423, 4204 SHILO = 1424, 4205 SHLLV_PH = 1425, 4206 SHLLV_QB = 1426, 4207 SHLLV_S_PH = 1427, 4208 SHLLV_S_W = 1428, 4209 SHLL_PH = 1429, 4210 SHLL_QB = 1430, 4211 SHLL_S_PH = 1431, 4212 SHLL_S_W = 1432, 4213 SHRAV_PH = 1433, 4214 SHRAV_R_PH = 1434, 4215 SHRAV_R_W = 1435, 4216 SHRA_PH = 1436, 4217 SHRA_R_PH = 1437, 4218 SHRA_R_W = 1438, 4219 SHRLV_QB = 1439, 4220 SHRL_QB = 1440, 4221 SUBQ_PH = 1441, 4222 SUBQ_S_PH = 1442, 4223 SUBQ_S_W = 1443, 4224 SUBU_QB = 1444, 4225 SUBU_S_QB = 1445, 4226 WRDSP = 1446, 4227 PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1447, 4228 PseudoPICK_PH_PseudoPICK_QB = 1448, 4229 ABSQ_S_QB = 1449, 4230 ADDQH_PH = 1450, 4231 ADDQH_R_PH = 1451, 4232 ADDQH_R_W = 1452, 4233 ADDQH_W = 1453, 4234 ADDUH_QB = 1454, 4235 ADDUH_R_QB = 1455, 4236 ADDU_PH = 1456, 4237 ADDU_S_PH = 1457, 4238 APPEND = 1458, 4239 BALIGN = 1459, 4240 CMPGDU_EQ_QB = 1460, 4241 CMPGDU_LE_QB = 1461, 4242 CMPGDU_LT_QB = 1462, 4243 DPA_W_PH = 1463, 4244 DPAQX_SA_W_PH = 1464, 4245 DPAQX_S_W_PH = 1465, 4246 DPAX_W_PH = 1466, 4247 DPS_W_PH = 1467, 4248 DPSQX_S_W_PH = 1468, 4249 DPSQX_SA_W_PH = 1469, 4250 DPSX_W_PH = 1470, 4251 MUL_PH = 1471, 4252 MUL_S_PH = 1472, 4253 MULQ_RS_W = 1473, 4254 MULQ_S_PH = 1474, 4255 MULQ_S_W = 1475, 4256 MULSA_W_PH = 1476, 4257 PRECR_QB_PH = 1477, 4258 PRECR_SRA_PH_W = 1478, 4259 PRECR_SRA_R_PH_W = 1479, 4260 PREPEND = 1480, 4261 SHRA_QB = 1481, 4262 SHRA_R_QB = 1482, 4263 SHRAV_QB = 1483, 4264 SHRAV_R_QB = 1484, 4265 SHRL_PH = 1485, 4266 SHRLV_PH = 1486, 4267 SUBQH_PH = 1487, 4268 SUBQH_R_PH = 1488, 4269 SUBQH_W = 1489, 4270 SUBQH_R_W = 1490, 4271 SUBU_PH = 1491, 4272 SUBU_S_PH = 1492, 4273 SUBUH_QB = 1493, 4274 SUBUH_R_QB = 1494, 4275 LWDSP_MM = 1495, 4276 SWDSP_MM = 1496, 4277 ABSQ_S_PH_MM = 1497, 4278 ABSQ_S_W_MM = 1498, 4279 ADDQ_PH_MM = 1499, 4280 ADDQ_S_PH_MM = 1500, 4281 ADDQ_S_W_MM = 1501, 4282 ADDSC_MM = 1502, 4283 ADDU_QB_MM = 1503, 4284 ADDU_S_QB_MM = 1504, 4285 ADDWC_MM = 1505, 4286 BITREV_MM = 1506, 4287 BPOSGE32_MM = 1507, 4288 CMPGU_EQ_QB_MM = 1508, 4289 CMPGU_LE_QB_MM = 1509, 4290 CMPGU_LT_QB_MM = 1510, 4291 CMPU_EQ_QB_MM = 1511, 4292 CMPU_LE_QB_MM = 1512, 4293 CMPU_LT_QB_MM = 1513, 4294 CMP_EQ_PH_MM = 1514, 4295 CMP_LE_PH_MM = 1515, 4296 CMP_LT_PH_MM = 1516, 4297 DPAQ_SA_L_W_MM = 1517, 4298 DPAQ_S_W_PH_MM = 1518, 4299 DPAU_H_QBL_MM = 1519, 4300 DPAU_H_QBR_MM = 1520, 4301 DPSQ_SA_L_W_MM = 1521, 4302 DPSQ_S_W_PH_MM = 1522, 4303 DPSU_H_QBL_MM = 1523, 4304 DPSU_H_QBR_MM = 1524, 4305 EXTPDPV_MM = 1525, 4306 EXTPDP_MM = 1526, 4307 EXTPV_MM = 1527, 4308 EXTP_MM = 1528, 4309 EXTRV_RS_W_MM = 1529, 4310 EXTRV_R_W_MM = 1530, 4311 EXTRV_S_H_MM = 1531, 4312 EXTRV_W_MM = 1532, 4313 EXTR_RS_W_MM = 1533, 4314 EXTR_R_W_MM = 1534, 4315 EXTR_S_H_MM = 1535, 4316 EXTR_W_MM = 1536, 4317 INSV_MM = 1537, 4318 LBUX_MM = 1538, 4319 LHX_MM = 1539, 4320 LWX_MM = 1540, 4321 MADDU_DSP_MM = 1541, 4322 MADD_DSP_MM = 1542, 4323 MAQ_SA_W_PHL_MM = 1543, 4324 MAQ_SA_W_PHR_MM = 1544, 4325 MAQ_S_W_PHL_MM = 1545, 4326 MAQ_S_W_PHR_MM = 1546, 4327 MFHI_DSP_MM = 1547, 4328 MFLO_DSP_MM = 1548, 4329 MODSUB_MM = 1549, 4330 MOVEP_MMR6 = 1550, 4331 MOVN_I_MM = 1551, 4332 MOVZ_I_MM = 1552, 4333 MSUBU_DSP_MM = 1553, 4334 MSUB_DSP_MM = 1554, 4335 MTHI_DSP_MM = 1555, 4336 MTHLIP_MM = 1556, 4337 MTLO_DSP_MM = 1557, 4338 MULEQ_S_W_PHL_MM = 1558, 4339 MULEQ_S_W_PHR_MM = 1559, 4340 MULEU_S_PH_QBL_MM = 1560, 4341 MULEU_S_PH_QBR_MM = 1561, 4342 MULQ_RS_PH_MM = 1562, 4343 MULSAQ_S_W_PH_MM = 1563, 4344 MULTU_DSP_MM = 1564, 4345 MULT_DSP_MM = 1565, 4346 PACKRL_PH_MM = 1566, 4347 PICK_PH_MM = 1567, 4348 PICK_QB_MM = 1568, 4349 PRECEQU_PH_QBLA_MM = 1569, 4350 PRECEQU_PH_QBL_MM = 1570, 4351 PRECEQU_PH_QBRA_MM = 1571, 4352 PRECEQU_PH_QBR_MM = 1572, 4353 PRECEQ_W_PHL_MM = 1573, 4354 PRECEQ_W_PHR_MM = 1574, 4355 PRECEU_PH_QBLA_MM = 1575, 4356 PRECEU_PH_QBL_MM = 1576, 4357 PRECEU_PH_QBRA_MM = 1577, 4358 PRECEU_PH_QBR_MM = 1578, 4359 PRECRQU_S_QB_PH_MM = 1579, 4360 PRECRQ_PH_W_MM = 1580, 4361 PRECRQ_QB_PH_MM = 1581, 4362 PRECRQ_RS_PH_W_MM = 1582, 4363 RADDU_W_QB_MM = 1583, 4364 RDDSP_MM = 1584, 4365 REPLV_PH_MM = 1585, 4366 REPLV_QB_MM = 1586, 4367 REPL_PH_MM = 1587, 4368 REPL_QB_MM = 1588, 4369 SHILOV_MM = 1589, 4370 SHILO_MM = 1590, 4371 SHLLV_PH_MM = 1591, 4372 SHLLV_QB_MM = 1592, 4373 SHLLV_S_PH_MM = 1593, 4374 SHLLV_S_W_MM = 1594, 4375 SHLL_PH_MM = 1595, 4376 SHLL_QB_MM = 1596, 4377 SHLL_S_PH_MM = 1597, 4378 SHLL_S_W_MM = 1598, 4379 SHRAV_PH_MM = 1599, 4380 SHRAV_R_PH_MM = 1600, 4381 SHRAV_R_W_MM = 1601, 4382 SHRA_PH_MM = 1602, 4383 SHRA_R_PH_MM = 1603, 4384 SHRA_R_W_MM = 1604, 4385 SHRLV_QB_MM = 1605, 4386 SHRL_QB_MM = 1606, 4387 SUBQ_PH_MM = 1607, 4388 SUBQ_S_PH_MM = 1608, 4389 SUBQ_S_W_MM = 1609, 4390 SUBU_QB_MM = 1610, 4391 SUBU_S_QB_MM = 1611, 4392 WRDSP_MM = 1612, 4393 ABSQ_S_QB_MMR2 = 1613, 4394 ADDQH_PH_MMR2 = 1614, 4395 ADDQH_R_PH_MMR2 = 1615, 4396 ADDQH_R_W_MMR2 = 1616, 4397 ADDQH_W_MMR2 = 1617, 4398 ADDUH_QB_MMR2 = 1618, 4399 ADDUH_R_QB_MMR2 = 1619, 4400 ADDU_PH_MMR2 = 1620, 4401 ADDU_S_PH_MMR2 = 1621, 4402 APPEND_MMR2 = 1622, 4403 BALIGN_MMR2 = 1623, 4404 CMPGDU_EQ_QB_MMR2 = 1624, 4405 CMPGDU_LE_QB_MMR2 = 1625, 4406 CMPGDU_LT_QB_MMR2 = 1626, 4407 DPA_W_PH_MMR2 = 1627, 4408 DPAQX_SA_W_PH_MMR2 = 1628, 4409 DPAQX_S_W_PH_MMR2 = 1629, 4410 DPAX_W_PH_MMR2 = 1630, 4411 DPS_W_PH_MMR2 = 1631, 4412 DPSQX_S_W_PH_MMR2 = 1632, 4413 DPSQX_SA_W_PH_MMR2 = 1633, 4414 DPSX_W_PH_MMR2 = 1634, 4415 MUL_PH_MMR2 = 1635, 4416 MUL_S_PH_MMR2 = 1636, 4417 MULQ_RS_W_MMR2 = 1637, 4418 MULQ_S_PH_MMR2 = 1638, 4419 MULQ_S_W_MMR2 = 1639, 4420 MULSA_W_PH_MMR2 = 1640, 4421 PRECR_QB_PH_MMR2 = 1641, 4422 PRECR_SRA_PH_W_MMR2 = 1642, 4423 PRECR_SRA_R_PH_W_MMR2 = 1643, 4424 PREPEND_MMR2 = 1644, 4425 SHRA_QB_MMR2 = 1645, 4426 SHRA_R_QB_MMR2 = 1646, 4427 SHRAV_QB_MMR2 = 1647, 4428 SHRAV_R_QB_MMR2 = 1648, 4429 SHRL_PH_MMR2 = 1649, 4430 SHRLV_PH_MMR2 = 1650, 4431 SUBQH_PH_MMR2 = 1651, 4432 SUBQH_R_PH_MMR2 = 1652, 4433 SUBQH_W_MMR2 = 1653, 4434 SUBQH_R_W_MMR2 = 1654, 4435 SUBU_PH_MMR2 = 1655, 4436 SUBU_S_PH_MMR2 = 1656, 4437 SUBUH_QB_MMR2 = 1657, 4438 SUBUH_R_QB_MMR2 = 1658, 4439 BPOSGE32C_MMR3 = 1659, 4440 CMP_F_D = 1660, 4441 CMP_F_S = 1661, 4442 CMP_SAF_D = 1662, 4443 CMP_SAF_S = 1663, 4444 CMP_SEQ_D = 1664, 4445 CMP_SEQ_S = 1665, 4446 CMP_SLE_D = 1666, 4447 CMP_SLE_S = 1667, 4448 CMP_SLT_D = 1668, 4449 CMP_SLT_S = 1669, 4450 CMP_SUEQ_D = 1670, 4451 CMP_SUEQ_S = 1671, 4452 CMP_SULE_D = 1672, 4453 CMP_SULE_S = 1673, 4454 CMP_SULT_D = 1674, 4455 CMP_SULT_S = 1675, 4456 CMP_SUN_D = 1676, 4457 CMP_SUN_S = 1677, 4458 SCHED_LIST_END = 1678 4459 }; 4460} // end namespace Sched 4461} // end namespace Mips 4462} // end namespace llvm 4463#endif // GET_INSTRINFO_SCHED_ENUM 4464 4465#ifdef GET_INSTRINFO_MC_DESC 4466#undef GET_INSTRINFO_MC_DESC 4467namespace llvm { 4468 4469static const MCPhysReg ImplicitList1[] = { Mips::SP, 0 }; 4470static const MCPhysReg ImplicitList2[] = { Mips::AT, 0 }; 4471static const MCPhysReg ImplicitList3[] = { Mips::RA, 0 }; 4472static const MCPhysReg ImplicitList4[] = { Mips::DSPPos, 0 }; 4473static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1, 0 }; 4474static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0, 0 }; 4475static const MCPhysReg ImplicitList7[] = { Mips::T8, 0 }; 4476static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20, 0 }; 4477static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry, 0 }; 4478static const MCPhysReg ImplicitList10[] = { Mips::DSPCCond, 0 }; 4479static const MCPhysReg ImplicitList11[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, 0 }; 4480static const MCPhysReg ImplicitList12[] = { Mips::HI0_64, Mips::LO0_64, 0 }; 4481static const MCPhysReg ImplicitList13[] = { Mips::DSPOutFlag16_19, 0 }; 4482static const MCPhysReg ImplicitList14[] = { Mips::DSPEFI, 0 }; 4483static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI, 0 }; 4484static const MCPhysReg ImplicitList16[] = { Mips::DSPOutFlag23, 0 }; 4485static const MCPhysReg ImplicitList17[] = { Mips::FCC0, 0 }; 4486static const MCPhysReg ImplicitList18[] = { Mips::DSPPos, Mips::DSPSCount, 0 }; 4487static const MCPhysReg ImplicitList19[] = { Mips::AC0, 0 }; 4488static const MCPhysReg ImplicitList20[] = { Mips::AC0_64, 0 }; 4489static const MCPhysReg ImplicitList21[] = { Mips::HI0, 0 }; 4490static const MCPhysReg ImplicitList22[] = { Mips::HI0_64, 0 }; 4491static const MCPhysReg ImplicitList23[] = { Mips::LO0, 0 }; 4492static const MCPhysReg ImplicitList24[] = { Mips::LO0_64, 0 }; 4493static const MCPhysReg ImplicitList25[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, 0 }; 4494static const MCPhysReg ImplicitList26[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, 0 }; 4495static const MCPhysReg ImplicitList27[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 }; 4496static const MCPhysReg ImplicitList28[] = { Mips::P0, 0 }; 4497static const MCPhysReg ImplicitList29[] = { Mips::P1, 0 }; 4498static const MCPhysReg ImplicitList30[] = { Mips::P2, 0 }; 4499static const MCPhysReg ImplicitList31[] = { Mips::DSPOutFlag21, 0 }; 4500static const MCPhysReg ImplicitList32[] = { Mips::DSPOutFlag22, 0 }; 4501static const MCPhysReg ImplicitList33[] = { Mips::P0, Mips::P1, Mips::P2, 0 }; 4502static const MCPhysReg ImplicitList34[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 }; 4503 4504static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4505static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4506static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4507static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4508static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4509static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4510static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4511static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4512static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4513static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4514static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4515static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4516static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4517static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4518static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4519static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4520static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4521static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4522static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4523static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4524static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4525static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4526static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4527static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4528static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; 4529static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4530static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4531static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4532static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4533static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4534static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; 4535static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; 4536static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; 4537static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4538static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4539static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; 4540static const MCOperandInfo OperandInfo38[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4541static const MCOperandInfo OperandInfo39[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4542static const MCOperandInfo OperandInfo40[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4543static const MCOperandInfo OperandInfo41[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4544static const MCOperandInfo OperandInfo42[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4545static const MCOperandInfo OperandInfo43[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4546static const MCOperandInfo OperandInfo44[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4547static const MCOperandInfo OperandInfo45[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4548static const MCOperandInfo OperandInfo46[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4549static const MCOperandInfo OperandInfo47[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4550static const MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4551static const MCOperandInfo OperandInfo49[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4552static const MCOperandInfo OperandInfo50[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4553static const MCOperandInfo OperandInfo51[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4554static const MCOperandInfo OperandInfo52[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4555static const MCOperandInfo OperandInfo53[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4556static const MCOperandInfo OperandInfo54[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4557static const MCOperandInfo OperandInfo55[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4558static const MCOperandInfo OperandInfo56[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4559static const MCOperandInfo OperandInfo57[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4560static const MCOperandInfo OperandInfo58[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4561static const MCOperandInfo OperandInfo59[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4562static const MCOperandInfo OperandInfo60[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4563static const MCOperandInfo OperandInfo61[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4564static const MCOperandInfo OperandInfo62[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4565static const MCOperandInfo OperandInfo63[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4566static const MCOperandInfo OperandInfo64[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4567static const MCOperandInfo OperandInfo65[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4568static const MCOperandInfo OperandInfo66[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4569static const MCOperandInfo OperandInfo67[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4570static const MCOperandInfo OperandInfo68[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4571static const MCOperandInfo OperandInfo69[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4572static const MCOperandInfo OperandInfo70[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4573static const MCOperandInfo OperandInfo71[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4574static const MCOperandInfo OperandInfo72[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4575static const MCOperandInfo OperandInfo73[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4576static const MCOperandInfo OperandInfo74[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4577static const MCOperandInfo OperandInfo75[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4578static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4579static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4580static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4581static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4582static const MCOperandInfo OperandInfo80[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4583static const MCOperandInfo OperandInfo81[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4584static const MCOperandInfo OperandInfo82[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4585static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4586static const MCOperandInfo OperandInfo84[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4587static const MCOperandInfo OperandInfo85[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4588static const MCOperandInfo OperandInfo86[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4589static const MCOperandInfo OperandInfo87[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4590static const MCOperandInfo OperandInfo88[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4591static const MCOperandInfo OperandInfo89[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4592static const MCOperandInfo OperandInfo90[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4593static const MCOperandInfo OperandInfo91[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4594static const MCOperandInfo OperandInfo92[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4595static const MCOperandInfo OperandInfo93[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4596static const MCOperandInfo OperandInfo94[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4597static const MCOperandInfo OperandInfo95[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4598static const MCOperandInfo OperandInfo96[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4599static const MCOperandInfo OperandInfo97[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4600static const MCOperandInfo OperandInfo98[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4601static const MCOperandInfo OperandInfo99[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4602static const MCOperandInfo OperandInfo100[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4603static const MCOperandInfo OperandInfo101[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4604static const MCOperandInfo OperandInfo102[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4605static const MCOperandInfo OperandInfo103[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4606static const MCOperandInfo OperandInfo104[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4607static const MCOperandInfo OperandInfo105[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4608static const MCOperandInfo OperandInfo106[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4609static const MCOperandInfo OperandInfo107[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4610static const MCOperandInfo OperandInfo108[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4611static const MCOperandInfo OperandInfo109[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4612static const MCOperandInfo OperandInfo110[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4613static const MCOperandInfo OperandInfo111[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4614static const MCOperandInfo OperandInfo112[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4615static const MCOperandInfo OperandInfo113[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4616static const MCOperandInfo OperandInfo114[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4617static const MCOperandInfo OperandInfo115[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4618static const MCOperandInfo OperandInfo116[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4619static const MCOperandInfo OperandInfo117[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4620static const MCOperandInfo OperandInfo118[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4621static const MCOperandInfo OperandInfo119[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4622static const MCOperandInfo OperandInfo120[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4623static const MCOperandInfo OperandInfo121[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4624static const MCOperandInfo OperandInfo122[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4625static const MCOperandInfo OperandInfo123[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4626static const MCOperandInfo OperandInfo124[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4627static const MCOperandInfo OperandInfo125[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4628static const MCOperandInfo OperandInfo126[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4629static const MCOperandInfo OperandInfo127[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4630static const MCOperandInfo OperandInfo128[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4631static const MCOperandInfo OperandInfo129[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4632static const MCOperandInfo OperandInfo130[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4633static const MCOperandInfo OperandInfo131[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4634static const MCOperandInfo OperandInfo132[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4635static const MCOperandInfo OperandInfo133[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4636static const MCOperandInfo OperandInfo134[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4637static const MCOperandInfo OperandInfo135[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4638static const MCOperandInfo OperandInfo136[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4639static const MCOperandInfo OperandInfo137[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4640static const MCOperandInfo OperandInfo138[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4641static const MCOperandInfo OperandInfo139[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4642static const MCOperandInfo OperandInfo140[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4643static const MCOperandInfo OperandInfo141[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4644static const MCOperandInfo OperandInfo142[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4645static const MCOperandInfo OperandInfo143[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4646static const MCOperandInfo OperandInfo144[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4647static const MCOperandInfo OperandInfo145[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4648static const MCOperandInfo OperandInfo146[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4649static const MCOperandInfo OperandInfo147[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4650static const MCOperandInfo OperandInfo148[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4651static const MCOperandInfo OperandInfo149[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4652static const MCOperandInfo OperandInfo150[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4653static const MCOperandInfo OperandInfo151[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4654static const MCOperandInfo OperandInfo152[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4655static const MCOperandInfo OperandInfo153[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4656static const MCOperandInfo OperandInfo154[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4657static const MCOperandInfo OperandInfo155[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4658static const MCOperandInfo OperandInfo156[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4659static const MCOperandInfo OperandInfo157[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4660static const MCOperandInfo OperandInfo158[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4661static const MCOperandInfo OperandInfo159[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4662static const MCOperandInfo OperandInfo160[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4663static const MCOperandInfo OperandInfo161[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4664static const MCOperandInfo OperandInfo162[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4665static const MCOperandInfo OperandInfo163[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4666static const MCOperandInfo OperandInfo164[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4667static const MCOperandInfo OperandInfo165[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4668static const MCOperandInfo OperandInfo166[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4669static const MCOperandInfo OperandInfo167[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4670static const MCOperandInfo OperandInfo168[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4671static const MCOperandInfo OperandInfo169[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4672static const MCOperandInfo OperandInfo170[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4673static const MCOperandInfo OperandInfo171[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4674static const MCOperandInfo OperandInfo172[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4675static const MCOperandInfo OperandInfo173[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4676static const MCOperandInfo OperandInfo174[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4677static const MCOperandInfo OperandInfo175[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4678static const MCOperandInfo OperandInfo176[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4679static const MCOperandInfo OperandInfo177[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4680static const MCOperandInfo OperandInfo178[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4681static const MCOperandInfo OperandInfo179[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4682static const MCOperandInfo OperandInfo180[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4683static const MCOperandInfo OperandInfo181[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4684static const MCOperandInfo OperandInfo182[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4685static const MCOperandInfo OperandInfo183[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4686static const MCOperandInfo OperandInfo184[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4687static const MCOperandInfo OperandInfo185[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4688static const MCOperandInfo OperandInfo186[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4689static const MCOperandInfo OperandInfo187[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4690static const MCOperandInfo OperandInfo188[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4691static const MCOperandInfo OperandInfo189[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4692static const MCOperandInfo OperandInfo190[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4693static const MCOperandInfo OperandInfo191[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; 4694static const MCOperandInfo OperandInfo192[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4695static const MCOperandInfo OperandInfo193[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4696static const MCOperandInfo OperandInfo194[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4697static const MCOperandInfo OperandInfo195[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4698static const MCOperandInfo OperandInfo196[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4699static const MCOperandInfo OperandInfo197[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4700static const MCOperandInfo OperandInfo198[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4701static const MCOperandInfo OperandInfo199[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4702static const MCOperandInfo OperandInfo200[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4703static const MCOperandInfo OperandInfo201[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4704static const MCOperandInfo OperandInfo202[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4705static const MCOperandInfo OperandInfo203[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4706static const MCOperandInfo OperandInfo204[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4707static const MCOperandInfo OperandInfo205[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4708static const MCOperandInfo OperandInfo206[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4709static const MCOperandInfo OperandInfo207[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4710static const MCOperandInfo OperandInfo208[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4711static const MCOperandInfo OperandInfo209[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4712static const MCOperandInfo OperandInfo210[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4713static const MCOperandInfo OperandInfo211[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4714static const MCOperandInfo OperandInfo212[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4715static const MCOperandInfo OperandInfo213[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4716static const MCOperandInfo OperandInfo214[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4717static const MCOperandInfo OperandInfo215[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4718static const MCOperandInfo OperandInfo216[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4719static const MCOperandInfo OperandInfo217[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4720static const MCOperandInfo OperandInfo218[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4721static const MCOperandInfo OperandInfo219[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4722static const MCOperandInfo OperandInfo220[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4723static const MCOperandInfo OperandInfo221[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4724static const MCOperandInfo OperandInfo222[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4725static const MCOperandInfo OperandInfo223[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4726static const MCOperandInfo OperandInfo224[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4727static const MCOperandInfo OperandInfo225[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4728static const MCOperandInfo OperandInfo226[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4729static const MCOperandInfo OperandInfo227[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4730static const MCOperandInfo OperandInfo228[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4731static const MCOperandInfo OperandInfo229[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4732static const MCOperandInfo OperandInfo230[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4733static const MCOperandInfo OperandInfo231[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4734static const MCOperandInfo OperandInfo232[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4735static const MCOperandInfo OperandInfo233[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4736static const MCOperandInfo OperandInfo234[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4737static const MCOperandInfo OperandInfo235[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4738static const MCOperandInfo OperandInfo236[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4739static const MCOperandInfo OperandInfo237[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4740static const MCOperandInfo OperandInfo238[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4741static const MCOperandInfo OperandInfo239[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4742static const MCOperandInfo OperandInfo240[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4743static const MCOperandInfo OperandInfo241[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4744static const MCOperandInfo OperandInfo242[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4745static const MCOperandInfo OperandInfo243[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4746static const MCOperandInfo OperandInfo244[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4747static const MCOperandInfo OperandInfo245[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4748static const MCOperandInfo OperandInfo246[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4749static const MCOperandInfo OperandInfo247[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4750static const MCOperandInfo OperandInfo248[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4751static const MCOperandInfo OperandInfo249[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4752static const MCOperandInfo OperandInfo250[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4753static const MCOperandInfo OperandInfo251[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4754static const MCOperandInfo OperandInfo252[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4755static const MCOperandInfo OperandInfo253[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4756static const MCOperandInfo OperandInfo254[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4757static const MCOperandInfo OperandInfo255[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4758static const MCOperandInfo OperandInfo256[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4759static const MCOperandInfo OperandInfo257[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4760static const MCOperandInfo OperandInfo258[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4761static const MCOperandInfo OperandInfo259[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4762static const MCOperandInfo OperandInfo260[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4763static const MCOperandInfo OperandInfo261[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4764static const MCOperandInfo OperandInfo262[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4765static const MCOperandInfo OperandInfo263[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4766static const MCOperandInfo OperandInfo264[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4767static const MCOperandInfo OperandInfo265[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4768static const MCOperandInfo OperandInfo266[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4769static const MCOperandInfo OperandInfo267[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4770static const MCOperandInfo OperandInfo268[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4771static const MCOperandInfo OperandInfo269[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4772static const MCOperandInfo OperandInfo270[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4773static const MCOperandInfo OperandInfo271[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4774static const MCOperandInfo OperandInfo272[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4775static const MCOperandInfo OperandInfo273[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4776static const MCOperandInfo OperandInfo274[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4777static const MCOperandInfo OperandInfo275[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4778static const MCOperandInfo OperandInfo276[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4779static const MCOperandInfo OperandInfo277[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4780static const MCOperandInfo OperandInfo278[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4781static const MCOperandInfo OperandInfo279[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4782static const MCOperandInfo OperandInfo280[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4783static const MCOperandInfo OperandInfo281[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; 4784static const MCOperandInfo OperandInfo282[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; 4785static const MCOperandInfo OperandInfo283[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4786static const MCOperandInfo OperandInfo284[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4787static const MCOperandInfo OperandInfo285[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4788static const MCOperandInfo OperandInfo286[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4789static const MCOperandInfo OperandInfo287[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4790static const MCOperandInfo OperandInfo288[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4791static const MCOperandInfo OperandInfo289[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4792static const MCOperandInfo OperandInfo290[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; 4793static const MCOperandInfo OperandInfo291[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4794static const MCOperandInfo OperandInfo292[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; 4795static const MCOperandInfo OperandInfo293[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4796static const MCOperandInfo OperandInfo294[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4797static const MCOperandInfo OperandInfo295[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4798static const MCOperandInfo OperandInfo296[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4799static const MCOperandInfo OperandInfo297[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4800static const MCOperandInfo OperandInfo298[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4801static const MCOperandInfo OperandInfo299[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4802static const MCOperandInfo OperandInfo300[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4803static const MCOperandInfo OperandInfo301[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4804static const MCOperandInfo OperandInfo302[] = { { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4805static const MCOperandInfo OperandInfo303[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4806static const MCOperandInfo OperandInfo304[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4807static const MCOperandInfo OperandInfo305[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4808static const MCOperandInfo OperandInfo306[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4809static const MCOperandInfo OperandInfo307[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4810static const MCOperandInfo OperandInfo308[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4811static const MCOperandInfo OperandInfo309[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4812static const MCOperandInfo OperandInfo310[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4813static const MCOperandInfo OperandInfo311[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4814static const MCOperandInfo OperandInfo312[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4815static const MCOperandInfo OperandInfo313[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4816static const MCOperandInfo OperandInfo314[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4817static const MCOperandInfo OperandInfo315[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4818static const MCOperandInfo OperandInfo316[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4819static const MCOperandInfo OperandInfo317[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4820static const MCOperandInfo OperandInfo318[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4821static const MCOperandInfo OperandInfo319[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4822static const MCOperandInfo OperandInfo320[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4823static const MCOperandInfo OperandInfo321[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4824static const MCOperandInfo OperandInfo322[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4825static const MCOperandInfo OperandInfo323[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4826static const MCOperandInfo OperandInfo324[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4827static const MCOperandInfo OperandInfo325[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4828static const MCOperandInfo OperandInfo326[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4829static const MCOperandInfo OperandInfo327[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4830static const MCOperandInfo OperandInfo328[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4831static const MCOperandInfo OperandInfo329[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4832static const MCOperandInfo OperandInfo330[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4833static const MCOperandInfo OperandInfo331[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4834static const MCOperandInfo OperandInfo332[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4835static const MCOperandInfo OperandInfo333[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4836static const MCOperandInfo OperandInfo334[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4837static const MCOperandInfo OperandInfo335[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4838static const MCOperandInfo OperandInfo336[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4839static const MCOperandInfo OperandInfo337[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4840static const MCOperandInfo OperandInfo338[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; 4841static const MCOperandInfo OperandInfo339[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4842static const MCOperandInfo OperandInfo340[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; 4843static const MCOperandInfo OperandInfo341[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4844static const MCOperandInfo OperandInfo342[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4845static const MCOperandInfo OperandInfo343[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4846static const MCOperandInfo OperandInfo344[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4847static const MCOperandInfo OperandInfo345[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4848static const MCOperandInfo OperandInfo346[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4849static const MCOperandInfo OperandInfo347[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4850static const MCOperandInfo OperandInfo348[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4851static const MCOperandInfo OperandInfo349[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4852static const MCOperandInfo OperandInfo350[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; 4853static const MCOperandInfo OperandInfo351[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4854static const MCOperandInfo OperandInfo352[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4855static const MCOperandInfo OperandInfo353[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4856static const MCOperandInfo OperandInfo354[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; 4857static const MCOperandInfo OperandInfo355[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; 4858static const MCOperandInfo OperandInfo356[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; 4859 4860extern const MCInstrDesc MipsInsts[] = { 4861 { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI 4862 { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM 4863 { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR 4864 { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION 4865 { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL 4866 { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL 4867 { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL 4868 { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL 4869 { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG 4870 { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG 4871 { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF 4872 { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG 4873 { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS 4874 { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE 4875 { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL 4876 { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE 4877 { 16, 2, 1, 0, 509, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY 4878 { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE 4879 { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START 4880 { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END 4881 { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP 4882 { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL 4883 { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT 4884 { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD 4885 { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT 4886 { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE 4887 { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP 4888 { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP 4889 { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER 4890 { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET 4891 { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT 4892 { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL 4893 { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL 4894 { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL 4895 { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL 4896 { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #35 = G_ADD 4897 { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #36 = G_SUB 4898 { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #37 = G_MUL 4899 { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #38 = G_SDIV 4900 { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #39 = G_UDIV 4901 { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #40 = G_SREM 4902 { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #41 = G_UREM 4903 { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #42 = G_AND 4904 { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #43 = G_OR 4905 { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #44 = G_XOR 4906 { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF 4907 { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #46 = G_PHI 4908 { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX 4909 { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE 4910 { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #49 = G_EXTRACT 4911 { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES 4912 { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #51 = G_INSERT 4913 { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES 4914 { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR 4915 { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC 4916 { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS 4917 { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #56 = G_PTRTOINT 4918 { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #57 = G_INTTOPTR 4919 { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #58 = G_BITCAST 4920 { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC 4921 { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND 4922 { 61, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #61 = G_READCYCLECOUNTER 4923 { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #62 = G_LOAD 4924 { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #63 = G_SEXTLOAD 4925 { 64, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #64 = G_ZEXTLOAD 4926 { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #65 = G_INDEXED_LOAD 4927 { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #66 = G_INDEXED_SEXTLOAD 4928 { 67, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #67 = G_INDEXED_ZEXTLOAD 4929 { 68, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #68 = G_STORE 4930 { 69, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_INDEXED_STORE 4931 { 70, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG_WITH_SUCCESS 4932 { 71, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMIC_CMPXCHG 4933 { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_XCHG 4934 { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_ADD 4935 { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_SUB 4936 { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_AND 4937 { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_NAND 4938 { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_OR 4939 { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_XOR 4940 { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MAX 4941 { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_MIN 4942 { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMAX 4943 { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_UMIN 4944 { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FADD 4945 { 84, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #84 = G_ATOMICRMW_FSUB 4946 { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #85 = G_FENCE 4947 { 86, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #86 = G_BRCOND 4948 { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #87 = G_BRINDIRECT 4949 { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC 4950 { 89, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #89 = G_INTRINSIC_W_SIDE_EFFECTS 4951 { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #90 = G_ANYEXT 4952 { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #91 = G_TRUNC 4953 { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #92 = G_CONSTANT 4954 { 93, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #93 = G_FCONSTANT 4955 { 94, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #94 = G_VASTART 4956 { 95, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_VAARG 4957 { 96, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #96 = G_SEXT 4958 { 97, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #97 = G_SEXT_INREG 4959 { 98, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #98 = G_ZEXT 4960 { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #99 = G_SHL 4961 { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #100 = G_LSHR 4962 { 101, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ASHR 4963 { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #102 = G_ICMP 4964 { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #103 = G_FCMP 4965 { 104, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #104 = G_SELECT 4966 { 105, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #105 = G_UADDO 4967 { 106, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #106 = G_UADDE 4968 { 107, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #107 = G_USUBO 4969 { 108, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #108 = G_USUBE 4970 { 109, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #109 = G_SADDO 4971 { 110, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #110 = G_SADDE 4972 { 111, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #111 = G_SSUBO 4973 { 112, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #112 = G_SSUBE 4974 { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #113 = G_UMULO 4975 { 114, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #114 = G_SMULO 4976 { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #115 = G_UMULH 4977 { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #116 = G_SMULH 4978 { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #117 = G_FADD 4979 { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #118 = G_FSUB 4980 { 119, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #119 = G_FMUL 4981 { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #120 = G_FMA 4982 { 121, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #121 = G_FMAD 4983 { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #122 = G_FDIV 4984 { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #123 = G_FREM 4985 { 124, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #124 = G_FPOW 4986 { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #125 = G_FEXP 4987 { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #126 = G_FEXP2 4988 { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #127 = G_FLOG 4989 { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #128 = G_FLOG2 4990 { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #129 = G_FLOG10 4991 { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #130 = G_FNEG 4992 { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #131 = G_FPEXT 4993 { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #132 = G_FPTRUNC 4994 { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #133 = G_FPTOSI 4995 { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #134 = G_FPTOUI 4996 { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #135 = G_SITOFP 4997 { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #136 = G_UITOFP 4998 { 137, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #137 = G_FABS 4999 { 138, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #138 = G_FCOPYSIGN 5000 { 139, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #139 = G_FCANONICALIZE 5001 { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #140 = G_FMINNUM 5002 { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #141 = G_FMAXNUM 5003 { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #142 = G_FMINNUM_IEEE 5004 { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #143 = G_FMAXNUM_IEEE 5005 { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #144 = G_FMINIMUM 5006 { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #145 = G_FMAXIMUM 5007 { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #146 = G_PTR_ADD 5008 { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #147 = G_PTR_MASK 5009 { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #148 = G_SMIN 5010 { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #149 = G_SMAX 5011 { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #150 = G_UMIN 5012 { 151, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #151 = G_UMAX 5013 { 152, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #152 = G_BR 5014 { 153, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_BRJT 5015 { 154, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_INSERT_VECTOR_ELT 5016 { 155, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_EXTRACT_VECTOR_ELT 5017 { 156, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #156 = G_SHUFFLE_VECTOR 5018 { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #157 = G_CTTZ 5019 { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #158 = G_CTTZ_ZERO_UNDEF 5020 { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #159 = G_CTLZ 5021 { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #160 = G_CTLZ_ZERO_UNDEF 5022 { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #161 = G_CTPOP 5023 { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #162 = G_BSWAP 5024 { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #163 = G_BITREVERSE 5025 { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #164 = G_FCEIL 5026 { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #165 = G_FCOS 5027 { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #166 = G_FSIN 5028 { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #167 = G_FSQRT 5029 { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #168 = G_FFLOOR 5030 { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #169 = G_FRINT 5031 { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #170 = G_FNEARBYINT 5032 { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #171 = G_ADDRSPACE_CAST 5033 { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #172 = G_BLOCK_ADDR 5034 { 173, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #173 = G_JUMP_TABLE 5035 { 174, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = G_DYN_STACKALLOC 5036 { 175, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #175 = G_READ_REGISTER 5037 { 176, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #176 = G_WRITE_REGISTER 5038 { 177, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #177 = ABSMacro 5039 { 178, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #178 = ADJCALLSTACKDOWN 5040 { 179, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #179 = ADJCALLSTACKUP 5041 { 180, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #180 = AND_V_D_PSEUDO 5042 { 181, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #181 = AND_V_H_PSEUDO 5043 { 182, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #182 = AND_V_W_PSEUDO 5044 { 183, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #183 = ATOMIC_CMP_SWAP_I16 5045 { 184, 7, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #184 = ATOMIC_CMP_SWAP_I16_POSTRA 5046 { 185, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #185 = ATOMIC_CMP_SWAP_I32 5047 { 186, 4, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #186 = ATOMIC_CMP_SWAP_I32_POSTRA 5048 { 187, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #187 = ATOMIC_CMP_SWAP_I64 5049 { 188, 4, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #188 = ATOMIC_CMP_SWAP_I64_POSTRA 5050 { 189, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #189 = ATOMIC_CMP_SWAP_I8 5051 { 190, 7, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #190 = ATOMIC_CMP_SWAP_I8_POSTRA 5052 { 191, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #191 = ATOMIC_LOAD_ADD_I16 5053 { 192, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #192 = ATOMIC_LOAD_ADD_I16_POSTRA 5054 { 193, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #193 = ATOMIC_LOAD_ADD_I32 5055 { 194, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #194 = ATOMIC_LOAD_ADD_I32_POSTRA 5056 { 195, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #195 = ATOMIC_LOAD_ADD_I64 5057 { 196, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #196 = ATOMIC_LOAD_ADD_I64_POSTRA 5058 { 197, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #197 = ATOMIC_LOAD_ADD_I8 5059 { 198, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #198 = ATOMIC_LOAD_ADD_I8_POSTRA 5060 { 199, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #199 = ATOMIC_LOAD_AND_I16 5061 { 200, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #200 = ATOMIC_LOAD_AND_I16_POSTRA 5062 { 201, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #201 = ATOMIC_LOAD_AND_I32 5063 { 202, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #202 = ATOMIC_LOAD_AND_I32_POSTRA 5064 { 203, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #203 = ATOMIC_LOAD_AND_I64 5065 { 204, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #204 = ATOMIC_LOAD_AND_I64_POSTRA 5066 { 205, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #205 = ATOMIC_LOAD_AND_I8 5067 { 206, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #206 = ATOMIC_LOAD_AND_I8_POSTRA 5068 { 207, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #207 = ATOMIC_LOAD_MAX_I16 5069 { 208, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #208 = ATOMIC_LOAD_MAX_I16_POSTRA 5070 { 209, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #209 = ATOMIC_LOAD_MAX_I32 5071 { 210, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #210 = ATOMIC_LOAD_MAX_I32_POSTRA 5072 { 211, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #211 = ATOMIC_LOAD_MAX_I64 5073 { 212, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #212 = ATOMIC_LOAD_MAX_I64_POSTRA 5074 { 213, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #213 = ATOMIC_LOAD_MAX_I8 5075 { 214, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #214 = ATOMIC_LOAD_MAX_I8_POSTRA 5076 { 215, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #215 = ATOMIC_LOAD_MIN_I16 5077 { 216, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #216 = ATOMIC_LOAD_MIN_I16_POSTRA 5078 { 217, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #217 = ATOMIC_LOAD_MIN_I32 5079 { 218, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #218 = ATOMIC_LOAD_MIN_I32_POSTRA 5080 { 219, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #219 = ATOMIC_LOAD_MIN_I64 5081 { 220, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #220 = ATOMIC_LOAD_MIN_I64_POSTRA 5082 { 221, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #221 = ATOMIC_LOAD_MIN_I8 5083 { 222, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #222 = ATOMIC_LOAD_MIN_I8_POSTRA 5084 { 223, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #223 = ATOMIC_LOAD_NAND_I16 5085 { 224, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #224 = ATOMIC_LOAD_NAND_I16_POSTRA 5086 { 225, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #225 = ATOMIC_LOAD_NAND_I32 5087 { 226, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #226 = ATOMIC_LOAD_NAND_I32_POSTRA 5088 { 227, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #227 = ATOMIC_LOAD_NAND_I64 5089 { 228, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #228 = ATOMIC_LOAD_NAND_I64_POSTRA 5090 { 229, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #229 = ATOMIC_LOAD_NAND_I8 5091 { 230, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #230 = ATOMIC_LOAD_NAND_I8_POSTRA 5092 { 231, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #231 = ATOMIC_LOAD_OR_I16 5093 { 232, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #232 = ATOMIC_LOAD_OR_I16_POSTRA 5094 { 233, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #233 = ATOMIC_LOAD_OR_I32 5095 { 234, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #234 = ATOMIC_LOAD_OR_I32_POSTRA 5096 { 235, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #235 = ATOMIC_LOAD_OR_I64 5097 { 236, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #236 = ATOMIC_LOAD_OR_I64_POSTRA 5098 { 237, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #237 = ATOMIC_LOAD_OR_I8 5099 { 238, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #238 = ATOMIC_LOAD_OR_I8_POSTRA 5100 { 239, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #239 = ATOMIC_LOAD_SUB_I16 5101 { 240, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #240 = ATOMIC_LOAD_SUB_I16_POSTRA 5102 { 241, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #241 = ATOMIC_LOAD_SUB_I32 5103 { 242, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #242 = ATOMIC_LOAD_SUB_I32_POSTRA 5104 { 243, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #243 = ATOMIC_LOAD_SUB_I64 5105 { 244, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #244 = ATOMIC_LOAD_SUB_I64_POSTRA 5106 { 245, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #245 = ATOMIC_LOAD_SUB_I8 5107 { 246, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #246 = ATOMIC_LOAD_SUB_I8_POSTRA 5108 { 247, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #247 = ATOMIC_LOAD_UMAX_I16 5109 { 248, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #248 = ATOMIC_LOAD_UMAX_I16_POSTRA 5110 { 249, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #249 = ATOMIC_LOAD_UMAX_I32 5111 { 250, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #250 = ATOMIC_LOAD_UMAX_I32_POSTRA 5112 { 251, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #251 = ATOMIC_LOAD_UMAX_I64 5113 { 252, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #252 = ATOMIC_LOAD_UMAX_I64_POSTRA 5114 { 253, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #253 = ATOMIC_LOAD_UMAX_I8 5115 { 254, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #254 = ATOMIC_LOAD_UMAX_I8_POSTRA 5116 { 255, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #255 = ATOMIC_LOAD_UMIN_I16 5117 { 256, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #256 = ATOMIC_LOAD_UMIN_I16_POSTRA 5118 { 257, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #257 = ATOMIC_LOAD_UMIN_I32 5119 { 258, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #258 = ATOMIC_LOAD_UMIN_I32_POSTRA 5120 { 259, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #259 = ATOMIC_LOAD_UMIN_I64 5121 { 260, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #260 = ATOMIC_LOAD_UMIN_I64_POSTRA 5122 { 261, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #261 = ATOMIC_LOAD_UMIN_I8 5123 { 262, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #262 = ATOMIC_LOAD_UMIN_I8_POSTRA 5124 { 263, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #263 = ATOMIC_LOAD_XOR_I16 5125 { 264, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #264 = ATOMIC_LOAD_XOR_I16_POSTRA 5126 { 265, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #265 = ATOMIC_LOAD_XOR_I32 5127 { 266, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #266 = ATOMIC_LOAD_XOR_I32_POSTRA 5128 { 267, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #267 = ATOMIC_LOAD_XOR_I64 5129 { 268, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #268 = ATOMIC_LOAD_XOR_I64_POSTRA 5130 { 269, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #269 = ATOMIC_LOAD_XOR_I8 5131 { 270, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #270 = ATOMIC_LOAD_XOR_I8_POSTRA 5132 { 271, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #271 = ATOMIC_SWAP_I16 5133 { 272, 6, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #272 = ATOMIC_SWAP_I16_POSTRA 5134 { 273, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #273 = ATOMIC_SWAP_I32 5135 { 274, 3, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #274 = ATOMIC_SWAP_I32_POSTRA 5136 { 275, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #275 = ATOMIC_SWAP_I64 5137 { 276, 3, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #276 = ATOMIC_SWAP_I64_POSTRA 5138 { 277, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #277 = ATOMIC_SWAP_I8 5139 { 278, 6, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #278 = ATOMIC_SWAP_I8_POSTRA 5140 { 279, 1, 0, 4, 369, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #279 = B 5141 { 280, 1, 0, 4, 911, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #280 = BAL_BR 5142 { 281, 1, 0, 4, 938, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #281 = BAL_BR_MM 5143 { 282, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #282 = BEQLImmMacro 5144 { 283, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #283 = BGE 5145 { 284, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #284 = BGEImmMacro 5146 { 285, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #285 = BGEL 5147 { 286, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #286 = BGELImmMacro 5148 { 287, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #287 = BGEU 5149 { 288, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #288 = BGEUImmMacro 5150 { 289, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #289 = BGEUL 5151 { 290, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #290 = BGEULImmMacro 5152 { 291, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #291 = BGT 5153 { 292, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #292 = BGTImmMacro 5154 { 293, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #293 = BGTL 5155 { 294, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #294 = BGTLImmMacro 5156 { 295, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #295 = BGTU 5157 { 296, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #296 = BGTUImmMacro 5158 { 297, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #297 = BGTUL 5159 { 298, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #298 = BGTULImmMacro 5160 { 299, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #299 = BLE 5161 { 300, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #300 = BLEImmMacro 5162 { 301, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #301 = BLEL 5163 { 302, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #302 = BLELImmMacro 5164 { 303, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #303 = BLEU 5165 { 304, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #304 = BLEUImmMacro 5166 { 305, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #305 = BLEUL 5167 { 306, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #306 = BLEULImmMacro 5168 { 307, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #307 = BLT 5169 { 308, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #308 = BLTImmMacro 5170 { 309, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #309 = BLTL 5171 { 310, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #310 = BLTLImmMacro 5172 { 311, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #311 = BLTU 5173 { 312, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #312 = BLTUImmMacro 5174 { 313, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #313 = BLTUL 5175 { 314, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #314 = BLTULImmMacro 5176 { 315, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #315 = BNELImmMacro 5177 { 316, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #316 = BPOSGE32_PSEUDO 5178 { 317, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #317 = BSEL_D_PSEUDO 5179 { 318, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #318 = BSEL_FD_PSEUDO 5180 { 319, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #319 = BSEL_FW_PSEUDO 5181 { 320, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #320 = BSEL_H_PSEUDO 5182 { 321, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #321 = BSEL_W_PSEUDO 5183 { 322, 1, 0, 4, 937, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #322 = B_MM 5184 { 323, 1, 0, 4, 989, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #323 = B_MMR6_Pseudo 5185 { 324, 1, 0, 4, 948, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #324 = B_MM_Pseudo 5186 { 325, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #325 = BeqImm 5187 { 326, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #326 = BneImm 5188 { 327, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #327 = BteqzT8CmpX16 5189 { 328, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #328 = BteqzT8CmpiX16 5190 { 329, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #329 = BteqzT8SltX16 5191 { 330, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #330 = BteqzT8SltiX16 5192 { 331, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #331 = BteqzT8SltiuX16 5193 { 332, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #332 = BteqzT8SltuX16 5194 { 333, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #333 = BtnezT8CmpX16 5195 { 334, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #334 = BtnezT8CmpiX16 5196 { 335, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #335 = BtnezT8SltX16 5197 { 336, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #336 = BtnezT8SltiX16 5198 { 337, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #337 = BtnezT8SltiuX16 5199 { 338, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #338 = BtnezT8SltuX16 5200 { 339, 3, 1, 4, 678, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #339 = BuildPairF64 5201 { 340, 3, 1, 4, 678, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #340 = BuildPairF64_64 5202 { 341, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #341 = CFTC1 5203 { 342, 3, 0, 2, 729, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #342 = CONSTPOOL_ENTRY 5204 { 343, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #343 = COPY_FD_PSEUDO 5205 { 344, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #344 = COPY_FW_PSEUDO 5206 { 345, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #345 = CTTC1 5207 { 346, 1, 0, 2, 729, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #346 = Constant32 5208 { 347, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #347 = DMULImmMacro 5209 { 348, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #348 = DMULMacro 5210 { 349, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #349 = DMULOMacro 5211 { 350, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #350 = DMULOUMacro 5212 { 351, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #351 = DROL 5213 { 352, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #352 = DROLImm 5214 { 353, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #353 = DROR 5215 { 354, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #354 = DRORImm 5216 { 355, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #355 = DSDivIMacro 5217 { 356, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #356 = DSDivMacro 5218 { 357, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #357 = DSRemIMacro 5219 { 358, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #358 = DSRemMacro 5220 { 359, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #359 = DUDivIMacro 5221 { 360, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #360 = DUDivMacro 5222 { 361, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #361 = DURemIMacro 5223 { 362, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #362 = DURemMacro 5224 { 363, 0, 0, 4, 916, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #363 = ERet 5225 { 364, 3, 1, 4, 687, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #364 = ExtractElementF64 5226 { 365, 3, 1, 4, 687, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #365 = ExtractElementF64_64 5227 { 366, 2, 1, 4, 583, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #366 = FABS_D 5228 { 367, 2, 1, 4, 583, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #367 = FABS_W 5229 { 368, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #368 = FEXP2_D_1_PSEUDO 5230 { 369, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #369 = FEXP2_W_1_PSEUDO 5231 { 370, 2, 1, 4, 546, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #370 = FILL_FD_PSEUDO 5232 { 371, 2, 1, 4, 546, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #371 = FILL_FW_PSEUDO 5233 { 372, 4, 2, 2, 729, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #372 = GotPrologue16 5234 { 373, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #373 = INSERT_B_VIDX64_PSEUDO 5235 { 374, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #374 = INSERT_B_VIDX_PSEUDO 5236 { 375, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #375 = INSERT_D_VIDX64_PSEUDO 5237 { 376, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #376 = INSERT_D_VIDX_PSEUDO 5238 { 377, 4, 1, 4, 547, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #377 = INSERT_FD_PSEUDO 5239 { 378, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #378 = INSERT_FD_VIDX64_PSEUDO 5240 { 379, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #379 = INSERT_FD_VIDX_PSEUDO 5241 { 380, 4, 1, 4, 547, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #380 = INSERT_FW_PSEUDO 5242 { 381, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #381 = INSERT_FW_VIDX64_PSEUDO 5243 { 382, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #382 = INSERT_FW_VIDX_PSEUDO 5244 { 383, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #383 = INSERT_H_VIDX64_PSEUDO 5245 { 384, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #384 = INSERT_H_VIDX_PSEUDO 5246 { 385, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #385 = INSERT_W_VIDX64_PSEUDO 5247 { 386, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #386 = INSERT_W_VIDX_PSEUDO 5248 { 387, 1, 0, 4, 1004, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo88, -1 ,nullptr }, // Inst #387 = JALR64Pseudo 5249 { 388, 1, 0, 4, 1004, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo88, -1 ,nullptr }, // Inst #388 = JALRHB64Pseudo 5250 { 389, 1, 0, 4, 402, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #389 = JALRHBPseudo 5251 { 390, 1, 0, 4, 402, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #390 = JALRPseudo 5252 { 391, 1, 0, 4, 982, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #391 = JAL_MMR6 5253 { 392, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #392 = JalOneReg 5254 { 393, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #393 = JalTwoReg 5255 { 394, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #394 = LDMacro 5256 { 395, 3, 1, 4, 708, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #395 = LD_F16 5257 { 396, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #396 = LOAD_ACC128 5258 { 397, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #397 = LOAD_ACC64 5259 { 398, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #398 = LOAD_ACC64DSP 5260 { 399, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #399 = LOAD_CCOND_DSP 5261 { 400, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #400 = LONG_BRANCH_ADDiu 5262 { 401, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #401 = LONG_BRANCH_ADDiu2Op 5263 { 402, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #402 = LONG_BRANCH_DADDiu 5264 { 403, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #403 = LONG_BRANCH_DADDiu2Op 5265 { 404, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #404 = LONG_BRANCH_LUi 5266 { 405, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #405 = LONG_BRANCH_LUi2Op 5267 { 406, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #406 = LONG_BRANCH_LUi2Op_64 5268 { 407, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #407 = LWM_MM 5269 { 408, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #408 = LoadAddrImm32 5270 { 409, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #409 = LoadAddrImm64 5271 { 410, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #410 = LoadAddrReg32 5272 { 411, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #411 = LoadAddrReg64 5273 { 412, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #412 = LoadImm32 5274 { 413, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #413 = LoadImm64 5275 { 414, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #414 = LoadImmDoubleFGR 5276 { 415, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #415 = LoadImmDoubleFGR_32 5277 { 416, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #416 = LoadImmDoubleGPR 5278 { 417, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #417 = LoadImmSingleFGR 5279 { 418, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #418 = LoadImmSingleGPR 5280 { 419, 3, 1, 2, 729, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #419 = LwConstant32 5281 { 420, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #420 = MFTACX 5282 { 421, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #421 = MFTC0 5283 { 422, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #422 = MFTC1 5284 { 423, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #423 = MFTDSP 5285 { 424, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #424 = MFTGPR 5286 { 425, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #425 = MFTHC1 5287 { 426, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #426 = MFTHI 5288 { 427, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #427 = MFTLO 5289 { 428, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #428 = MIPSeh_return32 5290 { 429, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #429 = MIPSeh_return64 5291 { 430, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #430 = MSA_FP_EXTEND_D_PSEUDO 5292 { 431, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #431 = MSA_FP_EXTEND_W_PSEUDO 5293 { 432, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #432 = MSA_FP_ROUND_D_PSEUDO 5294 { 433, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #433 = MSA_FP_ROUND_W_PSEUDO 5295 { 434, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #434 = MTTACX 5296 { 435, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #435 = MTTC0 5297 { 436, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #436 = MTTC1 5298 { 437, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #437 = MTTDSP 5299 { 438, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #438 = MTTGPR 5300 { 439, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #439 = MTTHC1 5301 { 440, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #440 = MTTHI 5302 { 441, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #441 = MTTLO 5303 { 442, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #442 = MULImmMacro 5304 { 443, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #443 = MULOMacro 5305 { 444, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #444 = MULOUMacro 5306 { 445, 2, 0, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo121, -1 ,nullptr }, // Inst #445 = MultRxRy16 5307 { 446, 3, 1, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo122, -1 ,nullptr }, // Inst #446 = MultRxRyRz16 5308 { 447, 2, 0, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo121, -1 ,nullptr }, // Inst #447 = MultuRxRy16 5309 { 448, 3, 1, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo122, -1 ,nullptr }, // Inst #448 = MultuRxRyRz16 5310 { 449, 0, 0, 4, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #449 = NOP 5311 { 450, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #450 = NORImm 5312 { 451, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #451 = NORImm64 5313 { 452, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #452 = NOR_V_D_PSEUDO 5314 { 453, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #453 = NOR_V_H_PSEUDO 5315 { 454, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #454 = NOR_V_W_PSEUDO 5316 { 455, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #455 = OR_V_D_PSEUDO 5317 { 456, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #456 = OR_V_H_PSEUDO 5318 { 457, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #457 = OR_V_W_PSEUDO 5319 { 458, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #458 = PseudoCMPU_EQ_QB 5320 { 459, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #459 = PseudoCMPU_LE_QB 5321 { 460, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #460 = PseudoCMPU_LT_QB 5322 { 461, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #461 = PseudoCMP_EQ_PH 5323 { 462, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #462 = PseudoCMP_LE_PH 5324 { 463, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #463 = PseudoCMP_LT_PH 5325 { 464, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #464 = PseudoCVT_D32_W 5326 { 465, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #465 = PseudoCVT_D64_L 5327 { 466, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #466 = PseudoCVT_D64_W 5328 { 467, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #467 = PseudoCVT_S_L 5329 { 468, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #468 = PseudoCVT_S_W 5330 { 469, 3, 1, 4, 894, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #469 = PseudoDMULT 5331 { 470, 3, 1, 4, 895, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #470 = PseudoDMULTu 5332 { 471, 3, 1, 4, 896, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #471 = PseudoDSDIV 5333 { 472, 3, 1, 4, 897, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #472 = PseudoDUDIV 5334 { 473, 7, 2, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #473 = PseudoD_SELECT_I 5335 { 474, 7, 2, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #474 = PseudoD_SELECT_I64 5336 { 475, 1, 0, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #475 = PseudoIndirectBranch 5337 { 476, 1, 0, 4, 1012, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #476 = PseudoIndirectBranch64 5338 { 477, 1, 0, 4, 1016, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #477 = PseudoIndirectBranch64R6 5339 { 478, 1, 0, 4, 928, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #478 = PseudoIndirectBranchR6 5340 { 479, 1, 0, 4, 957, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #479 = PseudoIndirectBranch_MM 5341 { 480, 1, 0, 4, 990, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #480 = PseudoIndirectBranch_MMR6 5342 { 481, 1, 0, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #481 = PseudoIndirectHazardBranch 5343 { 482, 1, 0, 4, 1012, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #482 = PseudoIndirectHazardBranch64 5344 { 483, 1, 0, 4, 1016, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #483 = PseudoIndrectHazardBranch64R6 5345 { 484, 1, 0, 4, 928, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #484 = PseudoIndrectHazardBranchR6 5346 { 485, 4, 1, 4, 484, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #485 = PseudoMADD 5347 { 486, 4, 1, 4, 485, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #486 = PseudoMADDU 5348 { 487, 4, 1, 4, 850, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #487 = PseudoMADDU_MM 5349 { 488, 4, 1, 4, 849, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #488 = PseudoMADD_MM 5350 { 489, 2, 1, 4, 473, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #489 = PseudoMFHI 5351 { 490, 2, 1, 4, 898, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #490 = PseudoMFHI64 5352 { 491, 2, 1, 4, 859, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #491 = PseudoMFHI_MM 5353 { 492, 2, 1, 4, 473, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #492 = PseudoMFLO 5354 { 493, 2, 1, 4, 898, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #493 = PseudoMFLO64 5355 { 494, 2, 1, 4, 859, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #494 = PseudoMFLO_MM 5356 { 495, 4, 1, 4, 486, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #495 = PseudoMSUB 5357 { 496, 4, 1, 4, 487, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #496 = PseudoMSUBU 5358 { 497, 4, 1, 4, 852, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #497 = PseudoMSUBU_MM 5359 { 498, 4, 1, 4, 851, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #498 = PseudoMSUB_MM 5360 { 499, 3, 1, 4, 488, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #499 = PseudoMTLOHI 5361 { 500, 3, 1, 4, 899, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #500 = PseudoMTLOHI64 5362 { 501, 3, 1, 4, 1333, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #501 = PseudoMTLOHI_DSP 5363 { 502, 3, 1, 4, 860, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #502 = PseudoMTLOHI_MM 5364 { 503, 3, 1, 4, 855, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #503 = PseudoMULT 5365 { 504, 3, 1, 4, 853, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #504 = PseudoMULT_MM 5366 { 505, 3, 1, 4, 856, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #505 = PseudoMULTu 5367 { 506, 3, 1, 4, 854, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #506 = PseudoMULTu_MM 5368 { 507, 4, 1, 4, 1448, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #507 = PseudoPICK_PH 5369 { 508, 4, 1, 4, 1448, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #508 = PseudoPICK_QB 5370 { 509, 1, 0, 4, 383, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #509 = PseudoReturn 5371 { 510, 1, 0, 4, 1008, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #510 = PseudoReturn64 5372 { 511, 3, 1, 4, 857, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #511 = PseudoSDIV 5373 { 512, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #512 = PseudoSELECTFP_F_D32 5374 { 513, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #513 = PseudoSELECTFP_F_D64 5375 { 514, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #514 = PseudoSELECTFP_F_I 5376 { 515, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #515 = PseudoSELECTFP_F_I64 5377 { 516, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #516 = PseudoSELECTFP_F_S 5378 { 517, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #517 = PseudoSELECTFP_T_D32 5379 { 518, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #518 = PseudoSELECTFP_T_D64 5380 { 519, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #519 = PseudoSELECTFP_T_I 5381 { 520, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #520 = PseudoSELECTFP_T_I64 5382 { 521, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #521 = PseudoSELECTFP_T_S 5383 { 522, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #522 = PseudoSELECT_D32 5384 { 523, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #523 = PseudoSELECT_D64 5385 { 524, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #524 = PseudoSELECT_I 5386 { 525, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #525 = PseudoSELECT_I64 5387 { 526, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #526 = PseudoSELECT_S 5388 { 527, 3, 1, 4, 1203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #527 = PseudoTRUNC_W_D 5389 { 528, 3, 1, 4, 1203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #528 = PseudoTRUNC_W_D32 5390 { 529, 3, 1, 4, 1203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #529 = PseudoTRUNC_W_S 5391 { 530, 3, 1, 4, 858, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #530 = PseudoUDIV 5392 { 531, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #531 = ROL 5393 { 532, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #532 = ROLImm 5394 { 533, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #533 = ROR 5395 { 534, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #534 = RORImm 5396 { 535, 0, 0, 4, 377, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #535 = RetRA 5397 { 536, 0, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #536 = RetRA16 5398 { 537, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #537 = SDC1_M1 5399 { 538, 3, 1, 4, 877, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #538 = SDIV_MM_Pseudo 5400 { 539, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #539 = SDMacro 5401 { 540, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #540 = SDivIMacro 5402 { 541, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #541 = SDivMacro 5403 { 542, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #542 = SEQIMacro 5404 { 543, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #543 = SEQMacro 5405 { 544, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #544 = SGE 5406 { 545, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #545 = SGEImm 5407 { 546, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #546 = SGEImm64 5408 { 547, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #547 = SGEU 5409 { 548, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #548 = SGEUImm 5410 { 549, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #549 = SGEUImm64 5411 { 550, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #550 = SGTImm 5412 { 551, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #551 = SGTImm64 5413 { 552, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #552 = SGTUImm 5414 { 553, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #553 = SGTUImm64 5415 { 554, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #554 = SLTImm64 5416 { 555, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #555 = SLTUImm64 5417 { 556, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #556 = SNZ_B_PSEUDO 5418 { 557, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #557 = SNZ_D_PSEUDO 5419 { 558, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #558 = SNZ_H_PSEUDO 5420 { 559, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #559 = SNZ_V_PSEUDO 5421 { 560, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #560 = SNZ_W_PSEUDO 5422 { 561, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #561 = SRemIMacro 5423 { 562, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #562 = SRemMacro 5424 { 563, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #563 = STORE_ACC128 5425 { 564, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #564 = STORE_ACC64 5426 { 565, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #565 = STORE_ACC64DSP 5427 { 566, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #566 = STORE_CCOND_DSP 5428 { 567, 3, 0, 4, 697, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #567 = ST_F16 5429 { 568, 3, 0, 4, 1128, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #568 = SWM_MM 5430 { 569, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #569 = SZ_B_PSEUDO 5431 { 570, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #570 = SZ_D_PSEUDO 5432 { 571, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #571 = SZ_H_PSEUDO 5433 { 572, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #572 = SZ_V_PSEUDO 5434 { 573, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #573 = SZ_W_PSEUDO 5435 { 574, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #574 = SaaAddr 5436 { 575, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #575 = SaadAddr 5437 { 576, 4, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #576 = SelBeqZ 5438 { 577, 4, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #577 = SelBneZ 5439 { 578, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #578 = SelTBteqZCmp 5440 { 579, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #579 = SelTBteqZCmpi 5441 { 580, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #580 = SelTBteqZSlt 5442 { 581, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #581 = SelTBteqZSlti 5443 { 582, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #582 = SelTBteqZSltiu 5444 { 583, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #583 = SelTBteqZSltu 5445 { 584, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #584 = SelTBtneZCmp 5446 { 585, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #585 = SelTBtneZCmpi 5447 { 586, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #586 = SelTBtneZSlt 5448 { 587, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #587 = SelTBtneZSlti 5449 { 588, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #588 = SelTBtneZSltiu 5450 { 589, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #589 = SelTBtneZSltu 5451 { 590, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #590 = SltCCRxRy16 5452 { 591, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #591 = SltiCCRxImmX16 5453 { 592, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #592 = SltiuCCRxImmX16 5454 { 593, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #593 = SltuCCRxRy16 5455 { 594, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo122, -1 ,nullptr }, // Inst #594 = SltuRxRyRz16 5456 { 595, 1, 0, 4, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #595 = TAILCALL 5457 { 596, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo88, -1 ,nullptr }, // Inst #596 = TAILCALL64R6REG 5458 { 597, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo88, -1 ,nullptr }, // Inst #597 = TAILCALLHB64R6REG 5459 { 598, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #598 = TAILCALLHBR6REG 5460 { 599, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #599 = TAILCALLR6REG 5461 { 600, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #600 = TAILCALLREG 5462 { 601, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo88, -1 ,nullptr }, // Inst #601 = TAILCALLREG64 5463 { 602, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #602 = TAILCALLREGHB 5464 { 603, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo88, -1 ,nullptr }, // Inst #603 = TAILCALLREGHB64 5465 { 604, 1, 0, 4, 955, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #604 = TAILCALLREG_MM 5466 { 605, 1, 0, 4, 997, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #605 = TAILCALLREG_MMR6 5467 { 606, 1, 0, 4, 956, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #606 = TAILCALL_MM 5468 { 607, 1, 0, 4, 998, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #607 = TAILCALL_MMR6 5469 { 608, 0, 0, 4, 397, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #608 = TRAP 5470 { 609, 0, 0, 4, 973, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #609 = TRAP_MM 5471 { 610, 3, 1, 4, 878, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #610 = UDIV_MM_Pseudo 5472 { 611, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #611 = UDivIMacro 5473 { 612, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #612 = UDivMacro 5474 { 613, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #613 = URemIMacro 5475 { 614, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #614 = URemMacro 5476 { 615, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #615 = Ulh 5477 { 616, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #616 = Ulhu 5478 { 617, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #617 = Ulw 5479 { 618, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #618 = Ush 5480 { 619, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #619 = Usw 5481 { 620, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #620 = XOR_V_D_PSEUDO 5482 { 621, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #621 = XOR_V_H_PSEUDO 5483 { 622, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #622 = XOR_V_W_PSEUDO 5484 { 623, 2, 1, 4, 1346, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo159, -1 ,nullptr }, // Inst #623 = ABSQ_S_PH 5485 { 624, 2, 1, 4, 1497, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo159, -1 ,nullptr }, // Inst #624 = ABSQ_S_PH_MM 5486 { 625, 2, 1, 4, 1449, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo159, -1 ,nullptr }, // Inst #625 = ABSQ_S_QB 5487 { 626, 2, 1, 4, 1613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo159, -1 ,nullptr }, // Inst #626 = ABSQ_S_QB_MMR2 5488 { 627, 2, 1, 4, 1347, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo38, -1 ,nullptr }, // Inst #627 = ABSQ_S_W 5489 { 628, 2, 1, 4, 1498, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo38, -1 ,nullptr }, // Inst #628 = ABSQ_S_W_MM 5490 { 629, 3, 1, 4, 491, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #629 = ADD 5491 { 630, 2, 1, 4, 717, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #630 = ADDIUPC 5492 { 631, 2, 1, 4, 730, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #631 = ADDIUPC_MM 5493 { 632, 2, 1, 4, 766, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #632 = ADDIUPC_MMR6 5494 { 633, 2, 1, 2, 730, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #633 = ADDIUR1SP_MM 5495 { 634, 3, 1, 2, 730, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #634 = ADDIUR2_MM 5496 { 635, 3, 1, 2, 730, 0, 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #635 = ADDIUS5_MM 5497 { 636, 1, 0, 2, 730, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #636 = ADDIUSP_MM 5498 { 637, 3, 1, 4, 767, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #637 = ADDIU_MMR6 5499 { 638, 3, 1, 4, 1450, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #638 = ADDQH_PH 5500 { 639, 3, 1, 4, 1614, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #639 = ADDQH_PH_MMR2 5501 { 640, 3, 1, 4, 1451, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #640 = ADDQH_R_PH 5502 { 641, 3, 1, 4, 1615, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #641 = ADDQH_R_PH_MMR2 5503 { 642, 3, 1, 4, 1452, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #642 = ADDQH_R_W 5504 { 643, 3, 1, 4, 1616, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #643 = ADDQH_R_W_MMR2 5505 { 644, 3, 1, 4, 1453, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #644 = ADDQH_W 5506 { 645, 3, 1, 4, 1617, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #645 = ADDQH_W_MMR2 5507 { 646, 3, 1, 4, 1348, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #646 = ADDQ_PH 5508 { 647, 3, 1, 4, 1499, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #647 = ADDQ_PH_MM 5509 { 648, 3, 1, 4, 1349, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #648 = ADDQ_S_PH 5510 { 649, 3, 1, 4, 1500, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #649 = ADDQ_S_PH_MM 5511 { 650, 3, 1, 4, 1350, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #650 = ADDQ_S_W 5512 { 651, 3, 1, 4, 1501, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #651 = ADDQ_S_W_MM 5513 { 652, 3, 1, 4, 1351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo65, -1 ,nullptr }, // Inst #652 = ADDSC 5514 { 653, 3, 1, 4, 1502, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo65, -1 ,nullptr }, // Inst #653 = ADDSC_MM 5515 { 654, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #654 = ADDS_A_B 5516 { 655, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #655 = ADDS_A_D 5517 { 656, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #656 = ADDS_A_H 5518 { 657, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #657 = ADDS_A_W 5519 { 658, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #658 = ADDS_S_B 5520 { 659, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #659 = ADDS_S_D 5521 { 660, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #660 = ADDS_S_H 5522 { 661, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #661 = ADDS_S_W 5523 { 662, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #662 = ADDS_U_B 5524 { 663, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #663 = ADDS_U_D 5525 { 664, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #664 = ADDS_U_H 5526 { 665, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #665 = ADDS_U_W 5527 { 666, 3, 1, 2, 731, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #666 = ADDU16_MM 5528 { 667, 3, 1, 2, 768, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #667 = ADDU16_MMR6 5529 { 668, 3, 1, 4, 1454, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #668 = ADDUH_QB 5530 { 669, 3, 1, 4, 1618, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #669 = ADDUH_QB_MMR2 5531 { 670, 3, 1, 4, 1455, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #670 = ADDUH_R_QB 5532 { 671, 3, 1, 4, 1619, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #671 = ADDUH_R_QB_MMR2 5533 { 672, 3, 1, 4, 768, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #672 = ADDU_MMR6 5534 { 673, 3, 1, 4, 1456, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #673 = ADDU_PH 5535 { 674, 3, 1, 4, 1620, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #674 = ADDU_PH_MMR2 5536 { 675, 3, 1, 4, 1352, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #675 = ADDU_QB 5537 { 676, 3, 1, 4, 1503, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #676 = ADDU_QB_MM 5538 { 677, 3, 1, 4, 1457, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #677 = ADDU_S_PH 5539 { 678, 3, 1, 4, 1621, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #678 = ADDU_S_PH_MMR2 5540 { 679, 3, 1, 4, 1353, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #679 = ADDU_S_QB 5541 { 680, 3, 1, 4, 1504, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #680 = ADDU_S_QB_MM 5542 { 681, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #681 = ADDVI_B 5543 { 682, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #682 = ADDVI_D 5544 { 683, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #683 = ADDVI_H 5545 { 684, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #684 = ADDVI_W 5546 { 685, 3, 1, 4, 535, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #685 = ADDV_B 5547 { 686, 3, 1, 4, 535, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #686 = ADDV_D 5548 { 687, 3, 1, 4, 535, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #687 = ADDV_H 5549 { 688, 3, 1, 4, 535, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #688 = ADDV_W 5550 { 689, 3, 1, 4, 1354, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #689 = ADDWC 5551 { 690, 3, 1, 4, 1505, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #690 = ADDWC_MM 5552 { 691, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #691 = ADD_A_B 5553 { 692, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #692 = ADD_A_D 5554 { 693, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #693 = ADD_A_H 5555 { 694, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #694 = ADD_A_W 5556 { 695, 3, 1, 4, 732, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #695 = ADD_MM 5557 { 696, 3, 1, 4, 769, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #696 = ADD_MMR6 5558 { 697, 3, 1, 4, 492, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #697 = ADDi 5559 { 698, 3, 1, 4, 733, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #698 = ADDi_MM 5560 { 699, 3, 1, 4, 493, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #699 = ADDiu 5561 { 700, 3, 1, 4, 730, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #700 = ADDiu_MM 5562 { 701, 3, 1, 4, 504, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #701 = ADDu 5563 { 702, 3, 1, 4, 731, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #702 = ADDu_MM 5564 { 703, 4, 1, 4, 718, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #703 = ALIGN 5565 { 704, 4, 1, 4, 770, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #704 = ALIGN_MMR6 5566 { 705, 2, 1, 4, 719, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #705 = ALUIPC 5567 { 706, 2, 1, 4, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #706 = ALUIPC_MMR6 5568 { 707, 3, 1, 4, 359, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #707 = AND 5569 { 708, 3, 1, 2, 734, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #708 = AND16_MM 5570 { 709, 3, 1, 2, 772, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #709 = AND16_MMR6 5571 { 710, 3, 1, 4, 798, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #710 = AND64 5572 { 711, 3, 1, 2, 734, 0, 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #711 = ANDI16_MM 5573 { 712, 3, 1, 2, 772, 0, 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #712 = ANDI16_MMR6 5574 { 713, 3, 1, 4, 544, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #713 = ANDI_B 5575 { 714, 3, 1, 4, 773, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #714 = ANDI_MMR6 5576 { 715, 3, 1, 4, 734, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #715 = AND_MM 5577 { 716, 3, 1, 4, 772, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #716 = AND_MMR6 5578 { 717, 3, 1, 4, 543, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #717 = AND_V 5579 { 718, 3, 1, 4, 494, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #718 = ANDi 5580 { 719, 3, 1, 4, 798, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #719 = ANDi64 5581 { 720, 3, 1, 4, 735, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #720 = ANDi_MM 5582 { 721, 4, 1, 4, 1458, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #721 = APPEND 5583 { 722, 4, 1, 4, 1622, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #722 = APPEND_MMR2 5584 { 723, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #723 = ASUB_S_B 5585 { 724, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #724 = ASUB_S_D 5586 { 725, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #725 = ASUB_S_H 5587 { 726, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #726 = ASUB_S_W 5588 { 727, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #727 = ASUB_U_B 5589 { 728, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #728 = ASUB_U_D 5590 { 729, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #729 = ASUB_U_H 5591 { 730, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #730 = ASUB_U_W 5592 { 731, 3, 1, 4, 720, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #731 = AUI 5593 { 732, 2, 1, 4, 721, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #732 = AUIPC 5594 { 733, 2, 1, 4, 774, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #733 = AUIPC_MMR6 5595 { 734, 3, 1, 4, 775, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #734 = AUI_MMR6 5596 { 735, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #735 = AVER_S_B 5597 { 736, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #736 = AVER_S_D 5598 { 737, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #737 = AVER_S_H 5599 { 738, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #738 = AVER_S_W 5600 { 739, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #739 = AVER_U_B 5601 { 740, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #740 = AVER_U_D 5602 { 741, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #741 = AVER_U_H 5603 { 742, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #742 = AVER_U_W 5604 { 743, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #743 = AVE_S_B 5605 { 744, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #744 = AVE_S_D 5606 { 745, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #745 = AVE_S_H 5607 { 746, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #746 = AVE_S_W 5608 { 747, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #747 = AVE_U_B 5609 { 748, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #748 = AVE_U_D 5610 { 749, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #749 = AVE_U_H 5611 { 750, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #750 = AVE_U_W 5612 { 751, 2, 1, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #751 = AddiuRxImmX16 5613 { 752, 2, 1, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #752 = AddiuRxPcImmX16 5614 { 753, 3, 1, 2, 727, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #753 = AddiuRxRxImm16 5615 { 754, 3, 1, 4, 727, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #754 = AddiuRxRxImmX16 5616 { 755, 3, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #755 = AddiuRxRyOffMemX16 5617 { 756, 1, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr }, // Inst #756 = AddiuSpImm16 5618 { 757, 1, 0, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr }, // Inst #757 = AddiuSpImmX16 5619 { 758, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #758 = AdduRxRyRz16 5620 { 759, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #759 = AndRxRxRy16 5621 { 760, 1, 0, 2, 937, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #760 = B16_MM 5622 { 761, 3, 1, 4, 1190, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #761 = BADDu 5623 { 762, 1, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #762 = BAL 5624 { 763, 1, 0, 4, 918, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #763 = BALC 5625 { 764, 1, 0, 4, 991, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #764 = BALC_MMR6 5626 { 765, 4, 1, 4, 1459, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #765 = BALIGN 5627 { 766, 4, 1, 4, 1623, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #766 = BALIGN_MMR2 5628 { 767, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #767 = BBIT0 5629 { 768, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #768 = BBIT032 5630 { 769, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #769 = BBIT1 5631 { 770, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #770 = BBIT132 5632 { 771, 1, 0, 4, 921, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #771 = BC 5633 { 772, 1, 0, 2, 974, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #772 = BC16_MMR6 5634 { 773, 2, 0, 4, 1220, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #773 = BC1EQZ 5635 { 774, 2, 0, 4, 975, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #774 = BC1EQZC_MMR6 5636 { 775, 2, 0, 4, 682, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #775 = BC1F 5637 { 776, 2, 0, 4, 683, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #776 = BC1FL 5638 { 777, 2, 0, 4, 939, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #777 = BC1F_MM 5639 { 778, 2, 0, 4, 1220, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #778 = BC1NEZ 5640 { 779, 2, 0, 4, 975, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #779 = BC1NEZC_MMR6 5641 { 780, 2, 0, 4, 684, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #780 = BC1T 5642 { 781, 2, 0, 4, 685, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #781 = BC1TL 5643 { 782, 2, 0, 4, 940, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #782 = BC1T_MM 5644 { 783, 2, 0, 4, 922, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #783 = BC2EQZ 5645 { 784, 2, 0, 4, 976, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo180, -1 ,nullptr }, // Inst #784 = BC2EQZC_MMR6 5646 { 785, 2, 0, 4, 922, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #785 = BC2NEZ 5647 { 786, 2, 0, 4, 976, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo180, -1 ,nullptr }, // Inst #786 = BC2NEZC_MMR6 5648 { 787, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #787 = BCLRI_B 5649 { 788, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #788 = BCLRI_D 5650 { 789, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #789 = BCLRI_H 5651 { 790, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #790 = BCLRI_W 5652 { 791, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #791 = BCLR_B 5653 { 792, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #792 = BCLR_D 5654 { 793, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #793 = BCLR_H 5655 { 794, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #794 = BCLR_W 5656 { 795, 1, 0, 4, 974, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #795 = BC_MMR6 5657 { 796, 3, 0, 4, 912, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #796 = BEQ 5658 { 797, 3, 0, 4, 1001, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #797 = BEQ64 5659 { 798, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #798 = BEQC 5660 { 799, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #799 = BEQC64 5661 { 800, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #800 = BEQC_MMR6 5662 { 801, 3, 0, 4, 372, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #801 = BEQL 5663 { 802, 2, 0, 2, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo181, -1 ,nullptr }, // Inst #802 = BEQZ16_MM 5664 { 803, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #803 = BEQZALC 5665 { 804, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #804 = BEQZALC_MMR6 5666 { 805, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #805 = BEQZC 5667 { 806, 2, 0, 2, 978, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo181, -1 ,nullptr }, // Inst #806 = BEQZC16_MMR6 5668 { 807, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #807 = BEQZC64 5669 { 808, 2, 0, 4, 942, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #808 = BEQZC_MM 5670 { 809, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #809 = BEQZC_MMR6 5671 { 810, 3, 0, 4, 943, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #810 = BEQ_MM 5672 { 811, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #811 = BGEC 5673 { 812, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #812 = BGEC64 5674 { 813, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #813 = BGEC_MMR6 5675 { 814, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #814 = BGEUC 5676 { 815, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #815 = BGEUC64 5677 { 816, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #816 = BGEUC_MMR6 5678 { 817, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #817 = BGEZ 5679 { 818, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #818 = BGEZ64 5680 { 819, 2, 0, 4, 917, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #819 = BGEZAL 5681 { 820, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #820 = BGEZALC 5682 { 821, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #821 = BGEZALC_MMR6 5683 { 822, 2, 0, 4, 371, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #822 = BGEZALL 5684 { 823, 2, 0, 4, 949, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #823 = BGEZALS_MM 5685 { 824, 2, 0, 4, 950, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #824 = BGEZAL_MM 5686 { 825, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #825 = BGEZC 5687 { 826, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #826 = BGEZC64 5688 { 827, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #827 = BGEZC_MMR6 5689 { 828, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #828 = BGEZL 5690 { 829, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #829 = BGEZ_MM 5691 { 830, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #830 = BGTZ 5692 { 831, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #831 = BGTZ64 5693 { 832, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #832 = BGTZALC 5694 { 833, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #833 = BGTZALC_MMR6 5695 { 834, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #834 = BGTZC 5696 { 835, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #835 = BGTZC64 5697 { 836, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #836 = BGTZC_MMR6 5698 { 837, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #837 = BGTZL 5699 { 838, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #838 = BGTZ_MM 5700 { 839, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #839 = BINSLI_B 5701 { 840, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #840 = BINSLI_D 5702 { 841, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #841 = BINSLI_H 5703 { 842, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #842 = BINSLI_W 5704 { 843, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #843 = BINSL_B 5705 { 844, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #844 = BINSL_D 5706 { 845, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #845 = BINSL_H 5707 { 846, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #846 = BINSL_W 5708 { 847, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #847 = BINSRI_B 5709 { 848, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #848 = BINSRI_D 5710 { 849, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #849 = BINSRI_H 5711 { 850, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #850 = BINSRI_W 5712 { 851, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #851 = BINSR_B 5713 { 852, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #852 = BINSR_D 5714 { 853, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #853 = BINSR_H 5715 { 854, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #854 = BINSR_W 5716 { 855, 2, 1, 4, 1355, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #855 = BITREV 5717 { 856, 2, 1, 4, 1506, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #856 = BITREV_MM 5718 { 857, 2, 1, 4, 722, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #857 = BITSWAP 5719 { 858, 2, 1, 4, 776, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #858 = BITSWAP_MMR6 5720 { 859, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #859 = BLEZ 5721 { 860, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #860 = BLEZ64 5722 { 861, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #861 = BLEZALC 5723 { 862, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #862 = BLEZALC_MMR6 5724 { 863, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #863 = BLEZC 5725 { 864, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #864 = BLEZC64 5726 { 865, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #865 = BLEZC_MMR6 5727 { 866, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #866 = BLEZL 5728 { 867, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #867 = BLEZ_MM 5729 { 868, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #868 = BLTC 5730 { 869, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #869 = BLTC64 5731 { 870, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #870 = BLTC_MMR6 5732 { 871, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #871 = BLTUC 5733 { 872, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #872 = BLTUC64 5734 { 873, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #873 = BLTUC_MMR6 5735 { 874, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #874 = BLTZ 5736 { 875, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #875 = BLTZ64 5737 { 876, 2, 0, 4, 911, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #876 = BLTZAL 5738 { 877, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #877 = BLTZALC 5739 { 878, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #878 = BLTZALC_MMR6 5740 { 879, 2, 0, 4, 371, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #879 = BLTZALL 5741 { 880, 2, 0, 4, 949, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #880 = BLTZALS_MM 5742 { 881, 2, 0, 4, 950, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #881 = BLTZAL_MM 5743 { 882, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #882 = BLTZC 5744 { 883, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #883 = BLTZC64 5745 { 884, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #884 = BLTZC_MMR6 5746 { 885, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #885 = BLTZL 5747 { 886, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #886 = BLTZ_MM 5748 { 887, 4, 1, 4, 519, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #887 = BMNZI_B 5749 { 888, 4, 1, 4, 519, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #888 = BMNZ_V 5750 { 889, 4, 1, 4, 519, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #889 = BMZI_B 5751 { 890, 4, 1, 4, 519, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #890 = BMZ_V 5752 { 891, 3, 0, 4, 912, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #891 = BNE 5753 { 892, 3, 0, 4, 1001, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #892 = BNE64 5754 { 893, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #893 = BNEC 5755 { 894, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #894 = BNEC64 5756 { 895, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #895 = BNEC_MMR6 5757 { 896, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #896 = BNEGI_B 5758 { 897, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #897 = BNEGI_D 5759 { 898, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #898 = BNEGI_H 5760 { 899, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #899 = BNEGI_W 5761 { 900, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #900 = BNEG_B 5762 { 901, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #901 = BNEG_D 5763 { 902, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #902 = BNEG_H 5764 { 903, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #903 = BNEG_W 5765 { 904, 3, 0, 4, 372, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #904 = BNEL 5766 { 905, 2, 0, 2, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo181, -1 ,nullptr }, // Inst #905 = BNEZ16_MM 5767 { 906, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #906 = BNEZALC 5768 { 907, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #907 = BNEZALC_MMR6 5769 { 908, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #908 = BNEZC 5770 { 909, 2, 0, 2, 978, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo181, -1 ,nullptr }, // Inst #909 = BNEZC16_MMR6 5771 { 910, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #910 = BNEZC64 5772 { 911, 2, 0, 4, 942, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #911 = BNEZC_MM 5773 { 912, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #912 = BNEZC_MMR6 5774 { 913, 3, 0, 4, 943, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #913 = BNE_MM 5775 { 914, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #914 = BNVC 5776 { 915, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #915 = BNVC_MMR6 5777 { 916, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #916 = BNZ_B 5778 { 917, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo188, -1 ,nullptr }, // Inst #917 = BNZ_D 5779 { 918, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo189, -1 ,nullptr }, // Inst #918 = BNZ_H 5780 { 919, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #919 = BNZ_V 5781 { 920, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo190, -1 ,nullptr }, // Inst #920 = BNZ_W 5782 { 921, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #921 = BOVC 5783 { 922, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #922 = BOVC_MMR6 5784 { 923, 1, 0, 4, 1356, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #923 = BPOSGE32 5785 { 924, 1, 0, 4, 1659, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #924 = BPOSGE32C_MMR3 5786 { 925, 1, 0, 4, 1507, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #925 = BPOSGE32_MM 5787 { 926, 2, 0, 4, 374, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #926 = BREAK 5788 { 927, 1, 0, 2, 958, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #927 = BREAK16_MM 5789 { 928, 1, 0, 2, 999, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #928 = BREAK16_MMR6 5790 { 929, 2, 0, 4, 958, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #929 = BREAK_MM 5791 { 930, 2, 0, 4, 999, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #930 = BREAK_MMR6 5792 { 931, 4, 1, 4, 518, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #931 = BSELI_B 5793 { 932, 4, 1, 4, 518, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #932 = BSEL_V 5794 { 933, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #933 = BSETI_B 5795 { 934, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #934 = BSETI_D 5796 { 935, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #935 = BSETI_H 5797 { 936, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #936 = BSETI_W 5798 { 937, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #937 = BSET_B 5799 { 938, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #938 = BSET_D 5800 { 939, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #939 = BSET_H 5801 { 940, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #940 = BSET_W 5802 { 941, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #941 = BZ_B 5803 { 942, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo188, -1 ,nullptr }, // Inst #942 = BZ_D 5804 { 943, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo189, -1 ,nullptr }, // Inst #943 = BZ_H 5805 { 944, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #944 = BZ_V 5806 { 945, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo190, -1 ,nullptr }, // Inst #945 = BZ_W 5807 { 946, 2, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #946 = BeqzRxImm16 5808 { 947, 2, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #947 = BeqzRxImmX16 5809 { 948, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #948 = Bimm16 5810 { 949, 1, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #949 = BimmX16 5811 { 950, 2, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #950 = BnezRxImm16 5812 { 951, 2, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #951 = BnezRxImmX16 5813 { 952, 0, 0, 2, 935, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #952 = Break16 5814 { 953, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #953 = Bteqz16 5815 { 954, 1, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #954 = BteqzX16 5816 { 955, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #955 = Btnez16 5817 { 956, 1, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #956 = BtnezX16 5818 { 957, 3, 0, 4, 465, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #957 = CACHE 5819 { 958, 3, 0, 4, 466, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #958 = CACHEE 5820 { 959, 3, 0, 4, 1099, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #959 = CACHEE_MM 5821 { 960, 3, 0, 4, 1132, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #960 = CACHE_MM 5822 { 961, 3, 0, 4, 1154, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #961 = CACHE_MMR6 5823 { 962, 3, 0, 4, 1080, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #962 = CACHE_R6 5824 { 963, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #963 = CEIL_L_D64 5825 { 964, 2, 1, 4, 1300, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #964 = CEIL_L_D_MMR6 5826 { 965, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #965 = CEIL_L_S 5827 { 966, 2, 1, 4, 1300, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #966 = CEIL_L_S_MMR6 5828 { 967, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #967 = CEIL_W_D32 5829 { 968, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #968 = CEIL_W_D64 5830 { 969, 2, 1, 4, 1300, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #969 = CEIL_W_D_MMR6 5831 { 970, 2, 1, 4, 1236, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #970 = CEIL_W_MM 5832 { 971, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #971 = CEIL_W_S 5833 { 972, 2, 1, 4, 1236, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #972 = CEIL_W_S_MM 5834 { 973, 2, 1, 4, 1300, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #973 = CEIL_W_S_MMR6 5835 { 974, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #974 = CEQI_B 5836 { 975, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #975 = CEQI_D 5837 { 976, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #976 = CEQI_H 5838 { 977, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #977 = CEQI_W 5839 { 978, 3, 1, 4, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #978 = CEQ_B 5840 { 979, 3, 1, 4, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #979 = CEQ_D 5841 { 980, 3, 1, 4, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #980 = CEQ_H 5842 { 981, 3, 1, 4, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #981 = CEQ_W 5843 { 982, 2, 1, 4, 686, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #982 = CFC1 5844 { 983, 2, 1, 4, 1283, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #983 = CFC1_MM 5845 { 984, 2, 1, 4, 1049, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #984 = CFC2_MM 5846 { 985, 2, 1, 4, 524, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #985 = CFCMSA 5847 { 986, 4, 1, 4, 1192, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #986 = CINS 5848 { 987, 4, 1, 4, 1192, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #987 = CINS32 5849 { 988, 4, 1, 4, 1192, 0, 0x1ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #988 = CINS64_32 5850 { 989, 4, 1, 4, 1192, 0, 0x1ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #989 = CINS_i32 5851 { 990, 2, 1, 4, 1217, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #990 = CLASS_D 5852 { 991, 2, 1, 4, 1303, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #991 = CLASS_D_MMR6 5853 { 992, 2, 1, 4, 1216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #992 = CLASS_S 5854 { 993, 2, 1, 4, 1303, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #993 = CLASS_S_MMR6 5855 { 994, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #994 = CLEI_S_B 5856 { 995, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #995 = CLEI_S_D 5857 { 996, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #996 = CLEI_S_H 5858 { 997, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #997 = CLEI_S_W 5859 { 998, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #998 = CLEI_U_B 5860 { 999, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #999 = CLEI_U_D 5861 { 1000, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1000 = CLEI_U_H 5862 { 1001, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1001 = CLEI_U_W 5863 { 1002, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1002 = CLE_S_B 5864 { 1003, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1003 = CLE_S_D 5865 { 1004, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1004 = CLE_S_H 5866 { 1005, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1005 = CLE_S_W 5867 { 1006, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1006 = CLE_U_B 5868 { 1007, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1007 = CLE_U_D 5869 { 1008, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1008 = CLE_U_H 5870 { 1009, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1009 = CLE_U_W 5871 { 1010, 2, 1, 4, 469, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1010 = CLO 5872 { 1011, 2, 1, 4, 736, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1011 = CLO_MM 5873 { 1012, 2, 1, 4, 777, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1012 = CLO_MMR6 5874 { 1013, 2, 1, 4, 723, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1013 = CLO_R6 5875 { 1014, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1014 = CLTI_S_B 5876 { 1015, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1015 = CLTI_S_D 5877 { 1016, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1016 = CLTI_S_H 5878 { 1017, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1017 = CLTI_S_W 5879 { 1018, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1018 = CLTI_U_B 5880 { 1019, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1019 = CLTI_U_D 5881 { 1020, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1020 = CLTI_U_H 5882 { 1021, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1021 = CLTI_U_W 5883 { 1022, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1022 = CLT_S_B 5884 { 1023, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1023 = CLT_S_D 5885 { 1024, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1024 = CLT_S_H 5886 { 1025, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1025 = CLT_S_W 5887 { 1026, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1026 = CLT_U_B 5888 { 1027, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1027 = CLT_U_D 5889 { 1028, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1028 = CLT_U_H 5890 { 1029, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1029 = CLT_U_W 5891 { 1030, 2, 1, 4, 470, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1030 = CLZ 5892 { 1031, 2, 1, 4, 737, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1031 = CLZ_MM 5893 { 1032, 2, 1, 4, 778, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1032 = CLZ_MMR6 5894 { 1033, 2, 1, 4, 724, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1033 = CLZ_R6 5895 { 1034, 3, 1, 4, 1460, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1034 = CMPGDU_EQ_QB 5896 { 1035, 3, 1, 4, 1624, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1035 = CMPGDU_EQ_QB_MMR2 5897 { 1036, 3, 1, 4, 1461, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1036 = CMPGDU_LE_QB 5898 { 1037, 3, 1, 4, 1625, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1037 = CMPGDU_LE_QB_MMR2 5899 { 1038, 3, 1, 4, 1462, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1038 = CMPGDU_LT_QB 5900 { 1039, 3, 1, 4, 1626, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1039 = CMPGDU_LT_QB_MMR2 5901 { 1040, 3, 1, 4, 1357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1040 = CMPGU_EQ_QB 5902 { 1041, 3, 1, 4, 1508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1041 = CMPGU_EQ_QB_MM 5903 { 1042, 3, 1, 4, 1358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1042 = CMPGU_LE_QB 5904 { 1043, 3, 1, 4, 1509, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1043 = CMPGU_LE_QB_MM 5905 { 1044, 3, 1, 4, 1359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1044 = CMPGU_LT_QB 5906 { 1045, 3, 1, 4, 1510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1045 = CMPGU_LT_QB_MM 5907 { 1046, 2, 0, 4, 1360, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1046 = CMPU_EQ_QB 5908 { 1047, 2, 0, 4, 1511, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1047 = CMPU_EQ_QB_MM 5909 { 1048, 2, 0, 4, 1361, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1048 = CMPU_LE_QB 5910 { 1049, 2, 0, 4, 1512, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1049 = CMPU_LE_QB_MM 5911 { 1050, 2, 0, 4, 1362, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1050 = CMPU_LT_QB 5912 { 1051, 2, 0, 4, 1513, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1051 = CMPU_LT_QB_MM 5913 { 1052, 3, 1, 4, 1290, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1052 = CMP_AF_D_MMR6 5914 { 1053, 3, 1, 4, 1291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1053 = CMP_AF_S_MMR6 5915 { 1054, 3, 1, 4, 556, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1054 = CMP_EQ_D 5916 { 1055, 3, 1, 4, 1290, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1055 = CMP_EQ_D_MMR6 5917 { 1056, 2, 0, 4, 1363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1056 = CMP_EQ_PH 5918 { 1057, 2, 0, 4, 1514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1057 = CMP_EQ_PH_MM 5919 { 1058, 3, 1, 4, 557, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1058 = CMP_EQ_S 5920 { 1059, 3, 1, 4, 1291, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1059 = CMP_EQ_S_MMR6 5921 { 1060, 3, 1, 4, 1660, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1060 = CMP_F_D 5922 { 1061, 3, 1, 4, 1661, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1061 = CMP_F_S 5923 { 1062, 3, 1, 4, 562, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1062 = CMP_LE_D 5924 { 1063, 3, 1, 4, 1290, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1063 = CMP_LE_D_MMR6 5925 { 1064, 2, 0, 4, 1364, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1064 = CMP_LE_PH 5926 { 1065, 2, 0, 4, 1515, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1065 = CMP_LE_PH_MM 5927 { 1066, 3, 1, 4, 563, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1066 = CMP_LE_S 5928 { 1067, 3, 1, 4, 1291, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1067 = CMP_LE_S_MMR6 5929 { 1068, 3, 1, 4, 558, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1068 = CMP_LT_D 5930 { 1069, 3, 1, 4, 1290, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1069 = CMP_LT_D_MMR6 5931 { 1070, 2, 0, 4, 1365, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1070 = CMP_LT_PH 5932 { 1071, 2, 0, 4, 1516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1071 = CMP_LT_PH_MM 5933 { 1072, 3, 1, 4, 559, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1072 = CMP_LT_S 5934 { 1073, 3, 1, 4, 1291, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1073 = CMP_LT_S_MMR6 5935 { 1074, 3, 1, 4, 1662, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1074 = CMP_SAF_D 5936 { 1075, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1075 = CMP_SAF_D_MMR6 5937 { 1076, 3, 1, 4, 1663, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1076 = CMP_SAF_S 5938 { 1077, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1077 = CMP_SAF_S_MMR6 5939 { 1078, 3, 1, 4, 1664, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1078 = CMP_SEQ_D 5940 { 1079, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1079 = CMP_SEQ_D_MMR6 5941 { 1080, 3, 1, 4, 1665, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1080 = CMP_SEQ_S 5942 { 1081, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1081 = CMP_SEQ_S_MMR6 5943 { 1082, 3, 1, 4, 1666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1082 = CMP_SLE_D 5944 { 1083, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1083 = CMP_SLE_D_MMR6 5945 { 1084, 3, 1, 4, 1667, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1084 = CMP_SLE_S 5946 { 1085, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1085 = CMP_SLE_S_MMR6 5947 { 1086, 3, 1, 4, 1668, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1086 = CMP_SLT_D 5948 { 1087, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1087 = CMP_SLT_D_MMR6 5949 { 1088, 3, 1, 4, 1669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1088 = CMP_SLT_S 5950 { 1089, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1089 = CMP_SLT_S_MMR6 5951 { 1090, 3, 1, 4, 1670, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1090 = CMP_SUEQ_D 5952 { 1091, 3, 1, 4, 1294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1091 = CMP_SUEQ_D_MMR6 5953 { 1092, 3, 1, 4, 1671, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1092 = CMP_SUEQ_S 5954 { 1093, 3, 1, 4, 1295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1093 = CMP_SUEQ_S_MMR6 5955 { 1094, 3, 1, 4, 1672, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1094 = CMP_SULE_D 5956 { 1095, 3, 1, 4, 1294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1095 = CMP_SULE_D_MMR6 5957 { 1096, 3, 1, 4, 1673, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1096 = CMP_SULE_S 5958 { 1097, 3, 1, 4, 1295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1097 = CMP_SULE_S_MMR6 5959 { 1098, 3, 1, 4, 1674, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1098 = CMP_SULT_D 5960 { 1099, 3, 1, 4, 1294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1099 = CMP_SULT_D_MMR6 5961 { 1100, 3, 1, 4, 1675, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1100 = CMP_SULT_S 5962 { 1101, 3, 1, 4, 1295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1101 = CMP_SULT_S_MMR6 5963 { 1102, 3, 1, 4, 1676, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1102 = CMP_SUN_D 5964 { 1103, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1103 = CMP_SUN_D_MMR6 5965 { 1104, 3, 1, 4, 1677, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1104 = CMP_SUN_S 5966 { 1105, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1105 = CMP_SUN_S_MMR6 5967 { 1106, 3, 1, 4, 554, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1106 = CMP_UEQ_D 5968 { 1107, 3, 1, 4, 1292, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1107 = CMP_UEQ_D_MMR6 5969 { 1108, 3, 1, 4, 555, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1108 = CMP_UEQ_S 5970 { 1109, 3, 1, 4, 1293, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1109 = CMP_UEQ_S_MMR6 5971 { 1110, 3, 1, 4, 564, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1110 = CMP_ULE_D 5972 { 1111, 3, 1, 4, 1292, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1111 = CMP_ULE_D_MMR6 5973 { 1112, 3, 1, 4, 565, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1112 = CMP_ULE_S 5974 { 1113, 3, 1, 4, 1293, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1113 = CMP_ULE_S_MMR6 5975 { 1114, 3, 1, 4, 560, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1114 = CMP_ULT_D 5976 { 1115, 3, 1, 4, 1292, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1115 = CMP_ULT_D_MMR6 5977 { 1116, 3, 1, 4, 561, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1116 = CMP_ULT_S 5978 { 1117, 3, 1, 4, 1293, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1117 = CMP_ULT_S_MMR6 5979 { 1118, 3, 1, 4, 552, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1118 = CMP_UN_D 5980 { 1119, 3, 1, 4, 1290, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1119 = CMP_UN_D_MMR6 5981 { 1120, 3, 1, 4, 553, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1120 = CMP_UN_S 5982 { 1121, 3, 1, 4, 1291, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1121 = CMP_UN_S_MMR6 5983 { 1122, 3, 1, 4, 681, 0, 0x6ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1122 = COPY_S_B 5984 { 1123, 3, 1, 4, 681, 0, 0x6ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1123 = COPY_S_D 5985 { 1124, 3, 1, 4, 681, 0, 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1124 = COPY_S_H 5986 { 1125, 3, 1, 4, 681, 0, 0x6ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1125 = COPY_S_W 5987 { 1126, 3, 1, 4, 680, 0, 0x6ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1126 = COPY_U_B 5988 { 1127, 3, 1, 4, 680, 0, 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1127 = COPY_U_H 5989 { 1128, 3, 1, 4, 680, 0, 0x6ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1128 = COPY_U_W 5990 { 1129, 3, 1, 4, 1182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1129 = CRC32B 5991 { 1130, 3, 1, 4, 1185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1130 = CRC32CB 5992 { 1131, 3, 1, 4, 1189, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1131 = CRC32CD 5993 { 1132, 3, 1, 4, 1186, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1132 = CRC32CH 5994 { 1133, 3, 1, 4, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1133 = CRC32CW 5995 { 1134, 3, 1, 4, 1188, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1134 = CRC32D 5996 { 1135, 3, 1, 4, 1183, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1135 = CRC32H 5997 { 1136, 3, 1, 4, 1184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1136 = CRC32W 5998 { 1137, 2, 1, 4, 677, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1137 = CTC1 5999 { 1138, 2, 1, 4, 1284, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1138 = CTC1_MM 6000 { 1139, 2, 1, 4, 1050, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1139 = CTC2_MM 6001 { 1140, 2, 0, 4, 524, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1140 = CTCMSA 6002 { 1141, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1141 = CVT_D32_S 6003 { 1142, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1142 = CVT_D32_S_MM 6004 { 1143, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1143 = CVT_D32_W 6005 { 1144, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1144 = CVT_D32_W_MM 6006 { 1145, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1145 = CVT_D64_L 6007 { 1146, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1146 = CVT_D64_S 6008 { 1147, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1147 = CVT_D64_S_MM 6009 { 1148, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1148 = CVT_D64_W 6010 { 1149, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1149 = CVT_D64_W_MM 6011 { 1150, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1150 = CVT_D_L_MMR6 6012 { 1151, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1151 = CVT_L_D64 6013 { 1152, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1152 = CVT_L_D64_MM 6014 { 1153, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1153 = CVT_L_D_MMR6 6015 { 1154, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1154 = CVT_L_S 6016 { 1155, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1155 = CVT_L_S_MM 6017 { 1156, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1156 = CVT_L_S_MMR6 6018 { 1157, 3, 1, 4, 631, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #1157 = CVT_PS_S64 6019 { 1158, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1158 = CVT_S_D32 6020 { 1159, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1159 = CVT_S_D32_MM 6021 { 1160, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1160 = CVT_S_D64 6022 { 1161, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1161 = CVT_S_D64_MM 6023 { 1162, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1162 = CVT_S_L 6024 { 1163, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1163 = CVT_S_L_MMR6 6025 { 1164, 2, 1, 4, 631, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1164 = CVT_S_PL64 6026 { 1165, 2, 1, 4, 631, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1165 = CVT_S_PU64 6027 { 1166, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1166 = CVT_S_W 6028 { 1167, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1167 = CVT_S_W_MM 6029 { 1168, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1168 = CVT_S_W_MMR6 6030 { 1169, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1169 = CVT_W_D32 6031 { 1170, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1170 = CVT_W_D32_MM 6032 { 1171, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1171 = CVT_W_D64 6033 { 1172, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1172 = CVT_W_D64_MM 6034 { 1173, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1173 = CVT_W_S 6035 { 1174, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1174 = CVT_W_S_MM 6036 { 1175, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1175 = CVT_W_S_MMR6 6037 { 1176, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1176 = C_EQ_D32 6038 { 1177, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1177 = C_EQ_D32_MM 6039 { 1178, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1178 = C_EQ_D64 6040 { 1179, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1179 = C_EQ_D64_MM 6041 { 1180, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1180 = C_EQ_S 6042 { 1181, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1181 = C_EQ_S_MM 6043 { 1182, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1182 = C_F_D32 6044 { 1183, 3, 1, 4, 1246, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1183 = C_F_D32_MM 6045 { 1184, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1184 = C_F_D64 6046 { 1185, 3, 1, 4, 1246, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1185 = C_F_D64_MM 6047 { 1186, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1186 = C_F_S 6048 { 1187, 3, 1, 4, 1247, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1187 = C_F_S_MM 6049 { 1188, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1188 = C_LE_D32 6050 { 1189, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1189 = C_LE_D32_MM 6051 { 1190, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1190 = C_LE_D64 6052 { 1191, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1191 = C_LE_D64_MM 6053 { 1192, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1192 = C_LE_S 6054 { 1193, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1193 = C_LE_S_MM 6055 { 1194, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1194 = C_LT_D32 6056 { 1195, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1195 = C_LT_D32_MM 6057 { 1196, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1196 = C_LT_D64 6058 { 1197, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1197 = C_LT_D64_MM 6059 { 1198, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1198 = C_LT_S 6060 { 1199, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1199 = C_LT_S_MM 6061 { 1200, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1200 = C_NGE_D32 6062 { 1201, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1201 = C_NGE_D32_MM 6063 { 1202, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1202 = C_NGE_D64 6064 { 1203, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1203 = C_NGE_D64_MM 6065 { 1204, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1204 = C_NGE_S 6066 { 1205, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1205 = C_NGE_S_MM 6067 { 1206, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1206 = C_NGLE_D32 6068 { 1207, 3, 1, 4, 1252, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1207 = C_NGLE_D32_MM 6069 { 1208, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1208 = C_NGLE_D64 6070 { 1209, 3, 1, 4, 1252, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1209 = C_NGLE_D64_MM 6071 { 1210, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1210 = C_NGLE_S 6072 { 1211, 3, 1, 4, 1253, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1211 = C_NGLE_S_MM 6073 { 1212, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1212 = C_NGL_D32 6074 { 1213, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1213 = C_NGL_D32_MM 6075 { 1214, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1214 = C_NGL_D64 6076 { 1215, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1215 = C_NGL_D64_MM 6077 { 1216, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1216 = C_NGL_S 6078 { 1217, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1217 = C_NGL_S_MM 6079 { 1218, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1218 = C_NGT_D32 6080 { 1219, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1219 = C_NGT_D32_MM 6081 { 1220, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1220 = C_NGT_D64 6082 { 1221, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1221 = C_NGT_D64_MM 6083 { 1222, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1222 = C_NGT_S 6084 { 1223, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1223 = C_NGT_S_MM 6085 { 1224, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1224 = C_OLE_D32 6086 { 1225, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1225 = C_OLE_D32_MM 6087 { 1226, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1226 = C_OLE_D64 6088 { 1227, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1227 = C_OLE_D64_MM 6089 { 1228, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1228 = C_OLE_S 6090 { 1229, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1229 = C_OLE_S_MM 6091 { 1230, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1230 = C_OLT_D32 6092 { 1231, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1231 = C_OLT_D32_MM 6093 { 1232, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1232 = C_OLT_D64 6094 { 1233, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1233 = C_OLT_D64_MM 6095 { 1234, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1234 = C_OLT_S 6096 { 1235, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1235 = C_OLT_S_MM 6097 { 1236, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1236 = C_SEQ_D32 6098 { 1237, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1237 = C_SEQ_D32_MM 6099 { 1238, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1238 = C_SEQ_D64 6100 { 1239, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1239 = C_SEQ_D64_MM 6101 { 1240, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1240 = C_SEQ_S 6102 { 1241, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1241 = C_SEQ_S_MM 6103 { 1242, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1242 = C_SF_D32 6104 { 1243, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1243 = C_SF_D32_MM 6105 { 1244, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1244 = C_SF_D64 6106 { 1245, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1245 = C_SF_D64_MM 6107 { 1246, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1246 = C_SF_S 6108 { 1247, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1247 = C_SF_S_MM 6109 { 1248, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1248 = C_UEQ_D32 6110 { 1249, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1249 = C_UEQ_D32_MM 6111 { 1250, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1250 = C_UEQ_D64 6112 { 1251, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1251 = C_UEQ_D64_MM 6113 { 1252, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1252 = C_UEQ_S 6114 { 1253, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1253 = C_UEQ_S_MM 6115 { 1254, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1254 = C_ULE_D32 6116 { 1255, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1255 = C_ULE_D32_MM 6117 { 1256, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1256 = C_ULE_D64 6118 { 1257, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1257 = C_ULE_D64_MM 6119 { 1258, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1258 = C_ULE_S 6120 { 1259, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1259 = C_ULE_S_MM 6121 { 1260, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1260 = C_ULT_D32 6122 { 1261, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1261 = C_ULT_D32_MM 6123 { 1262, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1262 = C_ULT_D64 6124 { 1263, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1263 = C_ULT_D64_MM 6125 { 1264, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1264 = C_ULT_S 6126 { 1265, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1265 = C_ULT_S_MM 6127 { 1266, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1266 = C_UN_D32 6128 { 1267, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1267 = C_UN_D32_MM 6129 { 1268, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1268 = C_UN_D64 6130 { 1269, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1269 = C_UN_D64_MM 6131 { 1270, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1270 = C_UN_S 6132 { 1271, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1271 = C_UN_S_MM 6133 { 1272, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo121, -1 ,nullptr }, // Inst #1272 = CmpRxRy16 6134 { 1273, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #1273 = CmpiRxImm16 6135 { 1274, 2, 0, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #1274 = CmpiRxImmX16 6136 { 1275, 3, 1, 4, 808, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1275 = DADD 6137 { 1276, 3, 1, 4, 809, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1276 = DADDi 6138 { 1277, 3, 1, 4, 810, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1277 = DADDiu 6139 { 1278, 3, 1, 4, 811, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1278 = DADDu 6140 { 1279, 3, 1, 4, 837, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1279 = DAHI 6141 { 1280, 4, 1, 4, 836, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1280 = DALIGN 6142 { 1281, 3, 1, 4, 838, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1281 = DATI 6143 { 1282, 3, 1, 4, 839, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1282 = DAUI 6144 { 1283, 2, 1, 4, 842, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1283 = DBITSWAP 6145 { 1284, 2, 1, 4, 812, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1284 = DCLO 6146 { 1285, 2, 1, 4, 840, 0, 0x6ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1285 = DCLO_R6 6147 { 1286, 2, 1, 4, 813, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1286 = DCLZ 6148 { 1287, 2, 1, 4, 841, 0, 0x6ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1287 = DCLZ_R6 6149 { 1288, 3, 1, 4, 907, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1288 = DDIV 6150 { 1289, 3, 1, 4, 909, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1289 = DDIVU 6151 { 1290, 0, 0, 4, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1290 = DERET 6152 { 1291, 0, 0, 4, 944, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1291 = DERET_MM 6153 { 1292, 0, 0, 4, 980, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1292 = DERET_MMR6 6154 { 1293, 4, 1, 4, 814, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1293 = DEXT 6155 { 1294, 4, 1, 4, 799, 0, 0x1ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1294 = DEXT64_32 6156 { 1295, 4, 1, 4, 814, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1295 = DEXTM 6157 { 1296, 4, 1, 4, 814, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1296 = DEXTU 6158 { 1297, 1, 1, 4, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1297 = DI 6159 { 1298, 5, 1, 4, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1298 = DINS 6160 { 1299, 5, 1, 4, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1299 = DINSM 6161 { 1300, 5, 1, 4, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1300 = DINSU 6162 { 1301, 3, 1, 4, 479, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1301 = DIV 6163 { 1302, 3, 1, 4, 480, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1302 = DIVU 6164 { 1303, 3, 1, 4, 890, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1303 = DIVU_MMR6 6165 { 1304, 3, 1, 4, 891, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1304 = DIV_MMR6 6166 { 1305, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1305 = DIV_S_B 6167 { 1306, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1306 = DIV_S_D 6168 { 1307, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1307 = DIV_S_H 6169 { 1308, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1308 = DIV_S_W 6170 { 1309, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1309 = DIV_U_B 6171 { 1310, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1310 = DIV_U_D 6172 { 1311, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1311 = DIV_U_H 6173 { 1312, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1312 = DIV_U_W 6174 { 1313, 1, 1, 4, 1023, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1313 = DI_MM 6175 { 1314, 1, 1, 4, 1040, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1314 = DI_MMR6 6176 { 1315, 4, 1, 4, 843, 0, 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1315 = DLSA 6177 { 1316, 4, 1, 4, 843, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1316 = DLSA_R6 6178 { 1317, 3, 1, 4, 1045, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1317 = DMFC0 6179 { 1318, 2, 1, 4, 1329, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1318 = DMFC1 6180 { 1319, 3, 1, 4, 1047, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1319 = DMFC2 6181 { 1320, 2, 2, 4, 1193, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1320 = DMFC2_OCTEON 6182 { 1321, 3, 1, 4, 1059, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1321 = DMFGC0 6183 { 1322, 3, 1, 4, 908, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1322 = DMOD 6184 { 1323, 3, 1, 4, 910, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1323 = DMODU 6185 { 1324, 1, 1, 4, 1051, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1324 = DMT 6186 { 1325, 3, 1, 4, 1046, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1325 = DMTC0 6187 { 1326, 2, 1, 4, 1330, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #1326 = DMTC1 6188 { 1327, 3, 1, 4, 1048, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1327 = DMTC2 6189 { 1328, 2, 2, 4, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1328 = DMTC2_OCTEON 6190 { 1329, 3, 1, 4, 1060, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1329 = DMTGC0 6191 { 1330, 3, 1, 4, 904, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1330 = DMUH 6192 { 1331, 3, 1, 4, 905, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1331 = DMUHU 6193 { 1332, 3, 1, 4, 1201, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList11, OperandInfo64, -1 ,nullptr }, // Inst #1332 = DMUL 6194 { 1333, 2, 0, 4, 894, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo113, -1 ,nullptr }, // Inst #1333 = DMULT 6195 { 1334, 2, 0, 4, 895, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo113, -1 ,nullptr }, // Inst #1334 = DMULTu 6196 { 1335, 3, 1, 4, 893, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1335 = DMULU 6197 { 1336, 3, 1, 4, 906, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1336 = DMUL_R6 6198 { 1337, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1337 = DOTP_S_D 6199 { 1338, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1338 = DOTP_S_H 6200 { 1339, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1339 = DOTP_S_W 6201 { 1340, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1340 = DOTP_U_D 6202 { 1341, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1341 = DOTP_U_H 6203 { 1342, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1342 = DOTP_U_W 6204 { 1343, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1343 = DPADD_S_D 6205 { 1344, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1344 = DPADD_S_H 6206 { 1345, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1345 = DPADD_S_W 6207 { 1346, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1346 = DPADD_U_D 6208 { 1347, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1347 = DPADD_U_H 6209 { 1348, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1348 = DPADD_U_W 6210 { 1349, 4, 1, 4, 1464, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1349 = DPAQX_SA_W_PH 6211 { 1350, 4, 1, 4, 1628, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1350 = DPAQX_SA_W_PH_MMR2 6212 { 1351, 4, 1, 4, 1465, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1351 = DPAQX_S_W_PH 6213 { 1352, 4, 1, 4, 1629, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1352 = DPAQX_S_W_PH_MMR2 6214 { 1353, 4, 1, 4, 1366, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1353 = DPAQ_SA_L_W 6215 { 1354, 4, 1, 4, 1517, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1354 = DPAQ_SA_L_W_MM 6216 { 1355, 4, 1, 4, 1367, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1355 = DPAQ_S_W_PH 6217 { 1356, 4, 1, 4, 1518, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1356 = DPAQ_S_W_PH_MM 6218 { 1357, 4, 1, 4, 1368, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1357 = DPAU_H_QBL 6219 { 1358, 4, 1, 4, 1519, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1358 = DPAU_H_QBL_MM 6220 { 1359, 4, 1, 4, 1369, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1359 = DPAU_H_QBR 6221 { 1360, 4, 1, 4, 1520, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1360 = DPAU_H_QBR_MM 6222 { 1361, 4, 1, 4, 1466, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1361 = DPAX_W_PH 6223 { 1362, 4, 1, 4, 1630, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1362 = DPAX_W_PH_MMR2 6224 { 1363, 4, 1, 4, 1463, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1363 = DPA_W_PH 6225 { 1364, 4, 1, 4, 1627, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1364 = DPA_W_PH_MMR2 6226 { 1365, 2, 1, 4, 1195, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1365 = DPOP 6227 { 1366, 4, 1, 4, 1469, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1366 = DPSQX_SA_W_PH 6228 { 1367, 4, 1, 4, 1633, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1367 = DPSQX_SA_W_PH_MMR2 6229 { 1368, 4, 1, 4, 1468, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1368 = DPSQX_S_W_PH 6230 { 1369, 4, 1, 4, 1632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1369 = DPSQX_S_W_PH_MMR2 6231 { 1370, 4, 1, 4, 1370, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1370 = DPSQ_SA_L_W 6232 { 1371, 4, 1, 4, 1521, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1371 = DPSQ_SA_L_W_MM 6233 { 1372, 4, 1, 4, 1371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1372 = DPSQ_S_W_PH 6234 { 1373, 4, 1, 4, 1522, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1373 = DPSQ_S_W_PH_MM 6235 { 1374, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1374 = DPSUB_S_D 6236 { 1375, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1375 = DPSUB_S_H 6237 { 1376, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1376 = DPSUB_S_W 6238 { 1377, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1377 = DPSUB_U_D 6239 { 1378, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1378 = DPSUB_U_H 6240 { 1379, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1379 = DPSUB_U_W 6241 { 1380, 4, 1, 4, 1372, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1380 = DPSU_H_QBL 6242 { 1381, 4, 1, 4, 1523, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1381 = DPSU_H_QBL_MM 6243 { 1382, 4, 1, 4, 1373, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1382 = DPSU_H_QBR 6244 { 1383, 4, 1, 4, 1524, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1383 = DPSU_H_QBR_MM 6245 { 1384, 4, 1, 4, 1470, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1384 = DPSX_W_PH 6246 { 1385, 4, 1, 4, 1634, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1385 = DPSX_W_PH_MMR2 6247 { 1386, 4, 1, 4, 1467, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1386 = DPS_W_PH 6248 { 1387, 4, 1, 4, 1631, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1387 = DPS_W_PH_MMR2 6249 { 1388, 3, 1, 4, 816, 0, 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1388 = DROTR 6250 { 1389, 3, 1, 4, 817, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1389 = DROTR32 6251 { 1390, 3, 1, 4, 818, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1390 = DROTRV 6252 { 1391, 2, 1, 4, 819, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1391 = DSBH 6253 { 1392, 2, 0, 4, 896, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo113, -1 ,nullptr }, // Inst #1392 = DSDIV 6254 { 1393, 2, 1, 4, 820, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1393 = DSHD 6255 { 1394, 3, 1, 4, 821, 0, 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1394 = DSLL 6256 { 1395, 3, 1, 4, 822, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1395 = DSLL32 6257 { 1396, 2, 1, 4, 800, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #1396 = DSLL64_32 6258 { 1397, 3, 1, 4, 823, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1397 = DSLLV 6259 { 1398, 3, 1, 4, 824, 0, 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1398 = DSRA 6260 { 1399, 3, 1, 4, 825, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1399 = DSRA32 6261 { 1400, 3, 1, 4, 826, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1400 = DSRAV 6262 { 1401, 3, 1, 4, 827, 0, 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1401 = DSRL 6263 { 1402, 3, 1, 4, 828, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1402 = DSRL32 6264 { 1403, 3, 1, 4, 829, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1403 = DSRLV 6265 { 1404, 3, 1, 4, 830, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1404 = DSUB 6266 { 1405, 3, 1, 4, 831, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1405 = DSUBu 6267 { 1406, 2, 0, 4, 897, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo113, -1 ,nullptr }, // Inst #1406 = DUDIV 6268 { 1407, 1, 1, 4, 1018, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1407 = DVP 6269 { 1408, 1, 1, 4, 1052, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1408 = DVPE 6270 { 1409, 1, 1, 4, 1039, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1409 = DVP_MMR6 6271 { 1410, 2, 0, 2, 868, 0, 0x0ULL, nullptr, ImplicitList6, OperandInfo121, -1 ,nullptr }, // Inst #1410 = DivRxRy16 6272 { 1411, 2, 0, 2, 869, 0, 0x0ULL, nullptr, ImplicitList6, OperandInfo121, -1 ,nullptr }, // Inst #1411 = DivuRxRy16 6273 { 1412, 0, 0, 4, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1412 = EHB 6274 { 1413, 0, 0, 4, 1025, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1413 = EHB_MM 6275 { 1414, 0, 0, 4, 1042, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1414 = EHB_MMR6 6276 { 1415, 1, 1, 4, 472, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1415 = EI 6277 { 1416, 1, 1, 4, 1024, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1416 = EI_MM 6278 { 1417, 1, 1, 4, 1041, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1417 = EI_MMR6 6279 { 1418, 1, 1, 4, 1053, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1418 = EMT 6280 { 1419, 0, 0, 4, 376, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1419 = ERET 6281 { 1420, 0, 0, 4, 378, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1420 = ERETNC 6282 { 1421, 0, 0, 4, 981, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1421 = ERETNC_MMR6 6283 { 1422, 0, 0, 4, 945, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1422 = ERET_MM 6284 { 1423, 0, 0, 4, 983, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1423 = ERET_MMR6 6285 { 1424, 1, 1, 4, 1017, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1424 = EVP 6286 { 1425, 1, 1, 4, 1054, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1425 = EVPE 6287 { 1426, 1, 1, 4, 1038, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1426 = EVP_MMR6 6288 { 1427, 4, 1, 4, 489, 0, 0x1ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1427 = EXT 6289 { 1428, 3, 1, 4, 1377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo236, -1 ,nullptr }, // Inst #1428 = EXTP 6290 { 1429, 3, 1, 4, 1375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo236, -1 ,nullptr }, // Inst #1429 = EXTPDP 6291 { 1430, 3, 1, 4, 1374, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo237, -1 ,nullptr }, // Inst #1430 = EXTPDPV 6292 { 1431, 3, 1, 4, 1525, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo237, -1 ,nullptr }, // Inst #1431 = EXTPDPV_MM 6293 { 1432, 3, 1, 4, 1526, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo236, -1 ,nullptr }, // Inst #1432 = EXTPDP_MM 6294 { 1433, 3, 1, 4, 1376, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo237, -1 ,nullptr }, // Inst #1433 = EXTPV 6295 { 1434, 3, 1, 4, 1527, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo237, -1 ,nullptr }, // Inst #1434 = EXTPV_MM 6296 { 1435, 3, 1, 4, 1528, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo236, -1 ,nullptr }, // Inst #1435 = EXTP_MM 6297 { 1436, 3, 1, 4, 1334, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1436 = EXTRV_RS_W 6298 { 1437, 3, 1, 4, 1529, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1437 = EXTRV_RS_W_MM 6299 { 1438, 3, 1, 4, 1335, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1438 = EXTRV_R_W 6300 { 1439, 3, 1, 4, 1530, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1439 = EXTRV_R_W_MM 6301 { 1440, 3, 1, 4, 1336, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1440 = EXTRV_S_H 6302 { 1441, 3, 1, 4, 1531, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1441 = EXTRV_S_H_MM 6303 { 1442, 3, 1, 4, 1337, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1442 = EXTRV_W 6304 { 1443, 3, 1, 4, 1532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1443 = EXTRV_W_MM 6305 { 1444, 3, 1, 4, 1338, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1444 = EXTR_RS_W 6306 { 1445, 3, 1, 4, 1533, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1445 = EXTR_RS_W_MM 6307 { 1446, 3, 1, 4, 1339, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1446 = EXTR_R_W 6308 { 1447, 3, 1, 4, 1534, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1447 = EXTR_R_W_MM 6309 { 1448, 3, 1, 4, 1340, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1448 = EXTR_S_H 6310 { 1449, 3, 1, 4, 1535, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1449 = EXTR_S_H_MM 6311 { 1450, 3, 1, 4, 1341, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1450 = EXTR_W 6312 { 1451, 3, 1, 4, 1536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1451 = EXTR_W_MM 6313 { 1452, 4, 1, 4, 1196, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1452 = EXTS 6314 { 1453, 4, 1, 4, 1196, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1453 = EXTS32 6315 { 1454, 4, 1, 4, 738, 0, 0x1ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1454 = EXT_MM 6316 { 1455, 4, 1, 4, 779, 0, 0x1ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1455 = EXT_MMR6 6317 { 1456, 2, 1, 4, 525, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1456 = FABS_D32 6318 { 1457, 2, 1, 4, 1260, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1457 = FABS_D32_MM 6319 { 1458, 2, 1, 4, 525, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1458 = FABS_D64 6320 { 1459, 2, 1, 4, 1260, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1459 = FABS_D64_MM 6321 { 1460, 2, 1, 4, 525, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1460 = FABS_S 6322 { 1461, 2, 1, 4, 1261, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1461 = FABS_S_MM 6323 { 1462, 3, 1, 4, 655, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1462 = FADD_D 6324 { 1463, 3, 1, 4, 623, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1463 = FADD_D32 6325 { 1464, 3, 1, 4, 1263, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1464 = FADD_D32_MM 6326 { 1465, 3, 1, 4, 623, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1465 = FADD_D64 6327 { 1466, 3, 1, 4, 1263, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1466 = FADD_D64_MM 6328 { 1467, 3, 1, 4, 624, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1467 = FADD_S 6329 { 1468, 3, 1, 4, 1264, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1468 = FADD_S_MM 6330 { 1469, 3, 1, 4, 1304, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1469 = FADD_S_MMR6 6331 { 1470, 3, 1, 4, 655, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1470 = FADD_W 6332 { 1471, 3, 1, 4, 572, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1471 = FCAF_D 6333 { 1472, 3, 1, 4, 572, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1472 = FCAF_W 6334 { 1473, 3, 1, 4, 573, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1473 = FCEQ_D 6335 { 1474, 3, 1, 4, 573, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1474 = FCEQ_W 6336 { 1475, 2, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1475 = FCLASS_D 6337 { 1476, 2, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1476 = FCLASS_W 6338 { 1477, 3, 1, 4, 574, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1477 = FCLE_D 6339 { 1478, 3, 1, 4, 574, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1478 = FCLE_W 6340 { 1479, 3, 1, 4, 575, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1479 = FCLT_D 6341 { 1480, 3, 1, 4, 575, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1480 = FCLT_W 6342 { 1481, 3, 0, 4, 634, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo242, -1 ,nullptr }, // Inst #1481 = FCMP_D32 6343 { 1482, 3, 0, 4, 1255, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo242, -1 ,nullptr }, // Inst #1482 = FCMP_D32_MM 6344 { 1483, 3, 0, 4, 634, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo243, -1 ,nullptr }, // Inst #1483 = FCMP_D64 6345 { 1484, 3, 0, 4, 635, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo244, -1 ,nullptr }, // Inst #1484 = FCMP_S32 6346 { 1485, 3, 0, 4, 1254, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo244, -1 ,nullptr }, // Inst #1485 = FCMP_S32_MM 6347 { 1486, 3, 1, 4, 576, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1486 = FCNE_D 6348 { 1487, 3, 1, 4, 576, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1487 = FCNE_W 6349 { 1488, 3, 1, 4, 577, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1488 = FCOR_D 6350 { 1489, 3, 1, 4, 577, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1489 = FCOR_W 6351 { 1490, 3, 1, 4, 578, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1490 = FCUEQ_D 6352 { 1491, 3, 1, 4, 578, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1491 = FCUEQ_W 6353 { 1492, 3, 1, 4, 579, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1492 = FCULE_D 6354 { 1493, 3, 1, 4, 579, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1493 = FCULE_W 6355 { 1494, 3, 1, 4, 580, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1494 = FCULT_D 6356 { 1495, 3, 1, 4, 580, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1495 = FCULT_W 6357 { 1496, 3, 1, 4, 581, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1496 = FCUNE_D 6358 { 1497, 3, 1, 4, 581, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1497 = FCUNE_W 6359 { 1498, 3, 1, 4, 582, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1498 = FCUN_D 6360 { 1499, 3, 1, 4, 582, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1499 = FCUN_W 6361 { 1500, 3, 1, 4, 651, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1500 = FDIV_D 6362 { 1501, 3, 1, 4, 639, 0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1501 = FDIV_D32 6363 { 1502, 3, 1, 4, 1274, 0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1502 = FDIV_D32_MM 6364 { 1503, 3, 1, 4, 639, 0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1503 = FDIV_D64 6365 { 1504, 3, 1, 4, 1274, 0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1504 = FDIV_D64_MM 6366 { 1505, 3, 1, 4, 638, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1505 = FDIV_S 6367 { 1506, 3, 1, 4, 1273, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1506 = FDIV_S_MM 6368 { 1507, 3, 1, 4, 1326, 0, 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1507 = FDIV_S_MMR6 6369 { 1508, 3, 1, 4, 650, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1508 = FDIV_W 6370 { 1509, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1509 = FEXDO_H 6371 { 1510, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1510 = FEXDO_W 6372 { 1511, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1511 = FEXP2_D 6373 { 1512, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1512 = FEXP2_W 6374 { 1513, 2, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1513 = FEXUPL_D 6375 { 1514, 2, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1514 = FEXUPL_W 6376 { 1515, 2, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1515 = FEXUPR_D 6377 { 1516, 2, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1516 = FEXUPR_W 6378 { 1517, 2, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1517 = FFINT_S_D 6379 { 1518, 2, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1518 = FFINT_S_W 6380 { 1519, 2, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1519 = FFINT_U_D 6381 { 1520, 2, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1520 = FFINT_U_W 6382 { 1521, 2, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1521 = FFQL_D 6383 { 1522, 2, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1522 = FFQL_W 6384 { 1523, 2, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1523 = FFQR_D 6385 { 1524, 2, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1524 = FFQR_W 6386 { 1525, 2, 1, 4, 539, 0, 0x6ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #1525 = FILL_B 6387 { 1526, 2, 1, 4, 539, 0, 0x6ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1526 = FILL_D 6388 { 1527, 2, 1, 4, 539, 0, 0x6ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1527 = FILL_H 6389 { 1528, 2, 1, 4, 539, 0, 0x6ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1528 = FILL_W 6390 { 1529, 2, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1529 = FLOG2_D 6391 { 1530, 2, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1530 = FLOG2_W 6392 { 1531, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1531 = FLOOR_L_D64 6393 { 1532, 2, 1, 4, 1299, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1532 = FLOOR_L_D_MMR6 6394 { 1533, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1533 = FLOOR_L_S 6395 { 1534, 2, 1, 4, 1299, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1534 = FLOOR_L_S_MMR6 6396 { 1535, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1535 = FLOOR_W_D32 6397 { 1536, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1536 = FLOOR_W_D64 6398 { 1537, 2, 1, 4, 1299, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1537 = FLOOR_W_D_MMR6 6399 { 1538, 2, 1, 4, 1237, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1538 = FLOOR_W_MM 6400 { 1539, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1539 = FLOOR_W_S 6401 { 1540, 2, 1, 4, 1237, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1540 = FLOOR_W_S_MM 6402 { 1541, 2, 1, 4, 1299, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1541 = FLOOR_W_S_MMR6 6403 { 1542, 4, 1, 4, 648, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1542 = FMADD_D 6404 { 1543, 4, 1, 4, 648, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1543 = FMADD_W 6405 { 1544, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1544 = FMAX_A_D 6406 { 1545, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1545 = FMAX_A_W 6407 { 1546, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1546 = FMAX_D 6408 { 1547, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1547 = FMAX_W 6409 { 1548, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1548 = FMIN_A_D 6410 { 1549, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1549 = FMIN_A_W 6411 { 1550, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1550 = FMIN_D 6412 { 1551, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1551 = FMIN_W 6413 { 1552, 2, 1, 4, 530, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1552 = FMOV_D32 6414 { 1553, 2, 1, 4, 1265, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1553 = FMOV_D32_MM 6415 { 1554, 2, 1, 4, 530, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1554 = FMOV_D64 6416 { 1555, 2, 1, 4, 1265, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1555 = FMOV_D64_MM 6417 { 1556, 2, 1, 4, 1325, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1556 = FMOV_D_MMR6 6418 { 1557, 2, 1, 4, 531, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1557 = FMOV_S 6419 { 1558, 2, 1, 4, 1266, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1558 = FMOV_S_MM 6420 { 1559, 2, 1, 4, 1322, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1559 = FMOV_S_MMR6 6421 { 1560, 4, 1, 4, 649, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1560 = FMSUB_D 6422 { 1561, 4, 1, 4, 649, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1561 = FMSUB_W 6423 { 1562, 3, 1, 4, 654, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1562 = FMUL_D 6424 { 1563, 3, 1, 4, 625, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1563 = FMUL_D32 6425 { 1564, 3, 1, 4, 1267, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1564 = FMUL_D32_MM 6426 { 1565, 3, 1, 4, 625, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1565 = FMUL_D64 6427 { 1566, 3, 1, 4, 1267, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1566 = FMUL_D64_MM 6428 { 1567, 3, 1, 4, 626, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1567 = FMUL_S 6429 { 1568, 3, 1, 4, 1268, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1568 = FMUL_S_MM 6430 { 1569, 3, 1, 4, 1323, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1569 = FMUL_S_MMR6 6431 { 1570, 3, 1, 4, 654, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1570 = FMUL_W 6432 { 1571, 2, 1, 4, 532, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1571 = FNEG_D32 6433 { 1572, 2, 1, 4, 1262, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1572 = FNEG_D32_MM 6434 { 1573, 2, 1, 4, 532, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1573 = FNEG_D64 6435 { 1574, 2, 1, 4, 1262, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1574 = FNEG_D64_MM 6436 { 1575, 2, 1, 4, 532, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1575 = FNEG_S 6437 { 1576, 2, 1, 4, 1262, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1576 = FNEG_S_MM 6438 { 1577, 2, 1, 4, 1289, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1577 = FNEG_S_MMR6 6439 { 1578, 3, 2, 4, 1058, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1578 = FORK 6440 { 1579, 2, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1579 = FRCP_D 6441 { 1580, 2, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1580 = FRCP_W 6442 { 1581, 2, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1581 = FRINT_D 6443 { 1582, 2, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1582 = FRINT_W 6444 { 1583, 2, 1, 4, 643, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1583 = FRSQRT_D 6445 { 1584, 2, 1, 4, 643, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1584 = FRSQRT_W 6446 { 1585, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1585 = FSAF_D 6447 { 1586, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1586 = FSAF_W 6448 { 1587, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1587 = FSEQ_D 6449 { 1588, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1588 = FSEQ_W 6450 { 1589, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1589 = FSLE_D 6451 { 1590, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1590 = FSLE_W 6452 { 1591, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1591 = FSLT_D 6453 { 1592, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1592 = FSLT_W 6454 { 1593, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1593 = FSNE_D 6455 { 1594, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1594 = FSNE_W 6456 { 1595, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1595 = FSOR_D 6457 { 1596, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1596 = FSOR_W 6458 { 1597, 2, 1, 4, 653, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1597 = FSQRT_D 6459 { 1598, 2, 1, 4, 641, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1598 = FSQRT_D32 6460 { 1599, 2, 1, 4, 1276, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1599 = FSQRT_D32_MM 6461 { 1600, 2, 1, 4, 641, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1600 = FSQRT_D64 6462 { 1601, 2, 1, 4, 1276, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1601 = FSQRT_D64_MM 6463 { 1602, 2, 1, 4, 640, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1602 = FSQRT_S 6464 { 1603, 2, 1, 4, 1275, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1603 = FSQRT_S_MM 6465 { 1604, 2, 1, 4, 652, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1604 = FSQRT_W 6466 { 1605, 3, 1, 4, 656, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1605 = FSUB_D 6467 { 1606, 3, 1, 4, 627, 0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1606 = FSUB_D32 6468 { 1607, 3, 1, 4, 1269, 0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1607 = FSUB_D32_MM 6469 { 1608, 3, 1, 4, 627, 0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1608 = FSUB_D64 6470 { 1609, 3, 1, 4, 1269, 0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1609 = FSUB_D64_MM 6471 { 1610, 3, 1, 4, 628, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1610 = FSUB_S 6472 { 1611, 3, 1, 4, 1270, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1611 = FSUB_S_MM 6473 { 1612, 3, 1, 4, 1324, 0, 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1612 = FSUB_S_MMR6 6474 { 1613, 3, 1, 4, 656, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1613 = FSUB_W 6475 { 1614, 3, 1, 4, 567, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1614 = FSUEQ_D 6476 { 1615, 3, 1, 4, 567, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1615 = FSUEQ_W 6477 { 1616, 3, 1, 4, 568, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1616 = FSULE_D 6478 { 1617, 3, 1, 4, 568, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1617 = FSULE_W 6479 { 1618, 3, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1618 = FSULT_D 6480 { 1619, 3, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1619 = FSULT_W 6481 { 1620, 3, 1, 4, 570, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1620 = FSUNE_D 6482 { 1621, 3, 1, 4, 570, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1621 = FSUNE_W 6483 { 1622, 3, 1, 4, 571, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1622 = FSUN_D 6484 { 1623, 3, 1, 4, 571, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1623 = FSUN_W 6485 { 1624, 2, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1624 = FTINT_S_D 6486 { 1625, 2, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1625 = FTINT_S_W 6487 { 1626, 2, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1626 = FTINT_U_D 6488 { 1627, 2, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1627 = FTINT_U_W 6489 { 1628, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1628 = FTQ_H 6490 { 1629, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1629 = FTQ_W 6491 { 1630, 2, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1630 = FTRUNC_S_D 6492 { 1631, 2, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1631 = FTRUNC_S_W 6493 { 1632, 2, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1632 = FTRUNC_U_D 6494 { 1633, 2, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1633 = FTRUNC_U_W 6495 { 1634, 1, 0, 4, 1081, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1634 = GINVI 6496 { 1635, 1, 0, 4, 1135, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1635 = GINVI_MMR6 6497 { 1636, 2, 0, 4, 1082, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1636 = GINVT 6498 { 1637, 2, 0, 4, 1136, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1637 = GINVT_MMR6 6499 { 1638, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1638 = HADD_S_D 6500 { 1639, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1639 = HADD_S_H 6501 { 1640, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1640 = HADD_S_W 6502 { 1641, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1641 = HADD_U_D 6503 { 1642, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1642 = HADD_U_H 6504 { 1643, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1643 = HADD_U_W 6505 { 1644, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1644 = HSUB_S_D 6506 { 1645, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1645 = HSUB_S_H 6507 { 1646, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1646 = HSUB_S_W 6508 { 1647, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1647 = HSUB_U_D 6509 { 1648, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1648 = HSUB_U_H 6510 { 1649, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1649 = HSUB_U_W 6511 { 1650, 1, 0, 4, 415, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1650 = HYPCALL 6512 { 1651, 1, 0, 4, 1061, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1651 = HYPCALL_MM 6513 { 1652, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1652 = ILVEV_B 6514 { 1653, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1653 = ILVEV_D 6515 { 1654, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1654 = ILVEV_H 6516 { 1655, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1655 = ILVEV_W 6517 { 1656, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1656 = ILVL_B 6518 { 1657, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1657 = ILVL_D 6519 { 1658, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1658 = ILVL_H 6520 { 1659, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1659 = ILVL_W 6521 { 1660, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1660 = ILVOD_B 6522 { 1661, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1661 = ILVOD_D 6523 { 1662, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1662 = ILVOD_H 6524 { 1663, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1663 = ILVOD_W 6525 { 1664, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1664 = ILVR_B 6526 { 1665, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1665 = ILVR_D 6527 { 1666, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1666 = ILVR_H 6528 { 1667, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1667 = ILVR_W 6529 { 1668, 5, 1, 4, 490, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1668 = INS 6530 { 1669, 4, 1, 4, 513, 0, 0x6ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1669 = INSERT_B 6531 { 1670, 4, 1, 4, 513, 0, 0x6ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1670 = INSERT_D 6532 { 1671, 4, 1, 4, 513, 0, 0x6ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #1671 = INSERT_H 6533 { 1672, 4, 1, 4, 513, 0, 0x6ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1672 = INSERT_W 6534 { 1673, 3, 1, 4, 1342, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList18, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1673 = INSV 6535 { 1674, 5, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1674 = INSVE_B 6536 { 1675, 5, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1675 = INSVE_D 6537 { 1676, 5, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #1676 = INSVE_H 6538 { 1677, 5, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1677 = INSVE_W 6539 { 1678, 3, 1, 4, 1537, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList18, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1678 = INSV_MM 6540 { 1679, 5, 1, 4, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1679 = INS_MM 6541 { 1680, 5, 1, 4, 780, 0, 0x1ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1680 = INS_MMR6 6542 { 1681, 1, 0, 4, 914, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1681 = J 6543 { 1682, 1, 0, 4, 401, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1682 = JAL 6544 { 1683, 2, 1, 4, 402, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #1683 = JALR 6545 { 1684, 1, 0, 2, 951, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #1684 = JALR16_MM 6546 { 1685, 2, 1, 4, 1004, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo113, -1 ,nullptr }, // Inst #1685 = JALR64 6547 { 1686, 1, 0, 2, 993, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #1686 = JALRC16_MMR6 6548 { 1687, 2, 1, 4, 994, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1687 = JALRC_HB_MMR6 6549 { 1688, 2, 1, 4, 995, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #1688 = JALRC_MMR6 6550 { 1689, 1, 0, 2, 952, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #1689 = JALRS16_MM 6551 { 1690, 2, 1, 4, 952, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #1690 = JALRS_MM 6552 { 1691, 2, 1, 4, 403, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1691 = JALR_HB 6553 { 1692, 2, 1, 4, 1005, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1692 = JALR_HB64 6554 { 1693, 2, 1, 4, 951, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #1693 = JALR_MM 6555 { 1694, 1, 0, 4, 953, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1694 = JALS_MM 6556 { 1695, 1, 0, 4, 404, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1695 = JALX 6557 { 1696, 1, 0, 4, 954, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1696 = JALX_MM 6558 { 1697, 1, 0, 4, 954, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1697 = JAL_MM 6559 { 1698, 2, 0, 4, 920, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo105, -1 ,nullptr }, // Inst #1698 = JIALC 6560 { 1699, 2, 0, 4, 1013, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo103, -1 ,nullptr }, // Inst #1699 = JIALC64 6561 { 1700, 2, 0, 4, 996, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo105, -1 ,nullptr }, // Inst #1700 = JIALC_MMR6 6562 { 1701, 2, 0, 4, 925, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo105, -1 ,nullptr }, // Inst #1701 = JIC 6563 { 1702, 2, 0, 4, 1011, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo103, -1 ,nullptr }, // Inst #1702 = JIC64 6564 { 1703, 2, 0, 4, 984, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo105, -1 ,nullptr }, // Inst #1703 = JIC_MMR6 6565 { 1704, 1, 0, 4, 915, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1704 = JR 6566 { 1705, 1, 0, 2, 946, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1705 = JR16_MM 6567 { 1706, 1, 0, 4, 1003, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1706 = JR64 6568 { 1707, 1, 0, 2, 985, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1707 = JRADDIUSP 6569 { 1708, 1, 0, 2, 986, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1708 = JRC16_MM 6570 { 1709, 1, 0, 2, 987, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1709 = JRC16_MMR6 6571 { 1710, 1, 0, 2, 985, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1710 = JRCADDIUSP_MMR6 6572 { 1711, 1, 0, 4, 381, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1711 = JR_HB 6573 { 1712, 1, 0, 4, 1006, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1712 = JR_HB64 6574 { 1713, 1, 0, 4, 1014, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1713 = JR_HB64_R6 6575 { 1714, 1, 0, 4, 926, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1714 = JR_HB_R6 6576 { 1715, 1, 0, 4, 946, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1715 = JR_MM 6577 { 1716, 1, 0, 4, 947, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1716 = J_MM 6578 { 1717, 1, 0, 6, 933, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1717 = Jal16 6579 { 1718, 1, 0, 6, 933, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1718 = JalB16 6580 { 1719, 0, 0, 2, 931, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1719 = JrRa16 6581 { 1720, 0, 0, 2, 931, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1720 = JrcRa16 6582 { 1721, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1721 = JrcRx16 6583 { 1722, 1, 0, 2, 934, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo263, -1 ,nullptr }, // Inst #1722 = JumpLinkReg16 6584 { 1723, 3, 1, 4, 426, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1723 = LB 6585 { 1724, 3, 1, 4, 1158, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1724 = LB64 6586 { 1725, 3, 1, 4, 436, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1725 = LBE 6587 { 1726, 3, 1, 4, 1083, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1726 = LBE_MM 6588 { 1727, 3, 1, 2, 1110, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1727 = LBU16_MM 6589 { 1728, 3, 1, 4, 1378, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1728 = LBUX 6590 { 1729, 3, 1, 4, 1538, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1729 = LBUX_MM 6591 { 1730, 3, 1, 4, 1137, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1730 = LBU_MMR6 6592 { 1731, 3, 1, 4, 1111, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1731 = LB_MM 6593 { 1732, 3, 1, 4, 1138, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1732 = LB_MMR6 6594 { 1733, 3, 1, 4, 427, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1733 = LBu 6595 { 1734, 3, 1, 4, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1734 = LBu64 6596 { 1735, 3, 1, 4, 437, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1735 = LBuE 6597 { 1736, 3, 1, 4, 1084, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1736 = LBuE_MM 6598 { 1737, 3, 1, 4, 1110, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1737 = LBu_MM 6599 { 1738, 3, 1, 4, 1155, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1738 = LD 6600 { 1739, 3, 1, 4, 702, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1739 = LDC1 6601 { 1740, 3, 1, 4, 702, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1740 = LDC164 6602 { 1741, 3, 1, 4, 1328, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1741 = LDC1_D64_MMR6 6603 { 1742, 3, 1, 4, 1285, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1742 = LDC1_MM 6604 { 1743, 3, 1, 4, 434, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1743 = LDC2 6605 { 1744, 3, 1, 4, 1139, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1744 = LDC2_MMR6 6606 { 1745, 3, 1, 4, 1073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1745 = LDC2_R6 6607 { 1746, 3, 1, 4, 435, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #1746 = LDC3 6608 { 1747, 2, 1, 4, 542, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #1747 = LDI_B 6609 { 1748, 2, 1, 4, 542, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #1748 = LDI_D 6610 { 1749, 2, 1, 4, 542, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1749 = LDI_H 6611 { 1750, 2, 1, 4, 542, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #1750 = LDI_W 6612 { 1751, 4, 1, 4, 1165, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1751 = LDL 6613 { 1752, 2, 1, 4, 1177, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1752 = LDPC 6614 { 1753, 4, 1, 4, 1166, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1753 = LDR 6615 { 1754, 3, 1, 4, 703, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1754 = LDXC1 6616 { 1755, 3, 1, 4, 703, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #1755 = LDXC164 6617 { 1756, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #1756 = LD_B 6618 { 1757, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #1757 = LD_D 6619 { 1758, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1758 = LD_H 6620 { 1759, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1759 = LD_W 6621 { 1760, 3, 1, 4, 716, 0, 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1760 = LEA_ADDiu 6622 { 1761, 3, 1, 4, 832, 0, 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1761 = LEA_ADDiu64 6623 { 1762, 3, 1, 4, 730, 0, 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1762 = LEA_ADDiu_MM 6624 { 1763, 3, 1, 4, 428, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1763 = LH 6625 { 1764, 3, 1, 4, 1160, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1764 = LH64 6626 { 1765, 3, 1, 4, 438, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1765 = LHE 6627 { 1766, 3, 1, 4, 1085, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1766 = LHE_MM 6628 { 1767, 3, 1, 2, 1112, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1767 = LHU16_MM 6629 { 1768, 3, 1, 4, 1379, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1768 = LHX 6630 { 1769, 3, 1, 4, 1539, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1769 = LHX_MM 6631 { 1770, 3, 1, 4, 1113, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1770 = LH_MM 6632 { 1771, 3, 1, 4, 429, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1771 = LHu 6633 { 1772, 3, 1, 4, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1772 = LHu64 6634 { 1773, 3, 1, 4, 439, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1773 = LHuE 6635 { 1774, 3, 1, 4, 1086, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1774 = LHuE_MM 6636 { 1775, 3, 1, 4, 1112, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1775 = LHu_MM 6637 { 1776, 2, 1, 2, 740, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1776 = LI16_MM 6638 { 1777, 2, 1, 2, 781, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1777 = LI16_MMR6 6639 { 1778, 3, 1, 4, 431, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1778 = LL 6640 { 1779, 3, 1, 4, 1156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1779 = LL64 6641 { 1780, 3, 1, 4, 1179, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1780 = LL64_R6 6642 { 1781, 3, 1, 4, 1156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1781 = LLD 6643 { 1782, 3, 1, 4, 1178, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1782 = LLD_R6 6644 { 1783, 3, 1, 4, 441, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1783 = LLE 6645 { 1784, 3, 1, 4, 1090, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1784 = LLE_MM 6646 { 1785, 3, 1, 4, 1114, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1785 = LL_MM 6647 { 1786, 3, 1, 4, 1140, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1786 = LL_MMR6 6648 { 1787, 3, 1, 4, 1074, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1787 = LL_R6 6649 { 1788, 4, 1, 4, 508, 0, 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #1788 = LSA 6650 { 1789, 4, 1, 4, 782, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #1789 = LSA_MMR6 6651 { 1790, 4, 1, 4, 725, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #1790 = LSA_R6 6652 { 1791, 2, 1, 4, 783, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1791 = LUI_MMR6 6653 { 1792, 3, 1, 4, 706, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1792 = LUXC1 6654 { 1793, 3, 1, 4, 706, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #1793 = LUXC164 6655 { 1794, 3, 1, 4, 1286, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #1794 = LUXC1_MM 6656 { 1795, 2, 1, 4, 360, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1795 = LUi 6657 { 1796, 2, 1, 4, 833, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1796 = LUi64 6658 { 1797, 2, 1, 4, 741, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1797 = LUi_MM 6659 { 1798, 3, 1, 4, 430, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1798 = LW 6660 { 1799, 3, 1, 2, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1799 = LW16_MM 6661 { 1800, 3, 1, 4, 1162, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1800 = LW64 6662 { 1801, 3, 1, 4, 704, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1801 = LWC1 6663 { 1802, 3, 1, 4, 1287, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1802 = LWC1_MM 6664 { 1803, 3, 1, 4, 432, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1803 = LWC2 6665 { 1804, 3, 1, 4, 1142, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1804 = LWC2_MMR6 6666 { 1805, 3, 1, 4, 1075, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1805 = LWC2_R6 6667 { 1806, 3, 1, 4, 433, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #1806 = LWC3 6668 { 1807, 3, 1, 4, 1332, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1807 = LWDSP 6669 { 1808, 3, 1, 4, 1495, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1808 = LWDSP_MM 6670 { 1809, 3, 1, 4, 440, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1809 = LWE 6671 { 1810, 3, 1, 4, 1087, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1810 = LWE_MM 6672 { 1811, 3, 1, 2, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1811 = LWGP_MM 6673 { 1812, 4, 1, 4, 443, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1812 = LWL 6674 { 1813, 4, 1, 4, 1163, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1813 = LWL64 6675 { 1814, 4, 1, 4, 445, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1814 = LWLE 6676 { 1815, 4, 1, 4, 1088, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1815 = LWLE_MM 6677 { 1816, 4, 1, 4, 1116, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1816 = LWL_MM 6678 { 1817, 3, 1, 2, 1117, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1817 = LWM16_MM 6679 { 1818, 3, 1, 2, 1141, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1818 = LWM16_MMR6 6680 { 1819, 3, 1, 4, 1117, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1819 = LWM32_MM 6681 { 1820, 2, 1, 4, 442, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1820 = LWPC 6682 { 1821, 2, 1, 4, 1143, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1821 = LWPC_MMR6 6683 { 1822, 4, 2, 4, 1118, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #1822 = LWP_MM 6684 { 1823, 4, 1, 4, 444, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1823 = LWR 6685 { 1824, 4, 1, 4, 1164, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1824 = LWR64 6686 { 1825, 4, 1, 4, 446, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1825 = LWRE 6687 { 1826, 4, 1, 4, 1089, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1826 = LWRE_MM 6688 { 1827, 4, 1, 4, 1119, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1827 = LWR_MM 6689 { 1828, 3, 1, 2, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #1828 = LWSP_MM 6690 { 1829, 2, 1, 4, 1176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1829 = LWUPC 6691 { 1830, 3, 1, 4, 1120, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1830 = LWU_MM 6692 { 1831, 3, 1, 4, 1380, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1831 = LWX 6693 { 1832, 3, 1, 4, 705, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #1832 = LWXC1 6694 { 1833, 3, 1, 4, 1288, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #1833 = LWXC1_MM 6695 { 1834, 3, 1, 4, 1121, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1834 = LWXS_MM 6696 { 1835, 3, 1, 4, 1540, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1835 = LWX_MM 6697 { 1836, 3, 1, 4, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1836 = LW_MM 6698 { 1837, 3, 1, 4, 1144, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1837 = LW_MMR6 6699 { 1838, 3, 1, 4, 1157, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1838 = LWu 6700 { 1839, 3, 1, 4, 1101, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1839 = LbRxRyOffMemX16 6701 { 1840, 3, 1, 4, 1102, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1840 = LbuRxRyOffMemX16 6702 { 1841, 3, 1, 4, 1103, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1841 = LhRxRyOffMemX16 6703 { 1842, 3, 1, 4, 1104, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1842 = LhuRxRyOffMemX16 6704 { 1843, 2, 1, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1843 = LiRxImm16 6705 { 1844, 2, 1, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1844 = LiRxImmAlignX16 6706 { 1845, 2, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1845 = LiRxImmX16 6707 { 1846, 3, 1, 2, 1105, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #1846 = LwRxPcTcp16 6708 { 1847, 3, 1, 4, 1105, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #1847 = LwRxPcTcpX16 6709 { 1848, 3, 1, 4, 1105, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1848 = LwRxRyOffMemX16 6710 { 1849, 3, 1, 4, 1105, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1849 = LwRxSpImmX16 6711 { 1850, 2, 0, 4, 845, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #1850 = MADD 6712 { 1851, 4, 1, 4, 1225, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1851 = MADDF_D 6713 { 1852, 4, 1, 4, 1318, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1852 = MADDF_D_MMR6 6714 { 1853, 4, 1, 4, 1223, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1853 = MADDF_S 6715 { 1854, 4, 1, 4, 1319, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1854 = MADDF_S_MMR6 6716 { 1855, 4, 1, 4, 663, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #1855 = MADDR_Q_H 6717 { 1856, 4, 1, 4, 663, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1856 = MADDR_Q_W 6718 { 1857, 2, 0, 4, 846, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #1857 = MADDU 6719 { 1858, 4, 1, 4, 1381, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1858 = MADDU_DSP 6720 { 1859, 4, 1, 4, 1541, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1859 = MADDU_DSP_MM 6721 { 1860, 2, 0, 4, 873, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #1860 = MADDU_MM 6722 { 1861, 4, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1861 = MADDV_B 6723 { 1862, 4, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1862 = MADDV_D 6724 { 1863, 4, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #1863 = MADDV_H 6725 { 1864, 4, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1864 = MADDV_W 6726 { 1865, 4, 1, 4, 669, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1865 = MADD_D32 6727 { 1866, 4, 1, 4, 1243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1866 = MADD_D32_MM 6728 { 1867, 4, 1, 4, 669, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1867 = MADD_D64 6729 { 1868, 4, 1, 4, 1382, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1868 = MADD_DSP 6730 { 1869, 4, 1, 4, 1542, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1869 = MADD_DSP_MM 6731 { 1870, 2, 0, 4, 872, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #1870 = MADD_MM 6732 { 1871, 4, 1, 4, 664, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #1871 = MADD_Q_H 6733 { 1872, 4, 1, 4, 664, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1872 = MADD_Q_W 6734 { 1873, 4, 1, 4, 670, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1873 = MADD_S 6735 { 1874, 4, 1, 4, 1242, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1874 = MADD_S_MM 6736 { 1875, 4, 1, 4, 1383, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1875 = MAQ_SA_W_PHL 6737 { 1876, 4, 1, 4, 1543, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1876 = MAQ_SA_W_PHL_MM 6738 { 1877, 4, 1, 4, 1384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1877 = MAQ_SA_W_PHR 6739 { 1878, 4, 1, 4, 1544, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1878 = MAQ_SA_W_PHR_MM 6740 { 1879, 4, 1, 4, 1385, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1879 = MAQ_S_W_PHL 6741 { 1880, 4, 1, 4, 1545, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1880 = MAQ_S_W_PHL_MM 6742 { 1881, 4, 1, 4, 1386, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1881 = MAQ_S_W_PHR 6743 { 1882, 4, 1, 4, 1546, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1882 = MAQ_S_W_PHR_MM 6744 { 1883, 3, 1, 4, 1213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1883 = MAXA_D 6745 { 1884, 3, 1, 4, 1309, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1884 = MAXA_D_MMR6 6746 { 1885, 3, 1, 4, 1212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1885 = MAXA_S 6747 { 1886, 3, 1, 4, 1310, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1886 = MAXA_S_MMR6 6748 { 1887, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1887 = MAXI_S_B 6749 { 1888, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1888 = MAXI_S_D 6750 { 1889, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1889 = MAXI_S_H 6751 { 1890, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1890 = MAXI_S_W 6752 { 1891, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1891 = MAXI_U_B 6753 { 1892, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1892 = MAXI_U_D 6754 { 1893, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1893 = MAXI_U_H 6755 { 1894, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1894 = MAXI_U_W 6756 { 1895, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1895 = MAX_A_B 6757 { 1896, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1896 = MAX_A_D 6758 { 1897, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1897 = MAX_A_H 6759 { 1898, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1898 = MAX_A_W 6760 { 1899, 3, 1, 4, 1213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1899 = MAX_D 6761 { 1900, 3, 1, 4, 1305, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1900 = MAX_D_MMR6 6762 { 1901, 3, 1, 4, 1212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1901 = MAX_S 6763 { 1902, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1902 = MAX_S_B 6764 { 1903, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1903 = MAX_S_D 6765 { 1904, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1904 = MAX_S_H 6766 { 1905, 3, 1, 4, 1306, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1905 = MAX_S_MMR6 6767 { 1906, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1906 = MAX_S_W 6768 { 1907, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1907 = MAX_U_B 6769 { 1908, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1908 = MAX_U_D 6770 { 1909, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1909 = MAX_U_H 6771 { 1910, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1910 = MAX_U_W 6772 { 1911, 3, 1, 4, 411, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1911 = MFC0 6773 { 1912, 3, 1, 4, 1033, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1912 = MFC0_MMR6 6774 { 1913, 2, 1, 4, 687, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1913 = MFC1 6775 { 1914, 2, 1, 4, 687, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1914 = MFC1_D64 6776 { 1915, 2, 1, 4, 1256, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1915 = MFC1_MM 6777 { 1916, 2, 1, 4, 1301, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1916 = MFC1_MMR6 6778 { 1917, 3, 1, 4, 413, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #1917 = MFC2 6779 { 1918, 2, 1, 4, 1034, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1918 = MFC2_MMR6 6780 { 1919, 3, 1, 4, 416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1919 = MFGC0 6781 { 1920, 3, 1, 4, 1068, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1920 = MFGC0_MM 6782 { 1921, 3, 1, 4, 1032, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1921 = MFHC0_MMR6 6783 { 1922, 2, 1, 4, 688, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #1922 = MFHC1_D32 6784 { 1923, 2, 1, 4, 1257, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #1923 = MFHC1_D32_MM 6785 { 1924, 2, 1, 4, 688, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1924 = MFHC1_D64 6786 { 1925, 2, 1, 4, 1257, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1925 = MFHC1_D64_MM 6787 { 1926, 2, 1, 4, 1034, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1926 = MFHC2_MMR6 6788 { 1927, 3, 1, 4, 417, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1927 = MFHGC0 6789 { 1928, 3, 1, 4, 1069, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1928 = MFHGC0_MM 6790 { 1929, 1, 1, 4, 473, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1929 = MFHI 6791 { 1930, 1, 1, 2, 879, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1930 = MFHI16_MM 6792 { 1931, 1, 1, 4, 898, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1931 = MFHI64 6793 { 1932, 2, 1, 4, 1387, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1932 = MFHI_DSP 6794 { 1933, 2, 1, 4, 1547, 0, 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1933 = MFHI_DSP_MM 6795 { 1934, 1, 1, 4, 879, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1934 = MFHI_MM 6796 { 1935, 1, 1, 4, 473, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1935 = MFLO 6797 { 1936, 1, 1, 2, 879, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1936 = MFLO16_MM 6798 { 1937, 1, 1, 4, 898, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1937 = MFLO64 6799 { 1938, 2, 1, 4, 1388, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1938 = MFLO_DSP 6800 { 1939, 2, 1, 4, 1548, 0, 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1939 = MFLO_DSP_MM 6801 { 1940, 1, 1, 4, 879, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1940 = MFLO_MM 6802 { 1941, 5, 1, 4, 1055, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #1941 = MFTR 6803 { 1942, 3, 1, 4, 1214, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1942 = MINA_D 6804 { 1943, 3, 1, 4, 1311, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1943 = MINA_D_MMR6 6805 { 1944, 3, 1, 4, 1215, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1944 = MINA_S 6806 { 1945, 3, 1, 4, 1312, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1945 = MINA_S_MMR6 6807 { 1946, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1946 = MINI_S_B 6808 { 1947, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1947 = MINI_S_D 6809 { 1948, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1948 = MINI_S_H 6810 { 1949, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1949 = MINI_S_W 6811 { 1950, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1950 = MINI_U_B 6812 { 1951, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1951 = MINI_U_D 6813 { 1952, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1952 = MINI_U_H 6814 { 1953, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1953 = MINI_U_W 6815 { 1954, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1954 = MIN_A_B 6816 { 1955, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1955 = MIN_A_D 6817 { 1956, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1956 = MIN_A_H 6818 { 1957, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1957 = MIN_A_W 6819 { 1958, 3, 1, 4, 1215, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1958 = MIN_D 6820 { 1959, 3, 1, 4, 1307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1959 = MIN_D_MMR6 6821 { 1960, 3, 1, 4, 1214, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1960 = MIN_S 6822 { 1961, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1961 = MIN_S_B 6823 { 1962, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1962 = MIN_S_D 6824 { 1963, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1963 = MIN_S_H 6825 { 1964, 3, 1, 4, 1308, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1964 = MIN_S_MMR6 6826 { 1965, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1965 = MIN_S_W 6827 { 1966, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1966 = MIN_U_B 6828 { 1967, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1967 = MIN_U_D 6829 { 1968, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1968 = MIN_U_H 6830 { 1969, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1969 = MIN_U_W 6831 { 1970, 3, 1, 4, 865, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1970 = MOD 6832 { 1971, 3, 1, 4, 1389, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1971 = MODSUB 6833 { 1972, 3, 1, 4, 1549, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1972 = MODSUB_MM 6834 { 1973, 3, 1, 4, 866, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1973 = MODU 6835 { 1974, 3, 1, 4, 888, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1974 = MODU_MMR6 6836 { 1975, 3, 1, 4, 889, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1975 = MOD_MMR6 6837 { 1976, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1976 = MOD_S_B 6838 { 1977, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1977 = MOD_S_D 6839 { 1978, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1978 = MOD_S_H 6840 { 1979, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1979 = MOD_S_W 6841 { 1980, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1980 = MOD_U_B 6842 { 1981, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1981 = MOD_U_D 6843 { 1982, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1982 = MOD_U_H 6844 { 1983, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1983 = MOD_U_W 6845 { 1984, 2, 1, 2, 742, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1984 = MOVE16_MM 6846 { 1985, 2, 1, 2, 784, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1985 = MOVE16_MMR6 6847 { 1986, 4, 2, 2, 743, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1986 = MOVEP_MM 6848 { 1987, 4, 2, 2, 1550, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1987 = MOVEP_MMR6 6849 { 1988, 2, 1, 4, 541, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #1988 = MOVE_V 6850 { 1989, 4, 1, 4, 526, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1989 = MOVF_D32 6851 { 1990, 4, 1, 4, 1227, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1990 = MOVF_D32_MM 6852 { 1991, 4, 1, 4, 526, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #1991 = MOVF_D64 6853 { 1992, 4, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #1992 = MOVF_I 6854 { 1993, 4, 1, 4, 1205, 0, 0x4ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #1993 = MOVF_I64 6855 { 1994, 4, 1, 4, 880, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #1994 = MOVF_I_MM 6856 { 1995, 4, 1, 4, 527, 0, 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #1995 = MOVF_S 6857 { 1996, 4, 1, 4, 1228, 0, 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #1996 = MOVF_S_MM 6858 { 1997, 4, 1, 4, 1207, 0, 0x4ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #1997 = MOVN_I64_D64 6859 { 1998, 4, 1, 4, 902, 0, 0x4ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #1998 = MOVN_I64_I 6860 { 1999, 4, 1, 4, 902, 0, 0x4ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #1999 = MOVN_I64_I64 6861 { 2000, 4, 1, 4, 1208, 0, 0x4ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2000 = MOVN_I64_S 6862 { 2001, 4, 1, 4, 698, 0, 0x4ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2001 = MOVN_I_D32 6863 { 2002, 4, 1, 4, 1229, 0, 0x4ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2002 = MOVN_I_D32_MM 6864 { 2003, 4, 1, 4, 698, 0, 0x4ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2003 = MOVN_I_D64 6865 { 2004, 4, 1, 4, 477, 0, 0x4ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2004 = MOVN_I_I 6866 { 2005, 4, 1, 4, 902, 0, 0x4ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2005 = MOVN_I_I64 6867 { 2006, 4, 1, 4, 1551, 0, 0x4ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2006 = MOVN_I_MM 6868 { 2007, 4, 1, 4, 699, 0, 0x4ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2007 = MOVN_I_S 6869 { 2008, 4, 1, 4, 1230, 0, 0x4ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2008 = MOVN_I_S_MM 6870 { 2009, 4, 1, 4, 528, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2009 = MOVT_D32 6871 { 2010, 4, 1, 4, 1231, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2010 = MOVT_D32_MM 6872 { 2011, 4, 1, 4, 528, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #2011 = MOVT_D64 6873 { 2012, 4, 1, 4, 690, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #2012 = MOVT_I 6874 { 2013, 4, 1, 4, 1204, 0, 0x4ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #2013 = MOVT_I64 6875 { 2014, 4, 1, 4, 881, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #2014 = MOVT_I_MM 6876 { 2015, 4, 1, 4, 529, 0, 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2015 = MOVT_S 6877 { 2016, 4, 1, 4, 1232, 0, 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2016 = MOVT_S_MM 6878 { 2017, 4, 1, 4, 1209, 0, 0x4ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #2017 = MOVZ_I64_D64 6879 { 2018, 4, 1, 4, 903, 0, 0x4ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #2018 = MOVZ_I64_I 6880 { 2019, 4, 1, 4, 903, 0, 0x4ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2019 = MOVZ_I64_I64 6881 { 2020, 4, 1, 4, 1206, 0, 0x4ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2020 = MOVZ_I64_S 6882 { 2021, 4, 1, 4, 700, 0, 0x4ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2021 = MOVZ_I_D32 6883 { 2022, 4, 1, 4, 1233, 0, 0x4ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2022 = MOVZ_I_D32_MM 6884 { 2023, 4, 1, 4, 700, 0, 0x4ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2023 = MOVZ_I_D64 6885 { 2024, 4, 1, 4, 478, 0, 0x4ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2024 = MOVZ_I_I 6886 { 2025, 4, 1, 4, 903, 0, 0x4ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2025 = MOVZ_I_I64 6887 { 2026, 4, 1, 4, 1552, 0, 0x4ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2026 = MOVZ_I_MM 6888 { 2027, 4, 1, 4, 701, 0, 0x4ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2027 = MOVZ_I_S 6889 { 2028, 4, 1, 4, 1234, 0, 0x4ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2028 = MOVZ_I_S_MM 6890 { 2029, 2, 0, 4, 847, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2029 = MSUB 6891 { 2030, 4, 1, 4, 1226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2030 = MSUBF_D 6892 { 2031, 4, 1, 4, 1320, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2031 = MSUBF_D_MMR6 6893 { 2032, 4, 1, 4, 1224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2032 = MSUBF_S 6894 { 2033, 4, 1, 4, 1321, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2033 = MSUBF_S_MMR6 6895 { 2034, 4, 1, 4, 665, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #2034 = MSUBR_Q_H 6896 { 2035, 4, 1, 4, 665, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2035 = MSUBR_Q_W 6897 { 2036, 2, 0, 4, 848, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2036 = MSUBU 6898 { 2037, 4, 1, 4, 1390, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2037 = MSUBU_DSP 6899 { 2038, 4, 1, 4, 1553, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2038 = MSUBU_DSP_MM 6900 { 2039, 2, 0, 4, 875, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2039 = MSUBU_MM 6901 { 2040, 4, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #2040 = MSUBV_B 6902 { 2041, 4, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2041 = MSUBV_D 6903 { 2042, 4, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #2042 = MSUBV_H 6904 { 2043, 4, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2043 = MSUBV_W 6905 { 2044, 4, 1, 4, 671, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2044 = MSUB_D32 6906 { 2045, 4, 1, 4, 1272, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2045 = MSUB_D32_MM 6907 { 2046, 4, 1, 4, 671, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2046 = MSUB_D64 6908 { 2047, 4, 1, 4, 1391, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2047 = MSUB_DSP 6909 { 2048, 4, 1, 4, 1554, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2048 = MSUB_DSP_MM 6910 { 2049, 2, 0, 4, 874, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2049 = MSUB_MM 6911 { 2050, 4, 1, 4, 666, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #2050 = MSUB_Q_H 6912 { 2051, 4, 1, 4, 666, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2051 = MSUB_Q_W 6913 { 2052, 4, 1, 4, 672, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2052 = MSUB_S 6914 { 2053, 4, 1, 4, 1271, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2053 = MSUB_S_MM 6915 { 2054, 3, 1, 4, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2054 = MTC0 6916 { 2055, 3, 1, 4, 1036, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2055 = MTC0_MMR6 6917 { 2056, 2, 1, 4, 678, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #2056 = MTC1 6918 { 2057, 2, 1, 4, 678, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #2057 = MTC1_D64 6919 { 2058, 2, 1, 4, 1258, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #2058 = MTC1_D64_MM 6920 { 2059, 2, 1, 4, 1258, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #2059 = MTC1_MM 6921 { 2060, 2, 1, 4, 1302, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #2060 = MTC1_MMR6 6922 { 2061, 3, 1, 4, 414, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2061 = MTC2 6923 { 2062, 2, 1, 4, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #2062 = MTC2_MMR6 6924 { 2063, 3, 1, 4, 418, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2063 = MTGC0 6925 { 2064, 3, 1, 4, 1070, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2064 = MTGC0_MM 6926 { 2065, 3, 1, 4, 1035, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2065 = MTHC0_MMR6 6927 { 2066, 3, 1, 4, 679, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2066 = MTHC1_D32 6928 { 2067, 3, 1, 4, 1259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2067 = MTHC1_D32_MM 6929 { 2068, 3, 1, 4, 679, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2068 = MTHC1_D64 6930 { 2069, 3, 1, 4, 1259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2069 = MTHC1_D64_MM 6931 { 2070, 2, 1, 4, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #2070 = MTHC2_MMR6 6932 { 2071, 3, 1, 4, 419, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2071 = MTHGC0 6933 { 2072, 3, 1, 4, 1071, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2072 = MTHGC0_MM 6934 { 2073, 1, 0, 4, 488, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo51, -1 ,nullptr }, // Inst #2073 = MTHI 6935 { 2074, 1, 0, 4, 900, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList22, OperandInfo88, -1 ,nullptr }, // Inst #2074 = MTHI64 6936 { 2075, 2, 1, 4, 1344, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2075 = MTHI_DSP 6937 { 2076, 2, 1, 4, 1555, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2076 = MTHI_DSP_MM 6938 { 2077, 1, 0, 4, 882, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo51, -1 ,nullptr }, // Inst #2077 = MTHI_MM 6939 { 2078, 3, 1, 4, 1343, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo322, -1 ,nullptr }, // Inst #2078 = MTHLIP 6940 { 2079, 3, 1, 4, 1556, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo322, -1 ,nullptr }, // Inst #2079 = MTHLIP_MM 6941 { 2080, 1, 0, 4, 488, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo51, -1 ,nullptr }, // Inst #2080 = MTLO 6942 { 2081, 1, 0, 4, 900, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList24, OperandInfo88, -1 ,nullptr }, // Inst #2081 = MTLO64 6943 { 2082, 2, 1, 4, 1345, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2082 = MTLO_DSP 6944 { 2083, 2, 1, 4, 1557, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2083 = MTLO_DSP_MM 6945 { 2084, 1, 0, 4, 882, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo51, -1 ,nullptr }, // Inst #2084 = MTLO_MM 6946 { 2085, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList25, OperandInfo88, -1 ,nullptr }, // Inst #2085 = MTM0 6947 { 2086, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList26, OperandInfo88, -1 ,nullptr }, // Inst #2086 = MTM1 6948 { 2087, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList27, OperandInfo88, -1 ,nullptr }, // Inst #2087 = MTM2 6949 { 2088, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList28, OperandInfo88, -1 ,nullptr }, // Inst #2088 = MTP0 6950 { 2089, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList29, OperandInfo88, -1 ,nullptr }, // Inst #2089 = MTP1 6951 { 2090, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList30, OperandInfo88, -1 ,nullptr }, // Inst #2090 = MTP2 6952 { 2091, 5, 1, 4, 1056, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2091 = MTTR 6953 { 2092, 3, 1, 4, 861, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2092 = MUH 6954 { 2093, 3, 1, 4, 862, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2093 = MUHU 6955 { 2094, 3, 1, 4, 884, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2094 = MUHU_MMR6 6956 { 2095, 3, 1, 4, 885, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2095 = MUH_MMR6 6957 { 2096, 3, 1, 4, 481, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo65, -1 ,nullptr }, // Inst #2096 = MUL 6958 { 2097, 3, 1, 4, 1392, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo204, -1 ,nullptr }, // Inst #2097 = MULEQ_S_W_PHL 6959 { 2098, 3, 1, 4, 1558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo204, -1 ,nullptr }, // Inst #2098 = MULEQ_S_W_PHL_MM 6960 { 2099, 3, 1, 4, 1393, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo204, -1 ,nullptr }, // Inst #2099 = MULEQ_S_W_PHR 6961 { 2100, 3, 1, 4, 1559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo204, -1 ,nullptr }, // Inst #2100 = MULEQ_S_W_PHR_MM 6962 { 2101, 3, 1, 4, 1394, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2101 = MULEU_S_PH_QBL 6963 { 2102, 3, 1, 4, 1560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2102 = MULEU_S_PH_QBL_MM 6964 { 2103, 3, 1, 4, 1395, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2103 = MULEU_S_PH_QBR 6965 { 2104, 3, 1, 4, 1561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2104 = MULEU_S_PH_QBR_MM 6966 { 2105, 3, 1, 4, 1396, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2105 = MULQ_RS_PH 6967 { 2106, 3, 1, 4, 1562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2106 = MULQ_RS_PH_MM 6968 { 2107, 3, 1, 4, 1473, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo65, -1 ,nullptr }, // Inst #2107 = MULQ_RS_W 6969 { 2108, 3, 1, 4, 1637, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo65, -1 ,nullptr }, // Inst #2108 = MULQ_RS_W_MMR2 6970 { 2109, 3, 1, 4, 1474, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2109 = MULQ_S_PH 6971 { 2110, 3, 1, 4, 1638, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2110 = MULQ_S_PH_MMR2 6972 { 2111, 3, 1, 4, 1475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo65, -1 ,nullptr }, // Inst #2111 = MULQ_S_W 6973 { 2112, 3, 1, 4, 1639, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo65, -1 ,nullptr }, // Inst #2112 = MULQ_S_W_MMR2 6974 { 2113, 3, 1, 4, 667, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2113 = MULR_Q_H 6975 { 2114, 3, 1, 4, 667, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2114 = MULR_Q_W 6976 { 2115, 4, 1, 4, 1397, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #2115 = MULSAQ_S_W_PH 6977 { 2116, 4, 1, 4, 1563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #2116 = MULSAQ_S_W_PH_MM 6978 { 2117, 4, 1, 4, 1476, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2117 = MULSA_W_PH 6979 { 2118, 4, 1, 4, 1640, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2118 = MULSA_W_PH_MMR2 6980 { 2119, 2, 0, 4, 482, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2119 = MULT 6981 { 2120, 3, 1, 4, 1398, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2120 = MULTU_DSP 6982 { 2121, 3, 1, 4, 1564, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2121 = MULTU_DSP_MM 6983 { 2122, 3, 1, 4, 1399, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2122 = MULT_DSP 6984 { 2123, 3, 1, 4, 1565, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2123 = MULT_DSP_MM 6985 { 2124, 2, 0, 4, 870, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2124 = MULT_MM 6986 { 2125, 2, 0, 4, 483, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2125 = MULTu 6987 { 2126, 2, 0, 4, 871, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2126 = MULTu_MM 6988 { 2127, 3, 1, 4, 863, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2127 = MULU 6989 { 2128, 3, 1, 4, 886, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2128 = MULU_MMR6 6990 { 2129, 3, 1, 4, 662, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2129 = MULV_B 6991 { 2130, 3, 1, 4, 662, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2130 = MULV_D 6992 { 2131, 3, 1, 4, 662, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2131 = MULV_H 6993 { 2132, 3, 1, 4, 662, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2132 = MULV_W 6994 { 2133, 3, 1, 4, 876, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo65, -1 ,nullptr }, // Inst #2133 = MUL_MM 6995 { 2134, 3, 1, 4, 887, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2134 = MUL_MMR6 6996 { 2135, 3, 1, 4, 1471, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2135 = MUL_PH 6997 { 2136, 3, 1, 4, 1635, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2136 = MUL_PH_MMR2 6998 { 2137, 3, 1, 4, 668, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2137 = MUL_Q_H 6999 { 2138, 3, 1, 4, 668, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2138 = MUL_Q_W 7000 { 2139, 3, 1, 4, 864, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2139 = MUL_R6 7001 { 2140, 3, 1, 4, 1472, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2140 = MUL_S_PH 7002 { 2141, 3, 1, 4, 1636, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2141 = MUL_S_PH_MMR2 7003 { 2142, 1, 1, 2, 727, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2142 = Mfhi16 7004 { 2143, 1, 1, 2, 727, 0, 0x0ULL, ImplicitList23, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2143 = Mflo16 7005 { 2144, 2, 1, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2144 = Move32R16 7006 { 2145, 2, 1, 2, 727, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2145 = MoveR3216 7007 { 2146, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2146 = NLOC_B 7008 { 2147, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2147 = NLOC_D 7009 { 2148, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2148 = NLOC_H 7010 { 2149, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #2149 = NLOC_W 7011 { 2150, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2150 = NLZC_B 7012 { 2151, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2151 = NLZC_D 7013 { 2152, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2152 = NLZC_H 7014 { 2153, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #2153 = NLZC_W 7015 { 2154, 4, 1, 4, 673, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2154 = NMADD_D32 7016 { 2155, 4, 1, 4, 1239, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2155 = NMADD_D32_MM 7017 { 2156, 4, 1, 4, 673, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2156 = NMADD_D64 7018 { 2157, 4, 1, 4, 674, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2157 = NMADD_S 7019 { 2158, 4, 1, 4, 1238, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2158 = NMADD_S_MM 7020 { 2159, 4, 1, 4, 675, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2159 = NMSUB_D32 7021 { 2160, 4, 1, 4, 1241, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2160 = NMSUB_D32_MM 7022 { 2161, 4, 1, 4, 675, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2161 = NMSUB_D64 7023 { 2162, 4, 1, 4, 676, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2162 = NMSUB_S 7024 { 2163, 4, 1, 4, 1240, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2163 = NMSUB_S_MM 7025 { 2164, 3, 1, 4, 361, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2164 = NOR 7026 { 2165, 3, 1, 4, 834, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2165 = NOR64 7027 { 2166, 3, 1, 4, 544, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2166 = NORI_B 7028 { 2167, 3, 1, 4, 744, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2167 = NOR_MM 7029 { 2168, 3, 1, 4, 785, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2168 = NOR_MMR6 7030 { 2169, 3, 1, 4, 543, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2169 = NOR_V 7031 { 2170, 2, 1, 2, 745, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2170 = NOT16_MM 7032 { 2171, 2, 1, 2, 786, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2171 = NOT16_MMR6 7033 { 2172, 2, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #2172 = NegRxRy16 7034 { 2173, 2, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #2173 = NotRxRy16 7035 { 2174, 3, 1, 4, 362, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2174 = OR 7036 { 2175, 3, 1, 2, 746, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2175 = OR16_MM 7037 { 2176, 3, 1, 2, 787, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2176 = OR16_MMR6 7038 { 2177, 3, 1, 4, 835, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2177 = OR64 7039 { 2178, 3, 1, 4, 544, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2178 = ORI_B 7040 { 2179, 3, 1, 4, 788, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2179 = ORI_MMR6 7041 { 2180, 3, 1, 4, 746, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2180 = OR_MM 7042 { 2181, 3, 1, 4, 787, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2181 = OR_MMR6 7043 { 2182, 3, 1, 4, 543, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2182 = OR_V 7044 { 2183, 3, 1, 4, 495, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2183 = ORi 7045 { 2184, 3, 1, 4, 801, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2184 = ORi64 7046 { 2185, 3, 1, 4, 747, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2185 = ORi_MM 7047 { 2186, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2186 = OrRxRxRy16 7048 { 2187, 3, 1, 4, 1400, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2187 = PACKRL_PH 7049 { 2188, 3, 1, 4, 1566, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2188 = PACKRL_PH_MM 7050 { 2189, 0, 0, 4, 400, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2189 = PAUSE 7051 { 2190, 0, 0, 4, 1026, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2190 = PAUSE_MM 7052 { 2191, 0, 0, 4, 1043, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2191 = PAUSE_MMR6 7053 { 2192, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2192 = PCKEV_B 7054 { 2193, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2193 = PCKEV_D 7055 { 2194, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2194 = PCKEV_H 7056 { 2195, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2195 = PCKEV_W 7057 { 2196, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2196 = PCKOD_B 7058 { 2197, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2197 = PCKOD_D 7059 { 2198, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2198 = PCKOD_H 7060 { 2199, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2199 = PCKOD_W 7061 { 2200, 2, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2200 = PCNT_B 7062 { 2201, 2, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2201 = PCNT_D 7063 { 2202, 2, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2202 = PCNT_H 7064 { 2203, 2, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #2203 = PCNT_W 7065 { 2204, 3, 1, 4, 1401, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2204 = PICK_PH 7066 { 2205, 3, 1, 4, 1567, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2205 = PICK_PH_MM 7067 { 2206, 3, 1, 4, 1402, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2206 = PICK_QB 7068 { 2207, 3, 1, 4, 1568, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2207 = PICK_QB_MM 7069 { 2208, 3, 1, 4, 637, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2208 = PLL_PS64 7070 { 2209, 3, 1, 4, 637, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2209 = PLU_PS64 7071 { 2210, 2, 1, 4, 1195, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2210 = POP 7072 { 2211, 2, 1, 4, 1404, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2211 = PRECEQU_PH_QBL 7073 { 2212, 2, 1, 4, 1403, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2212 = PRECEQU_PH_QBLA 7074 { 2213, 2, 1, 4, 1569, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2213 = PRECEQU_PH_QBLA_MM 7075 { 2214, 2, 1, 4, 1570, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2214 = PRECEQU_PH_QBL_MM 7076 { 2215, 2, 1, 4, 1406, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2215 = PRECEQU_PH_QBR 7077 { 2216, 2, 1, 4, 1405, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2216 = PRECEQU_PH_QBRA 7078 { 2217, 2, 1, 4, 1571, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2217 = PRECEQU_PH_QBRA_MM 7079 { 2218, 2, 1, 4, 1572, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2218 = PRECEQU_PH_QBR_MM 7080 { 2219, 2, 1, 4, 1407, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2219 = PRECEQ_W_PHL 7081 { 2220, 2, 1, 4, 1573, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2220 = PRECEQ_W_PHL_MM 7082 { 2221, 2, 1, 4, 1408, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2221 = PRECEQ_W_PHR 7083 { 2222, 2, 1, 4, 1574, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2222 = PRECEQ_W_PHR_MM 7084 { 2223, 2, 1, 4, 1410, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2223 = PRECEU_PH_QBL 7085 { 2224, 2, 1, 4, 1409, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2224 = PRECEU_PH_QBLA 7086 { 2225, 2, 1, 4, 1575, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2225 = PRECEU_PH_QBLA_MM 7087 { 2226, 2, 1, 4, 1576, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2226 = PRECEU_PH_QBL_MM 7088 { 2227, 2, 1, 4, 1412, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2227 = PRECEU_PH_QBR 7089 { 2228, 2, 1, 4, 1411, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2228 = PRECEU_PH_QBRA 7090 { 2229, 2, 1, 4, 1577, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2229 = PRECEU_PH_QBRA_MM 7091 { 2230, 2, 1, 4, 1578, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2230 = PRECEU_PH_QBR_MM 7092 { 2231, 3, 1, 4, 1413, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo163, -1 ,nullptr }, // Inst #2231 = PRECRQU_S_QB_PH 7093 { 2232, 3, 1, 4, 1579, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo163, -1 ,nullptr }, // Inst #2232 = PRECRQU_S_QB_PH_MM 7094 { 2233, 3, 1, 4, 1414, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2233 = PRECRQ_PH_W 7095 { 2234, 3, 1, 4, 1580, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2234 = PRECRQ_PH_W_MM 7096 { 2235, 3, 1, 4, 1415, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2235 = PRECRQ_QB_PH 7097 { 2236, 3, 1, 4, 1581, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2236 = PRECRQ_QB_PH_MM 7098 { 2237, 3, 1, 4, 1416, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2237 = PRECRQ_RS_PH_W 7099 { 2238, 3, 1, 4, 1582, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2238 = PRECRQ_RS_PH_W_MM 7100 { 2239, 3, 1, 4, 1477, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2239 = PRECR_QB_PH 7101 { 2240, 3, 1, 4, 1641, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2240 = PRECR_QB_PH_MMR2 7102 { 2241, 4, 1, 4, 1478, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2241 = PRECR_SRA_PH_W 7103 { 2242, 4, 1, 4, 1642, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2242 = PRECR_SRA_PH_W_MMR2 7104 { 2243, 4, 1, 4, 1479, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2243 = PRECR_SRA_R_PH_W 7105 { 2244, 4, 1, 4, 1643, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2244 = PRECR_SRA_R_PH_W_MMR2 7106 { 2245, 3, 0, 4, 463, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2245 = PREF 7107 { 2246, 3, 0, 4, 464, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2246 = PREFE 7108 { 2247, 3, 0, 4, 1098, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2247 = PREFE_MM 7109 { 2248, 3, 0, 4, 1131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2248 = PREFX_MM 7110 { 2249, 3, 0, 4, 1131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2249 = PREF_MM 7111 { 2250, 3, 0, 4, 1153, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2250 = PREF_MMR6 7112 { 2251, 3, 0, 4, 1079, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2251 = PREF_R6 7113 { 2252, 4, 1, 4, 1480, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2252 = PREPEND 7114 { 2253, 4, 1, 4, 1644, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2253 = PREPEND_MMR2 7115 { 2254, 2, 1, 4, 1417, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2254 = RADDU_W_QB 7116 { 2255, 2, 1, 4, 1583, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2255 = RADDU_W_QB_MM 7117 { 2256, 2, 1, 4, 1418, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2256 = RDDSP 7118 { 2257, 2, 1, 4, 1584, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2257 = RDDSP_MM 7119 { 2258, 3, 1, 4, 475, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2258 = RDHWR 7120 { 2259, 3, 1, 4, 901, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo333, -1 ,nullptr }, // Inst #2259 = RDHWR64 7121 { 2260, 3, 1, 4, 883, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2260 = RDHWR_MM 7122 { 2261, 3, 1, 4, 892, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2261 = RDHWR_MMR6 7123 { 2262, 2, 1, 4, 1028, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2262 = RDPGPR_MMR6 7124 { 2263, 2, 1, 4, 644, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2263 = RECIP_D32 7125 { 2264, 2, 1, 4, 1278, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2264 = RECIP_D32_MM 7126 { 2265, 2, 1, 4, 644, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2265 = RECIP_D64 7127 { 2266, 2, 1, 4, 1278, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2266 = RECIP_D64_MM 7128 { 2267, 2, 1, 4, 646, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2267 = RECIP_S 7129 { 2268, 2, 1, 4, 1277, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2268 = RECIP_S_MM 7130 { 2269, 2, 1, 4, 1419, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2269 = REPLV_PH 7131 { 2270, 2, 1, 4, 1585, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2270 = REPLV_PH_MM 7132 { 2271, 2, 1, 4, 1420, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2271 = REPLV_QB 7133 { 2272, 2, 1, 4, 1586, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2272 = REPLV_QB_MM 7134 { 2273, 2, 1, 4, 1421, 0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2273 = REPL_PH 7135 { 2274, 2, 1, 4, 1587, 0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2274 = REPL_PH_MM 7136 { 2275, 2, 1, 4, 1422, 0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2275 = REPL_QB 7137 { 2276, 2, 1, 4, 1588, 0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2276 = REPL_QB_MM 7138 { 2277, 2, 1, 4, 1219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2277 = RINT_D 7139 { 2278, 2, 1, 4, 1317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2278 = RINT_D_MMR6 7140 { 2279, 2, 1, 4, 1218, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2279 = RINT_S 7141 { 2280, 2, 1, 4, 1317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2280 = RINT_S_MMR6 7142 { 2281, 3, 1, 4, 496, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2281 = ROTR 7143 { 2282, 3, 1, 4, 712, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2282 = ROTRV 7144 { 2283, 3, 1, 4, 748, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2283 = ROTRV_MM 7145 { 2284, 3, 1, 4, 749, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2284 = ROTR_MM 7146 { 2285, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2285 = ROUND_L_D64 7147 { 2286, 2, 1, 4, 1298, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2286 = ROUND_L_D_MMR6 7148 { 2287, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2287 = ROUND_L_S 7149 { 2288, 2, 1, 4, 1298, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2288 = ROUND_L_S_MMR6 7150 { 2289, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #2289 = ROUND_W_D32 7151 { 2290, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #2290 = ROUND_W_D64 7152 { 2291, 2, 1, 4, 1298, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2291 = ROUND_W_D_MMR6 7153 { 2292, 2, 1, 4, 1244, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #2292 = ROUND_W_MM 7154 { 2293, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2293 = ROUND_W_S 7155 { 2294, 2, 1, 4, 1244, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2294 = ROUND_W_S_MM 7156 { 2295, 2, 1, 4, 1298, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2295 = ROUND_W_S_MMR6 7157 { 2296, 2, 1, 4, 645, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2296 = RSQRT_D32 7158 { 2297, 2, 1, 4, 1278, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2297 = RSQRT_D32_MM 7159 { 2298, 2, 1, 4, 645, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2298 = RSQRT_D64 7160 { 2299, 2, 1, 4, 1278, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2299 = RSQRT_D64_MM 7161 { 2300, 2, 1, 4, 647, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2300 = RSQRT_S 7162 { 2301, 2, 1, 4, 1277, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2301 = RSQRT_S_MM 7163 { 2302, 0, 0, 2, 1100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2302 = Restore16 7164 { 2303, 0, 0, 2, 1100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2303 = RestoreX16 7165 { 2304, 2, 0, 4, 1202, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2304 = SAA 7166 { 2305, 2, 0, 4, 1202, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2305 = SAAD 7167 { 2306, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2306 = SAT_S_B 7168 { 2307, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2307 = SAT_S_D 7169 { 2308, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2308 = SAT_S_H 7170 { 2309, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2309 = SAT_S_W 7171 { 2310, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2310 = SAT_U_B 7172 { 2311, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2311 = SAT_U_D 7173 { 2312, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2312 = SAT_U_H 7174 { 2313, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2313 = SAT_U_W 7175 { 2314, 3, 0, 4, 447, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2314 = SB 7176 { 2315, 3, 0, 2, 1122, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2315 = SB16_MM 7177 { 2316, 3, 0, 2, 1145, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2316 = SB16_MMR6 7178 { 2317, 3, 0, 4, 1169, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2317 = SB64 7179 { 2318, 3, 0, 4, 455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2318 = SBE 7180 { 2319, 3, 0, 4, 1091, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2319 = SBE_MM 7181 { 2320, 3, 0, 4, 1092, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2320 = SB_MM 7182 { 2321, 3, 0, 4, 1145, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2321 = SB_MMR6 7183 { 2322, 4, 1, 4, 454, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2322 = SC 7184 { 2323, 4, 1, 4, 1168, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2323 = SC64 7185 { 2324, 4, 1, 4, 1180, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2324 = SC64_R6 7186 { 2325, 4, 1, 4, 1168, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2325 = SCD 7187 { 2326, 4, 1, 4, 1181, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2326 = SCD_R6 7188 { 2327, 4, 1, 4, 458, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2327 = SCE 7189 { 2328, 4, 1, 4, 1097, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2328 = SCE_MM 7190 { 2329, 4, 1, 4, 1123, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2329 = SC_MM 7191 { 2330, 4, 1, 4, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2330 = SC_MMR6 7192 { 2331, 4, 1, 4, 1078, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2331 = SC_R6 7193 { 2332, 3, 0, 4, 1167, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2332 = SD 7194 { 2333, 1, 0, 4, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2333 = SDBBP 7195 { 2334, 1, 0, 2, 959, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2334 = SDBBP16_MM 7196 { 2335, 1, 0, 2, 1000, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2335 = SDBBP16_MMR6 7197 { 2336, 1, 0, 4, 959, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2336 = SDBBP_MM 7198 { 2337, 1, 0, 4, 1000, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2337 = SDBBP_MMR6 7199 { 2338, 1, 0, 4, 930, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2338 = SDBBP_R6 7200 { 2339, 3, 0, 4, 691, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #2339 = SDC1 7201 { 2340, 3, 0, 4, 691, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2340 = SDC164 7202 { 2341, 3, 0, 4, 1327, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2341 = SDC1_D64_MMR6 7203 { 2342, 3, 0, 4, 1279, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #2342 = SDC1_MM 7204 { 2343, 3, 0, 4, 452, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2343 = SDC2 7205 { 2344, 3, 0, 4, 1146, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2344 = SDC2_MMR6 7206 { 2345, 3, 0, 4, 1077, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2345 = SDC2_R6 7207 { 2346, 3, 0, 4, 453, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2346 = SDC3 7208 { 2347, 2, 0, 4, 857, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2347 = SDIV 7209 { 2348, 2, 0, 4, 877, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2348 = SDIV_MM 7210 { 2349, 3, 0, 4, 1174, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2349 = SDL 7211 { 2350, 3, 0, 4, 1175, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2350 = SDR 7212 { 2351, 3, 0, 4, 692, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2351 = SDXC1 7213 { 2352, 3, 0, 4, 692, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2352 = SDXC164 7214 { 2353, 2, 1, 4, 497, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2353 = SEB 7215 { 2354, 2, 1, 4, 802, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2354 = SEB64 7216 { 2355, 2, 1, 4, 750, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2355 = SEB_MM 7217 { 2356, 2, 1, 4, 498, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2356 = SEH 7218 { 2357, 2, 1, 4, 803, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2357 = SEH64 7219 { 2358, 2, 1, 4, 751, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2358 = SEH_MM 7220 { 2359, 3, 1, 4, 726, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2359 = SELEQZ 7221 { 2360, 3, 1, 4, 844, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2360 = SELEQZ64 7222 { 2361, 3, 1, 4, 1211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2361 = SELEQZ_D 7223 { 2362, 3, 1, 4, 1313, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2362 = SELEQZ_D_MMR6 7224 { 2363, 3, 1, 4, 789, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2363 = SELEQZ_MMR6 7225 { 2364, 3, 1, 4, 1210, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2364 = SELEQZ_S 7226 { 2365, 3, 1, 4, 1314, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2365 = SELEQZ_S_MMR6 7227 { 2366, 3, 1, 4, 726, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2366 = SELNEZ 7228 { 2367, 3, 1, 4, 844, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2367 = SELNEZ64 7229 { 2368, 3, 1, 4, 1211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2368 = SELNEZ_D 7230 { 2369, 3, 1, 4, 1313, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2369 = SELNEZ_D_MMR6 7231 { 2370, 3, 1, 4, 789, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2370 = SELNEZ_MMR6 7232 { 2371, 3, 1, 4, 1210, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2371 = SELNEZ_S 7233 { 2372, 3, 1, 4, 1314, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2372 = SELNEZ_S_MMR6 7234 { 2373, 4, 1, 4, 1221, 0, 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2373 = SEL_D 7235 { 2374, 4, 1, 4, 1315, 0, 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2374 = SEL_D_MMR6 7236 { 2375, 4, 1, 4, 1222, 0, 0x6ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2375 = SEL_S 7237 { 2376, 4, 1, 4, 1316, 0, 0x6ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2376 = SEL_S_MMR6 7238 { 2377, 3, 1, 4, 1198, 0, 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2377 = SEQ 7239 { 2378, 3, 1, 4, 1199, 0, 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2378 = SEQi 7240 { 2379, 3, 0, 4, 448, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2379 = SH 7241 { 2380, 3, 0, 2, 1124, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2380 = SH16_MM 7242 { 2381, 3, 0, 2, 1147, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2381 = SH16_MMR6 7243 { 2382, 3, 0, 4, 1170, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2382 = SH64 7244 { 2383, 3, 0, 4, 456, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2383 = SHE 7245 { 2384, 3, 0, 4, 1093, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2384 = SHE_MM 7246 { 2385, 3, 1, 4, 538, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2385 = SHF_B 7247 { 2386, 3, 1, 4, 538, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2386 = SHF_H 7248 { 2387, 3, 1, 4, 538, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2387 = SHF_W 7249 { 2388, 3, 1, 4, 1424, 0, 0x6ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2388 = SHILO 7250 { 2389, 3, 1, 4, 1423, 0, 0x6ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr }, // Inst #2389 = SHILOV 7251 { 2390, 3, 1, 4, 1589, 0, 0x6ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr }, // Inst #2390 = SHILOV_MM 7252 { 2391, 3, 1, 4, 1590, 0, 0x6ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2391 = SHILO_MM 7253 { 2392, 3, 1, 4, 1425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2392 = SHLLV_PH 7254 { 2393, 3, 1, 4, 1591, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2393 = SHLLV_PH_MM 7255 { 2394, 3, 1, 4, 1426, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2394 = SHLLV_QB 7256 { 2395, 3, 1, 4, 1592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2395 = SHLLV_QB_MM 7257 { 2396, 3, 1, 4, 1427, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2396 = SHLLV_S_PH 7258 { 2397, 3, 1, 4, 1593, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2397 = SHLLV_S_PH_MM 7259 { 2398, 3, 1, 4, 1428, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo65, -1 ,nullptr }, // Inst #2398 = SHLLV_S_W 7260 { 2399, 3, 1, 4, 1594, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo65, -1 ,nullptr }, // Inst #2399 = SHLLV_S_W_MM 7261 { 2400, 3, 1, 4, 1429, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2400 = SHLL_PH 7262 { 2401, 3, 1, 4, 1595, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2401 = SHLL_PH_MM 7263 { 2402, 3, 1, 4, 1430, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2402 = SHLL_QB 7264 { 2403, 3, 1, 4, 1596, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2403 = SHLL_QB_MM 7265 { 2404, 3, 1, 4, 1431, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2404 = SHLL_S_PH 7266 { 2405, 3, 1, 4, 1597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2405 = SHLL_S_PH_MM 7267 { 2406, 3, 1, 4, 1432, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo66, -1 ,nullptr }, // Inst #2406 = SHLL_S_W 7268 { 2407, 3, 1, 4, 1598, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo66, -1 ,nullptr }, // Inst #2407 = SHLL_S_W_MM 7269 { 2408, 3, 1, 4, 1433, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2408 = SHRAV_PH 7270 { 2409, 3, 1, 4, 1599, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2409 = SHRAV_PH_MM 7271 { 2410, 3, 1, 4, 1483, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2410 = SHRAV_QB 7272 { 2411, 3, 1, 4, 1647, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2411 = SHRAV_QB_MMR2 7273 { 2412, 3, 1, 4, 1434, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2412 = SHRAV_R_PH 7274 { 2413, 3, 1, 4, 1600, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2413 = SHRAV_R_PH_MM 7275 { 2414, 3, 1, 4, 1484, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2414 = SHRAV_R_QB 7276 { 2415, 3, 1, 4, 1648, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2415 = SHRAV_R_QB_MMR2 7277 { 2416, 3, 1, 4, 1435, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2416 = SHRAV_R_W 7278 { 2417, 3, 1, 4, 1601, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2417 = SHRAV_R_W_MM 7279 { 2418, 3, 1, 4, 1436, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2418 = SHRA_PH 7280 { 2419, 3, 1, 4, 1602, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2419 = SHRA_PH_MM 7281 { 2420, 3, 1, 4, 1481, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2420 = SHRA_QB 7282 { 2421, 3, 1, 4, 1645, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2421 = SHRA_QB_MMR2 7283 { 2422, 3, 1, 4, 1437, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2422 = SHRA_R_PH 7284 { 2423, 3, 1, 4, 1603, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2423 = SHRA_R_PH_MM 7285 { 2424, 3, 1, 4, 1482, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2424 = SHRA_R_QB 7286 { 2425, 3, 1, 4, 1646, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2425 = SHRA_R_QB_MMR2 7287 { 2426, 3, 1, 4, 1438, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2426 = SHRA_R_W 7288 { 2427, 3, 1, 4, 1604, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2427 = SHRA_R_W_MM 7289 { 2428, 3, 1, 4, 1486, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2428 = SHRLV_PH 7290 { 2429, 3, 1, 4, 1650, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2429 = SHRLV_PH_MMR2 7291 { 2430, 3, 1, 4, 1439, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2430 = SHRLV_QB 7292 { 2431, 3, 1, 4, 1605, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2431 = SHRLV_QB_MM 7293 { 2432, 3, 1, 4, 1485, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2432 = SHRL_PH 7294 { 2433, 3, 1, 4, 1649, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2433 = SHRL_PH_MMR2 7295 { 2434, 3, 1, 4, 1440, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2434 = SHRL_QB 7296 { 2435, 3, 1, 4, 1606, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2435 = SHRL_QB_MM 7297 { 2436, 3, 0, 4, 1124, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2436 = SH_MM 7298 { 2437, 3, 0, 4, 1147, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2437 = SH_MMR6 7299 { 2438, 1, 0, 4, 927, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2438 = SIGRIE 7300 { 2439, 1, 0, 4, 988, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2439 = SIGRIE_MMR6 7301 { 2440, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2440 = SLDI_B 7302 { 2441, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2441 = SLDI_D 7303 { 2442, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2442 = SLDI_H 7304 { 2443, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2443 = SLDI_W 7305 { 2444, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #2444 = SLD_B 7306 { 2445, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2445 = SLD_D 7307 { 2446, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo347, -1 ,nullptr }, // Inst #2446 = SLD_H 7308 { 2447, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo348, -1 ,nullptr }, // Inst #2447 = SLD_W 7309 { 2448, 3, 1, 4, 500, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2448 = SLL 7310 { 2449, 3, 1, 2, 752, 0, 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2449 = SLL16_MM 7311 { 2450, 3, 1, 2, 790, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2450 = SLL16_MMR6 7312 { 2451, 2, 1, 4, 804, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2451 = SLL64_32 7313 { 2452, 2, 1, 4, 804, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2452 = SLL64_64 7314 { 2453, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2453 = SLLI_B 7315 { 2454, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2454 = SLLI_D 7316 { 2455, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2455 = SLLI_H 7317 { 2456, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2456 = SLLI_W 7318 { 2457, 3, 1, 4, 505, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2457 = SLLV 7319 { 2458, 3, 1, 4, 753, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2458 = SLLV_MM 7320 { 2459, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2459 = SLL_B 7321 { 2460, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2460 = SLL_D 7322 { 2461, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2461 = SLL_H 7323 { 2462, 3, 1, 4, 752, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2462 = SLL_MM 7324 { 2463, 3, 1, 4, 790, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2463 = SLL_MMR6 7325 { 2464, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2464 = SLL_W 7326 { 2465, 3, 1, 4, 499, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2465 = SLT 7327 { 2466, 3, 1, 4, 805, 0, 0x1ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2466 = SLT64 7328 { 2467, 3, 1, 4, 754, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2467 = SLT_MM 7329 { 2468, 3, 1, 4, 363, 0, 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2468 = SLTi 7330 { 2469, 3, 1, 4, 806, 0, 0x2ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2469 = SLTi64 7331 { 2470, 3, 1, 4, 755, 0, 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2470 = SLTi_MM 7332 { 2471, 3, 1, 4, 363, 0, 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2471 = SLTiu 7333 { 2472, 3, 1, 4, 806, 0, 0x2ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2472 = SLTiu64 7334 { 2473, 3, 1, 4, 755, 0, 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2473 = SLTiu_MM 7335 { 2474, 3, 1, 4, 499, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2474 = SLTu 7336 { 2475, 3, 1, 4, 805, 0, 0x1ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2475 = SLTu64 7337 { 2476, 3, 1, 4, 754, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2476 = SLTu_MM 7338 { 2477, 3, 1, 4, 1198, 0, 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2477 = SNE 7339 { 2478, 3, 1, 4, 1199, 0, 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2478 = SNEi 7340 { 2479, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2479 = SPLATI_B 7341 { 2480, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2480 = SPLATI_D 7342 { 2481, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2481 = SPLATI_H 7343 { 2482, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2482 = SPLATI_W 7344 { 2483, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2483 = SPLAT_B 7345 { 2484, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2484 = SPLAT_D 7346 { 2485, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2485 = SPLAT_H 7347 { 2486, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo354, -1 ,nullptr }, // Inst #2486 = SPLAT_W 7348 { 2487, 3, 1, 4, 501, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2487 = SRA 7349 { 2488, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2488 = SRAI_B 7350 { 2489, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2489 = SRAI_D 7351 { 2490, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2490 = SRAI_H 7352 { 2491, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2491 = SRAI_W 7353 { 2492, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2492 = SRARI_B 7354 { 2493, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2493 = SRARI_D 7355 { 2494, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2494 = SRARI_H 7356 { 2495, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2495 = SRARI_W 7357 { 2496, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2496 = SRAR_B 7358 { 2497, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2497 = SRAR_D 7359 { 2498, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2498 = SRAR_H 7360 { 2499, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2499 = SRAR_W 7361 { 2500, 3, 1, 4, 506, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2500 = SRAV 7362 { 2501, 3, 1, 4, 756, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2501 = SRAV_MM 7363 { 2502, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2502 = SRA_B 7364 { 2503, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2503 = SRA_D 7365 { 2504, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2504 = SRA_H 7366 { 2505, 3, 1, 4, 757, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2505 = SRA_MM 7367 { 2506, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2506 = SRA_W 7368 { 2507, 3, 1, 4, 502, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2507 = SRL 7369 { 2508, 3, 1, 2, 758, 0, 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2508 = SRL16_MM 7370 { 2509, 3, 1, 2, 791, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2509 = SRL16_MMR6 7371 { 2510, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2510 = SRLI_B 7372 { 2511, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2511 = SRLI_D 7373 { 2512, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2512 = SRLI_H 7374 { 2513, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2513 = SRLI_W 7375 { 2514, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2514 = SRLRI_B 7376 { 2515, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2515 = SRLRI_D 7377 { 2516, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2516 = SRLRI_H 7378 { 2517, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2517 = SRLRI_W 7379 { 2518, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2518 = SRLR_B 7380 { 2519, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2519 = SRLR_D 7381 { 2520, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2520 = SRLR_H 7382 { 2521, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2521 = SRLR_W 7383 { 2522, 3, 1, 4, 507, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2522 = SRLV 7384 { 2523, 3, 1, 4, 759, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2523 = SRLV_MM 7385 { 2524, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2524 = SRL_B 7386 { 2525, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2525 = SRL_D 7387 { 2526, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2526 = SRL_H 7388 { 2527, 3, 1, 4, 758, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2527 = SRL_MM 7389 { 2528, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2528 = SRL_W 7390 { 2529, 0, 0, 4, 367, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2529 = SSNOP 7391 { 2530, 0, 0, 4, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2530 = SSNOP_MM 7392 { 2531, 0, 0, 4, 792, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2531 = SSNOP_MMR6 7393 { 2532, 3, 0, 4, 696, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2532 = ST_B 7394 { 2533, 3, 0, 4, 696, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2533 = ST_D 7395 { 2534, 3, 0, 4, 696, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #2534 = ST_H 7396 { 2535, 3, 0, 4, 696, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2535 = ST_W 7397 { 2536, 3, 1, 4, 364, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2536 = SUB 7398 { 2537, 3, 1, 4, 1487, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2537 = SUBQH_PH 7399 { 2538, 3, 1, 4, 1651, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2538 = SUBQH_PH_MMR2 7400 { 2539, 3, 1, 4, 1488, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2539 = SUBQH_R_PH 7401 { 2540, 3, 1, 4, 1652, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2540 = SUBQH_R_PH_MMR2 7402 { 2541, 3, 1, 4, 1490, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2541 = SUBQH_R_W 7403 { 2542, 3, 1, 4, 1654, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2542 = SUBQH_R_W_MMR2 7404 { 2543, 3, 1, 4, 1489, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2543 = SUBQH_W 7405 { 2544, 3, 1, 4, 1653, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2544 = SUBQH_W_MMR2 7406 { 2545, 3, 1, 4, 1441, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2545 = SUBQ_PH 7407 { 2546, 3, 1, 4, 1607, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2546 = SUBQ_PH_MM 7408 { 2547, 3, 1, 4, 1442, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2547 = SUBQ_S_PH 7409 { 2548, 3, 1, 4, 1608, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2548 = SUBQ_S_PH_MM 7410 { 2549, 3, 1, 4, 1443, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #2549 = SUBQ_S_W 7411 { 2550, 3, 1, 4, 1609, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #2550 = SUBQ_S_W_MM 7412 { 2551, 3, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2551 = SUBSUS_U_B 7413 { 2552, 3, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2552 = SUBSUS_U_D 7414 { 2553, 3, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2553 = SUBSUS_U_H 7415 { 2554, 3, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2554 = SUBSUS_U_W 7416 { 2555, 3, 1, 4, 605, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2555 = SUBSUU_S_B 7417 { 2556, 3, 1, 4, 605, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2556 = SUBSUU_S_D 7418 { 2557, 3, 1, 4, 605, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2557 = SUBSUU_S_H 7419 { 2558, 3, 1, 4, 605, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2558 = SUBSUU_S_W 7420 { 2559, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2559 = SUBS_S_B 7421 { 2560, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2560 = SUBS_S_D 7422 { 2561, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2561 = SUBS_S_H 7423 { 2562, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2562 = SUBS_S_W 7424 { 2563, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2563 = SUBS_U_B 7425 { 2564, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2564 = SUBS_U_D 7426 { 2565, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2565 = SUBS_U_H 7427 { 2566, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2566 = SUBS_U_W 7428 { 2567, 3, 1, 2, 761, 0, 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #2567 = SUBU16_MM 7429 { 2568, 3, 1, 2, 793, 0, 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #2568 = SUBU16_MMR6 7430 { 2569, 3, 1, 4, 1493, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2569 = SUBUH_QB 7431 { 2570, 3, 1, 4, 1657, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2570 = SUBUH_QB_MMR2 7432 { 2571, 3, 1, 4, 1494, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2571 = SUBUH_R_QB 7433 { 2572, 3, 1, 4, 1658, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2572 = SUBUH_R_QB_MMR2 7434 { 2573, 3, 1, 4, 793, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2573 = SUBU_MMR6 7435 { 2574, 3, 1, 4, 1491, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2574 = SUBU_PH 7436 { 2575, 3, 1, 4, 1655, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2575 = SUBU_PH_MMR2 7437 { 2576, 3, 1, 4, 1444, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2576 = SUBU_QB 7438 { 2577, 3, 1, 4, 1610, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2577 = SUBU_QB_MM 7439 { 2578, 3, 1, 4, 1492, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2578 = SUBU_S_PH 7440 { 2579, 3, 1, 4, 1656, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2579 = SUBU_S_PH_MMR2 7441 { 2580, 3, 1, 4, 1445, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2580 = SUBU_S_QB 7442 { 2581, 3, 1, 4, 1611, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2581 = SUBU_S_QB_MM 7443 { 2582, 3, 1, 4, 606, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2582 = SUBVI_B 7444 { 2583, 3, 1, 4, 606, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2583 = SUBVI_D 7445 { 2584, 3, 1, 4, 606, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2584 = SUBVI_H 7446 { 2585, 3, 1, 4, 606, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2585 = SUBVI_W 7447 { 2586, 3, 1, 4, 607, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2586 = SUBV_B 7448 { 2587, 3, 1, 4, 607, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2587 = SUBV_D 7449 { 2588, 3, 1, 4, 607, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2588 = SUBV_H 7450 { 2589, 3, 1, 4, 607, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2589 = SUBV_W 7451 { 2590, 3, 1, 4, 762, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2590 = SUB_MM 7452 { 2591, 3, 1, 4, 794, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2591 = SUB_MMR6 7453 { 2592, 3, 1, 4, 365, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2592 = SUBu 7454 { 2593, 3, 1, 4, 761, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2593 = SUBu_MM 7455 { 2594, 3, 0, 4, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2594 = SUXC1 7456 { 2595, 3, 0, 4, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2595 = SUXC164 7457 { 2596, 3, 0, 4, 1281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2596 = SUXC1_MM 7458 { 2597, 3, 0, 4, 449, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2597 = SW 7459 { 2598, 3, 0, 2, 1125, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2598 = SW16_MM 7460 { 2599, 3, 0, 2, 1148, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2599 = SW16_MMR6 7461 { 2600, 3, 0, 4, 1171, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2600 = SW64 7462 { 2601, 3, 0, 4, 693, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2601 = SWC1 7463 { 2602, 3, 0, 4, 1280, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2602 = SWC1_MM 7464 { 2603, 3, 0, 4, 450, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2603 = SWC2 7465 { 2604, 3, 0, 4, 1149, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2604 = SWC2_MMR6 7466 { 2605, 3, 0, 4, 1076, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2605 = SWC2_R6 7467 { 2606, 3, 0, 4, 451, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2606 = SWC3 7468 { 2607, 3, 0, 4, 1331, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2607 = SWDSP 7469 { 2608, 3, 0, 4, 1496, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2608 = SWDSP_MM 7470 { 2609, 3, 0, 4, 457, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2609 = SWE 7471 { 2610, 3, 0, 4, 1094, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2610 = SWE_MM 7472 { 2611, 3, 0, 4, 459, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2611 = SWL 7473 { 2612, 3, 0, 4, 1172, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2612 = SWL64 7474 { 2613, 3, 0, 4, 461, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2613 = SWLE 7475 { 2614, 3, 0, 4, 1095, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2614 = SWLE_MM 7476 { 2615, 3, 0, 4, 1126, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2615 = SWL_MM 7477 { 2616, 3, 0, 2, 1127, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2616 = SWM16_MM 7478 { 2617, 3, 0, 2, 1150, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2617 = SWM16_MMR6 7479 { 2618, 3, 0, 4, 1127, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #2618 = SWM32_MM 7480 { 2619, 4, 0, 4, 1129, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2619 = SWP_MM 7481 { 2620, 3, 0, 4, 460, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2620 = SWR 7482 { 2621, 3, 0, 4, 1173, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2621 = SWR64 7483 { 2622, 3, 0, 4, 462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2622 = SWRE 7484 { 2623, 3, 0, 4, 1096, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2623 = SWRE_MM 7485 { 2624, 3, 0, 4, 1130, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2624 = SWR_MM 7486 { 2625, 3, 0, 2, 1125, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2625 = SWSP_MM 7487 { 2626, 3, 0, 2, 1148, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2626 = SWSP_MMR6 7488 { 2627, 3, 0, 4, 694, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2627 = SWXC1 7489 { 2628, 3, 0, 4, 1282, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2628 = SWXC1_MM 7490 { 2629, 3, 0, 4, 1125, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2629 = SW_MM 7491 { 2630, 3, 0, 4, 1148, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2630 = SW_MMR6 7492 { 2631, 1, 0, 4, 467, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2631 = SYNC 7493 { 2632, 2, 0, 4, 468, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #2632 = SYNCI 7494 { 2633, 2, 0, 4, 1134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #2633 = SYNCI_MM 7495 { 2634, 2, 0, 4, 1152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #2634 = SYNCI_MMR6 7496 { 2635, 1, 0, 4, 1133, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2635 = SYNC_MM 7497 { 2636, 1, 0, 4, 1151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2636 = SYNC_MMR6 7498 { 2637, 1, 0, 4, 385, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2637 = SYSCALL 7499 { 2638, 1, 0, 4, 960, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2638 = SYSCALL_MM 7500 { 2639, 0, 0, 2, 1106, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2639 = Save16 7501 { 2640, 0, 0, 2, 1106, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2640 = SaveX16 7502 { 2641, 3, 0, 4, 1107, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2641 = SbRxRyOffMemX16 7503 { 2642, 2, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2642 = SebRx16 7504 { 2643, 2, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2643 = SehRx16 7505 { 2644, 3, 0, 4, 1108, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2644 = ShRxRyOffMemX16 7506 { 2645, 3, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2645 = SllX16 7507 { 2646, 3, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2646 = SllvRxRy16 7508 { 2647, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo121, -1 ,nullptr }, // Inst #2647 = SltRxRy16 7509 { 2648, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #2648 = SltiRxImm16 7510 { 2649, 2, 0, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #2649 = SltiRxImmX16 7511 { 2650, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #2650 = SltiuRxImm16 7512 { 2651, 2, 0, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #2651 = SltiuRxImmX16 7513 { 2652, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo121, -1 ,nullptr }, // Inst #2652 = SltuRxRy16 7514 { 2653, 3, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2653 = SraX16 7515 { 2654, 3, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2654 = SravRxRy16 7516 { 2655, 3, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2655 = SrlX16 7517 { 2656, 3, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2656 = SrlvRxRy16 7518 { 2657, 3, 1, 2, 727, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2657 = SubuRxRyRz16 7519 { 2658, 3, 0, 4, 1109, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2658 = SwRxRyOffMemX16 7520 { 2659, 3, 0, 4, 1109, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #2659 = SwRxSpImmX16 7521 { 2660, 3, 0, 4, 386, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2660 = TEQ 7522 { 2661, 2, 0, 4, 387, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2661 = TEQI 7523 { 2662, 2, 0, 4, 961, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2662 = TEQI_MM 7524 { 2663, 3, 0, 4, 962, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2663 = TEQ_MM 7525 { 2664, 3, 0, 4, 388, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2664 = TGE 7526 { 2665, 2, 0, 4, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2665 = TGEI 7527 { 2666, 2, 0, 4, 390, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2666 = TGEIU 7528 { 2667, 2, 0, 4, 963, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2667 = TGEIU_MM 7529 { 2668, 2, 0, 4, 964, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2668 = TGEI_MM 7530 { 2669, 3, 0, 4, 391, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2669 = TGEU 7531 { 2670, 3, 0, 4, 965, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2670 = TGEU_MM 7532 { 2671, 3, 0, 4, 966, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2671 = TGE_MM 7533 { 2672, 0, 0, 4, 420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2672 = TLBGINV 7534 { 2673, 0, 0, 4, 421, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2673 = TLBGINVF 7535 { 2674, 0, 0, 4, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2674 = TLBGINVF_MM 7536 { 2675, 0, 0, 4, 1063, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2675 = TLBGINV_MM 7537 { 2676, 0, 0, 4, 422, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2676 = TLBGP 7538 { 2677, 0, 0, 4, 1064, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2677 = TLBGP_MM 7539 { 2678, 0, 0, 4, 423, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2678 = TLBGR 7540 { 2679, 0, 0, 4, 1065, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2679 = TLBGR_MM 7541 { 2680, 0, 0, 4, 424, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2680 = TLBGWI 7542 { 2681, 0, 0, 4, 1066, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2681 = TLBGWI_MM 7543 { 2682, 0, 0, 4, 425, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2682 = TLBGWR 7544 { 2683, 0, 0, 4, 1067, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2683 = TLBGWR_MM 7545 { 2684, 0, 0, 4, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2684 = TLBINV 7546 { 2685, 0, 0, 4, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2685 = TLBINVF 7547 { 2686, 0, 0, 4, 1031, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2686 = TLBINVF_MMR6 7548 { 2687, 0, 0, 4, 1030, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2687 = TLBINV_MMR6 7549 { 2688, 0, 0, 4, 407, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2688 = TLBP 7550 { 2689, 0, 0, 4, 1019, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2689 = TLBP_MM 7551 { 2690, 0, 0, 4, 408, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2690 = TLBR 7552 { 2691, 0, 0, 4, 1020, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2691 = TLBR_MM 7553 { 2692, 0, 0, 4, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2692 = TLBWI 7554 { 2693, 0, 0, 4, 1021, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2693 = TLBWI_MM 7555 { 2694, 0, 0, 4, 410, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2694 = TLBWR 7556 { 2695, 0, 0, 4, 1022, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2695 = TLBWR_MM 7557 { 2696, 3, 0, 4, 392, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2696 = TLT 7558 { 2697, 2, 0, 4, 393, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2697 = TLTI 7559 { 2698, 2, 0, 4, 967, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2698 = TLTIU_MM 7560 { 2699, 2, 0, 4, 968, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2699 = TLTI_MM 7561 { 2700, 3, 0, 4, 394, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2700 = TLTU 7562 { 2701, 3, 0, 4, 969, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2701 = TLTU_MM 7563 { 2702, 3, 0, 4, 970, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2702 = TLT_MM 7564 { 2703, 3, 0, 4, 395, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2703 = TNE 7565 { 2704, 2, 0, 4, 396, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2704 = TNEI 7566 { 2705, 2, 0, 4, 971, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2705 = TNEI_MM 7567 { 2706, 3, 0, 4, 972, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2706 = TNE_MM 7568 { 2707, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2707 = TRUNC_L_D64 7569 { 2708, 2, 1, 4, 1297, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2708 = TRUNC_L_D_MMR6 7570 { 2709, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2709 = TRUNC_L_S 7571 { 2710, 2, 1, 4, 1297, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2710 = TRUNC_L_S_MMR6 7572 { 2711, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #2711 = TRUNC_W_D32 7573 { 2712, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #2712 = TRUNC_W_D64 7574 { 2713, 2, 1, 4, 1297, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #2713 = TRUNC_W_D_MMR6 7575 { 2714, 2, 1, 4, 1245, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #2714 = TRUNC_W_MM 7576 { 2715, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2715 = TRUNC_W_S 7577 { 2716, 2, 1, 4, 1245, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2716 = TRUNC_W_S_MM 7578 { 2717, 2, 1, 4, 1297, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2717 = TRUNC_W_S_MMR6 7579 { 2718, 2, 0, 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2718 = TTLTIU 7580 { 2719, 2, 0, 4, 858, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2719 = UDIV 7581 { 2720, 2, 0, 4, 878, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2720 = UDIV_MM 7582 { 2721, 3, 1, 4, 1200, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList33, OperandInfo64, -1 ,nullptr }, // Inst #2721 = V3MULU 7583 { 2722, 3, 1, 4, 1200, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList25, OperandInfo64, -1 ,nullptr }, // Inst #2722 = VMM0 7584 { 2723, 3, 1, 4, 1200, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList34, OperandInfo64, -1 ,nullptr }, // Inst #2723 = VMULU 7585 { 2724, 4, 1, 4, 510, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #2724 = VSHF_B 7586 { 2725, 4, 1, 4, 510, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2725 = VSHF_D 7587 { 2726, 4, 1, 4, 510, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #2726 = VSHF_H 7588 { 2727, 4, 1, 4, 510, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2727 = VSHF_W 7589 { 2728, 0, 0, 4, 399, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2728 = WAIT 7590 { 2729, 1, 0, 4, 1027, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2729 = WAIT_MM 7591 { 2730, 1, 0, 4, 1044, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2730 = WAIT_MMR6 7592 { 2731, 2, 0, 4, 1446, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2731 = WRDSP 7593 { 2732, 2, 0, 4, 1612, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2732 = WRDSP_MM 7594 { 2733, 2, 1, 4, 1029, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2733 = WRPGPR_MMR6 7595 { 2734, 2, 1, 4, 476, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2734 = WSBH 7596 { 2735, 2, 1, 4, 763, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2735 = WSBH_MM 7597 { 2736, 2, 1, 4, 795, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2736 = WSBH_MMR6 7598 { 2737, 3, 1, 4, 366, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2737 = XOR 7599 { 2738, 3, 1, 2, 764, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2738 = XOR16_MM 7600 { 2739, 3, 1, 2, 796, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2739 = XOR16_MMR6 7601 { 2740, 3, 1, 4, 807, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2740 = XOR64 7602 { 2741, 3, 1, 4, 544, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2741 = XORI_B 7603 { 2742, 3, 1, 4, 797, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2742 = XORI_MMR6 7604 { 2743, 3, 1, 4, 764, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2743 = XOR_MM 7605 { 2744, 3, 1, 4, 796, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2744 = XOR_MMR6 7606 { 2745, 3, 1, 4, 543, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2745 = XOR_V 7607 { 2746, 3, 1, 4, 503, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2746 = XORi 7608 { 2747, 3, 1, 4, 807, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2747 = XORi64 7609 { 2748, 3, 1, 4, 765, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2748 = XORi_MM 7610 { 2749, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2749 = XorRxRxRy16 7611 { 2750, 2, 1, 4, 1057, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2750 = YIELD 7612}; 7613 7614extern const char MipsInstrNameData[] = { 7615 /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0, 7616 /* 9 */ 'D', 'M', 'F', 'C', '0', 0, 7617 /* 15 */ 'D', 'M', 'F', 'G', 'C', '0', 0, 7618 /* 22 */ 'M', 'F', 'H', 'G', 'C', '0', 0, 7619 /* 29 */ 'M', 'T', 'H', 'G', 'C', '0', 0, 7620 /* 36 */ 'D', 'M', 'T', 'G', 'C', '0', 0, 7621 /* 43 */ 'M', 'F', 'T', 'C', '0', 0, 7622 /* 49 */ 'D', 'M', 'T', 'C', '0', 0, 7623 /* 55 */ 'M', 'T', 'T', 'C', '0', 0, 7624 /* 61 */ 'V', 'M', 'M', '0', 0, 7625 /* 66 */ 'M', 'T', 'M', '0', 0, 7626 /* 71 */ 'M', 'T', 'P', '0', 0, 7627 /* 76 */ 'B', 'B', 'I', 'T', '0', 0, 7628 /* 82 */ 'L', 'D', 'C', '1', 0, 7629 /* 87 */ 'S', 'D', 'C', '1', 0, 7630 /* 92 */ 'C', 'F', 'C', '1', 0, 7631 /* 97 */ 'D', 'M', 'F', 'C', '1', 0, 7632 /* 103 */ 'M', 'F', 'T', 'H', 'C', '1', 0, 7633 /* 110 */ 'M', 'T', 'T', 'H', 'C', '1', 0, 7634 /* 117 */ 'C', 'T', 'C', '1', 0, 7635 /* 122 */ 'C', 'F', 'T', 'C', '1', 0, 7636 /* 128 */ 'M', 'F', 'T', 'C', '1', 0, 7637 /* 134 */ 'D', 'M', 'T', 'C', '1', 0, 7638 /* 140 */ 'C', 'T', 'T', 'C', '1', 0, 7639 /* 146 */ 'M', 'T', 'T', 'C', '1', 0, 7640 /* 152 */ 'L', 'W', 'C', '1', 0, 7641 /* 157 */ 'S', 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25741 */ 'U', 'l', 'h', 0, 10090 /* 25745 */ 'U', 's', 'h', 0, 10091 /* 25749 */ 'D', 'A', 'D', 'D', 'i', 0, 10092 /* 25755 */ 'A', 'N', 'D', 'i', 0, 10093 /* 25760 */ 'S', 'N', 'E', 'i', 0, 10094 /* 25765 */ 'S', 'E', 'Q', 'i', 0, 10095 /* 25770 */ 'X', 'O', 'R', 'i', 0, 10096 /* 25775 */ 'S', 'L', 'T', 'i', 0, 10097 /* 25780 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', 0, 10098 /* 25796 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'C', 'm', 'p', 'i', 0, 10099 /* 25810 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'C', 'm', 'p', 'i', 0, 10100 /* 25824 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'i', 0, 10101 /* 25838 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'i', 0, 10102 /* 25852 */ 'S', 'G', 'E', 'I', 'm', 'm', 0, 10103 /* 25859 */ 'D', 'R', 'O', 'L', 'I', 'm', 'm', 0, 10104 /* 25867 */ 'N', 'O', 'R', 'I', 'm', 'm', 0, 10105 /* 25874 */ 'D', 'R', 'O', 'R', 'I', 'm', 'm', 0, 10106 /* 25882 */ 'S', 'G', 'T', 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5627U, 10399 5880U, 16949U, 19132U, 9727U, 2000U, 19023U, 19095U, 25541U, 10400 20156U, 18237U, 10898U, 2063U, 5713U, 10877U, 2057U, 5694U, 10401 22183U, 16922U, 3261U, 21826U, 16790U, 5378U, 6926U, 9721U, 10402 1992U, 7884U, 7919U, 19017U, 18223U, 4706U, 3746U, 4639U, 10403 4631U, 4845U, 4677U, 9735U, 2010U, 12849U, 17479U, 16969U, 10404 25546U, 20164U, 7663U, 17138U, 5641U, 26592U, 3689U, 13161U, 10405 17625U, 20281U, 11348U, 82U, 1924U, 5330U, 15733U, 1131U, 10406 5248U, 7852U, 1889U, 10236U, 11789U, 14118U, 24266U, 15248U, 10407 11038U, 21992U, 162U, 1938U, 10185U, 11590U, 14067U, 24066U, 10408 26676U, 3708U, 20334U, 13471U, 2780U, 12975U, 17535U, 16998U, 10409 25537U, 20149U, 17699U, 26614U, 3695U, 13166U, 17633U, 20304U, 10410 16846U, 5473U, 15414U, 3207U, 7903U, 11351U, 7941U, 13010U, 10411 17549U, 18415U, 6808U, 7965U, 9666U, 5609U, 7912U, 6762U, 10412 174U, 1954U, 15797U, 25792U, 3562U, 20274U, 23919U, 17007U, 10413 3351U, 152U, 15781U, 1153U, 5310U, 7868U, 1899U, 21673U, 10414 18641U, 13137U, 17611U, 18583U, 15612U, 3223U, 13014U, 17556U, 10415 18464U, 16883U, 5518U, 16312U, 11070U, 5860U, 18817U, 22377U, 10416 3293U, 13083U, 17586U, 19081U, 18793U, 11064U, 19711U, 25551U, 10417 186U, 15815U, 19141U, 20172U, 19826U, 7764U, 26648U, 4115U, 10418 4179U, 4147U, 4196U, 4725U, 4466U, 4351U, 4825U, 4482U, 10419 4232U, 4294U, 11303U, 11751U, 6222U, 22721U, 7182U, 14318U, 10420 24565U, 23600U, 21806U, 18756U, 19668U, 10822U, 12759U, 14842U, 10421 25398U, 294U, 15897U, 2253U, 21694U, 18671U, 17464U, 14291U, 10422 24538U, 22616U, 19207U, 15342U, 18345U, 22117U, 18953U, 15368U, 10423 18377U, 22143U, 18985U, 11503U, 6108U, 22586U, 7044U, 10526U, 10424 12270U, 14471U, 24871U, 10718U, 12635U, 14729U, 25265U, 10162U, 10425 11537U, 14044U, 24013U, 12814U, 6574U, 23189U, 10605U, 12378U, 10426 14578U, 7583U, 25048U, 10797U, 12743U, 14817U, 25373U, 10U, 10427 5186U, 98U, 2160U, 15757U, 5228U, 1142U, 5268U, 16U, 10428 15695U, 5196U, 245U, 15833U, 2169U, 16369U, 5278U, 22U, 10429 15704U, 14914U, 16836U, 2796U, 21734U, 18683U, 18116U, 21436U, 10430 16901U, 3241U, 21769U, 18707U, 18505U, 22331U, 11490U, 6096U, 10431 22579U, 7032U, 10508U, 12252U, 14453U, 24853U, 10700U, 12617U, 10432 14711U, 25247U, 10145U, 11519U, 14027U, 23995U, 11963U, 6318U, 10433 22869U, 10535U, 12279U, 14480U, 7302U, 24889U, 10727U, 12644U, 10434 14738U, 25274U, 11450U, 10067U, 17379U, 23607U, 7692U, 6087U, 10435 10475U, 12219U, 14420U, 24820U, 10667U, 12584U, 14678U, 25214U, 10436 16808U, 5439U, 18565U, 6904U, 23854U, 362U, 15986U, 2321U, 10437 15034U, 2932U, 18183U, 22736U, 19282U, 2198U, 15012U, 2825U, 10438 22557U, 409U, 16021U, 2368U, 15060U, 2962U, 18193U, 22783U, 10439 19311U, 602U, 16251U, 2618U, 15110U, 3136U, 18203U, 23096U, 10440 19495U, 2211U, 15023U, 2838U, 22568U, 420U, 16035U, 2379U, 10441 15069U, 2973U, 18213U, 22792U, 19323U, 10104U, 11743U, 6209U, 10442 22713U, 7169U, 14308U, 24555U, 23588U, 21796U, 18743U, 19653U, 10443 10814U, 12751U, 14834U, 25390U, 275U, 15872U, 2234U, 21685U, 10444 18659U, 17395U, 14282U, 24529U, 22601U, 19186U, 50U, 5218U, 10445 135U, 2189U, 16395U, 15773U, 5238U, 1148U, 5300U, 37U, 10446 15724U, 5207U, 255U, 15846U, 2179U, 16382U, 5289U, 29U, 10447 15714U, 14944U, 2818U, 21760U, 18695U, 18140U, 21553U, 18591U, 10448 21453U, 3248U, 21778U, 18719U, 18522U, 66U, 198U, 1171U, 10449 71U, 211U, 1176U, 22353U, 14009U, 23633U, 7702U, 6705U, 10450 15583U, 15380U, 18392U, 22155U, 19000U, 15182U, 18264U, 21888U, 10451 18853U, 13695U, 17872U, 24722U, 1860U, 13745U, 1517U, 24924U, 10452 1875U, 14328U, 24575U, 13933U, 18016U, 13873U, 1616U, 23370U, 10453 21816U, 18769U, 21787U, 18731U, 19632U, 26630U, 20325U, 23653U, 10454 7723U, 10846U, 12790U, 14866U, 25429U, 18457U, 6825U, 13613U, 10455 1459U, 14300U, 24547U, 7972U, 13716U, 1503U, 4691U, 4818U, 10456 4005U, 3728U, 10170U, 11560U, 14052U, 24036U, 10177U, 11567U, 10457 14059U, 24043U, 293U, 15896U, 2252U, 22615U, 19206U, 274U, 10458 15871U, 2233U, 22600U, 19185U, 22191U, 3273U, 10319U, 19031U, 10459 6970U, 23868U, 16960U, 5564U, 4886U, 4927U, 22192U, 16941U, 10460 5554U, 3274U, 10320U, 6744U, 19032U, 6971U, 23869U, 25771U, 10461 3549U, 20259U, 5026U, 13603U, 17797U, 13106U, 17602U, 6636U, 10462 10830U, 12767U, 14850U, 25406U, 10190U, 11595U, 14072U, 24071U, 10463 10637U, 12480U, 14610U, 25110U, 13571U, 17764U, 9812U, 17173U, 10464 3305U, 3314U, 21581U, 15211U, 8325U, 17061U, 18299U, 21917U, 10465 8362U, 17098U, 18888U, 15355U, 18361U, 22130U, 18969U, 15197U, 10466 8310U, 17043U, 18282U, 21903U, 8347U, 17080U, 18871U, 13515U, 10467 17732U, 24198U, 19886U, 13490U, 17716U, 24227U, 19901U, 13503U, 10468 1401U, 24183U, 1762U, 24210U, 1782U, 13227U, 12951U, 17510U, 10469 20140U, 17649U, 6647U, 7957U, 11394U, 1376U, 10053U, 17359U, 10470 21647U, 18623U, 22371U, 3285U, 19072U, 7012U, 6988U, 459U, 10471 16086U, 2475U, 16581U, 22901U, 19377U, 13846U, 17989U, 10035U, 10472 17335U, 13587U, 17786U, 9828U, 17195U, 12488U, 6491U, 23073U, 10473 7475U, 22337U, 23837U, 19809U, 19045U, 2421U, 6261U, 22832U, 10474 7245U, 668U, 2678U, 6530U, 19875U, 23152U, 19538U, 7526U, 10475 592U, 16238U, 2608U, 16721U, 23088U, 19484U, 4646U, 4022U, 10476 8306U, 11162U, 10570U, 12323U, 14533U, 24969U, 10773U, 12699U, 10477 14793U, 25329U, 10064U, 16782U, 5358U, 2015U, 12853U, 17486U, 10478 17373U, 5649U, 11083U, 2078U, 7895U, 11264U, 7934U, 12894U, 10479 17493U, 17425U, 5891U, 7928U, 11471U, 21511U, 16911U, 5540U, 10480 18538U, 6893U, 7987U, 87U, 1931U, 5344U, 15741U, 1136U, 10481 5258U, 7860U, 1894U, 23735U, 19736U, 15252U, 21996U, 168U, 10482 1946U, 9699U, 1970U, 17124U, 13462U, 2774U, 17692U, 25633U, 10483 3384U, 12840U, 6599U, 7814U, 23204U, 7608U, 25600U, 3375U, 10484 12825U, 6585U, 7793U, 23195U, 7594U, 11899U, 6235U, 22801U, 10485 7207U, 21875U, 25765U, 14005U, 16818U, 5451U, 2785U, 12979U, 10486 17542U, 10215U, 14097U, 24170U, 21441U, 23815U, 19779U, 18513U, 10487 13837U, 17977U, 10026U, 17323U, 13785U, 17938U, 25038U, 20116U, 10488 13579U, 17775U, 9820U, 17184U, 13706U, 17886U, 24880U, 20057U, 10489 13828U, 17965U, 10017U, 1362U, 13684U, 17858U, 9918U, 1313U, 10490 24695U, 20004U, 13482U, 17705U, 9738U, 1189U, 13652U, 17845U, 10491 9886U, 1266U, 24657U, 19980U, 13855U, 1588U, 10044U, 17347U, 10492 13595U, 1446U, 9836U, 17206U, 18048U, 6697U, 12983U, 6624U, 10493 10235U, 11788U, 14117U, 24265U, 10184U, 11589U, 14066U, 24065U, 10494 15535U, 16865U, 5496U, 1006U, 3444U, 10265U, 11803U, 14132U, 10495 24280U, 23789U, 19752U, 10397U, 11912U, 14235U, 18443U, 6816U, 10496 24383U, 23355U, 3334U, 19612U, 25775U, 3555U, 20266U, 26704U, 10497 3720U, 20347U, 26618U, 3701U, 20311U, 13028U, 25760U, 10342U, 10498 11866U, 14195U, 24343U, 10622U, 12395U, 14595U, 25065U, 8379U, 10499 10228U, 11781U, 14110U, 24258U, 10295U, 11833U, 14162U, 24310U, 10500 10430U, 12079U, 14337U, 24584U, 23704U, 19718U, 10131U, 11497U, 10501 14013U, 17117U, 23980U, 15550U, 16874U, 5507U, 10272U, 11810U, 10502 14139U, 24287U, 10311U, 11849U, 14178U, 24326U, 10444U, 12093U, 10503 14351U, 24598U, 23795U, 19760U, 10403U, 11934U, 14241U, 18450U, 10504 24405U, 21574U, 18601U, 6915U, 10653U, 12521U, 14626U, 25151U, 10505 10070U, 13547U, 1418U, 13662U, 1471U, 24666U, 1830U, 24242U, 10506 1804U, 13620U, 17810U, 13725U, 17899U, 24906U, 20069U, 10762U, 10507 12688U, 14782U, 25318U, 10586U, 12359U, 14549U, 25019U, 10552U, 10508 12305U, 14515U, 24951U, 10744U, 12670U, 14764U, 25300U, 16978U, 10509 5575U, 9788U, 1220U, 9896U, 1281U, 7672U, 13812U, 1562U, 10510 10001U, 17301U, 13765U, 1532U, 9939U, 17246U, 10359U, 11883U, 10511 14212U, 24360U, 10815U, 12752U, 14835U, 25391U, 17382U, 5657U, 10512 26597U, 20288U, 180U, 1962U, 15806U, 23929U, 17015U, 5599U, 10513 3356U, 157U, 15789U, 1158U, 5320U, 7876U, 1904U, 21679U, 10514 18650U, 13141U, 17618U, 15616U, 3229U, 13019U, 17564U, 18471U, 10515 16892U, 5529U, 16321U, 18824U, 22381U, 3299U, 13088U, 17594U, 10516 19088U, 18801U, 6942U, 192U, 15824U, 19832U, 7772U, 11016U, 10517 14884U, 18079U, 6714U, 17403U, 5814U, 15425U, 18432U, 4670U, 10518 4033U, 4131U, 4837U, 4853U, 4163U, 4101U, 4992U, 4906U, 10519 4747U, 4375U, 4759U, 4402U, 4937U, 4015U, 4971U, 4108U, 10520 5003U, 5062U, 4248U, 4307U, 21879U, 14955U, 18148U, 18838U, 10521 12965U, 14893U, 23638U, 19685U, 18094U, 23622U, 19677U, 17519U, 10522 23807U, 13240U, 17657U, 19768U, 21547U, 18574U, 22077U, 18944U, 10523 15005U, 18173U, 22364U, 19062U, 23800U, 13232U, 6657U, 7752U, 10524 21517U, 18547U, 21883U, 18845U, 14999U, 18164U, 22358U, 19053U, 10525 23359U, 14974U, 19694U, 18156U, 23686U, 19703U, 19619U, 13032U, 10526 14898U, 18102U, 17579U, 2409U, 6246U, 22822U, 7230U, 656U, 10527 2666U, 6515U, 19864U, 23142U, 19525U, 7511U, 23644U, 23765U, 10528 19744U, 23651U, 61U, 23664U, 10214U, 11759U, 14096U, 24169U, 10529 23274U, 19604U, 7633U, 21653U, 18632U, 7000U, 13449U, 17684U, 10530 6687U, 22243U, 16940U, 5553U, 3279U, 10326U, 6743U, 19038U, 10531 6979U, 23874U, 25770U, 3548U, 20258U, 5037U, 11345U, 10532}; 10533 10534static inline void InitMipsMCInstrInfo(MCInstrInfo *II) { 10535 II->InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, 2751); 10536} 10537 10538} // end namespace llvm 10539#endif // GET_INSTRINFO_MC_DESC 10540 10541#ifdef GET_INSTRINFO_HEADER 10542#undef GET_INSTRINFO_HEADER 10543namespace llvm { 10544struct MipsGenInstrInfo : public TargetInstrInfo { 10545 explicit MipsGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1); 10546 ~MipsGenInstrInfo() override = default; 10547 10548}; 10549} // end namespace llvm 10550#endif // GET_INSTRINFO_HEADER 10551 10552#ifdef GET_INSTRINFO_HELPER_DECLS 10553#undef GET_INSTRINFO_HELPER_DECLS 10554 10555 10556#endif // GET_INSTRINFO_HELPER_DECLS 10557 10558#ifdef GET_INSTRINFO_HELPERS 10559#undef GET_INSTRINFO_HELPERS 10560 10561#endif // GET_INSTRINFO_HELPERS 10562 10563#ifdef GET_INSTRINFO_CTOR_DTOR 10564#undef GET_INSTRINFO_CTOR_DTOR 10565namespace llvm { 10566extern const MCInstrDesc MipsInsts[]; 10567extern const unsigned MipsInstrNameIndices[]; 10568extern const char MipsInstrNameData[]; 10569MipsGenInstrInfo::MipsGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode) 10570 : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { 10571 InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, 2751); 10572} 10573} // end namespace llvm 10574#endif // GET_INSTRINFO_CTOR_DTOR 10575 10576#ifdef GET_INSTRINFO_OPERAND_ENUM 10577#undef GET_INSTRINFO_OPERAND_ENUM 10578namespace llvm { 10579namespace Mips { 10580namespace OpName { 10581enum { 10582OPERAND_LAST 10583}; 10584} // end namespace OpName 10585} // end namespace Mips 10586} // end namespace llvm 10587#endif //GET_INSTRINFO_OPERAND_ENUM 10588 10589#ifdef GET_INSTRINFO_NAMED_OPS 10590#undef GET_INSTRINFO_NAMED_OPS 10591namespace llvm { 10592namespace Mips { 10593LLVM_READONLY 10594int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { 10595 return -1; 10596} 10597} // end namespace Mips 10598} // end namespace llvm 10599#endif //GET_INSTRINFO_NAMED_OPS 10600 10601#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM 10602#undef GET_INSTRINFO_OPERAND_TYPES_ENUM 10603namespace llvm { 10604namespace Mips { 10605namespace OpTypes { 10606enum OperandType { 10607 InvertedImOperand = 0, 10608 InvertedImOperand64 = 1, 10609 PtrRC = 2, 10610 brtarget = 3, 10611 brtarget10_mm = 4, 10612 brtarget1SImm16 = 5, 10613 brtarget21 = 6, 10614 brtarget21_mm = 7, 10615 brtarget26 = 8, 10616 brtarget26_mm = 9, 10617 brtarget7_mm = 10, 10618 brtarget_lsl2_mm = 11, 10619 brtarget_mm = 12, 10620 brtargetr6 = 13, 10621 calloffset16 = 14, 10622 calltarget = 15, 10623 calltarget_mm = 16, 10624 condcode = 17, 10625 cpinst_operand = 18, 10626 f32imm = 19, 10627 f64imm = 20, 10628 i16imm = 21, 10629 i1imm = 22, 10630 i32imm = 23, 10631 i64imm = 24, 10632 i8imm = 25, 10633 imm64 = 26, 10634 jmpoffset16 = 27, 10635 jmptarget = 28, 10636 jmptarget_mm = 29, 10637 li16_imm = 30, 10638 mem = 31, 10639 mem16 = 32, 10640 mem16_ea = 33, 10641 mem16sp = 34, 10642 mem_ea = 35, 10643 mem_mm_11 = 36, 10644 mem_mm_12 = 37, 10645 mem_mm_16 = 38, 10646 mem_mm_4 = 39, 10647 mem_mm_4_lsl1 = 40, 10648 mem_mm_4_lsl2 = 41, 10649 mem_mm_4sp = 42, 10650 mem_mm_9 = 43, 10651 mem_mm_gp_simm7_lsl2 = 44, 10652 mem_mm_sp_imm5_lsl2 = 45, 10653 mem_msa = 46, 10654 mem_simm10 = 47, 10655 mem_simm10_lsl1 = 48, 10656 mem_simm10_lsl2 = 49, 10657 mem_simm10_lsl3 = 50, 10658 mem_simm11 = 51, 10659 mem_simm12 = 52, 10660 mem_simm16 = 53, 10661 mem_simm9 = 54, 10662 mem_simm9_exp = 55, 10663 mem_simmptr = 56, 10664 pcrel16 = 57, 10665 ptype0 = 58, 10666 ptype1 = 59, 10667 ptype2 = 60, 10668 ptype3 = 61, 10669 ptype4 = 62, 10670 ptype5 = 63, 10671 reglist = 64, 10672 reglist16 = 65, 10673 simm10 = 66, 10674 simm10_64 = 67, 10675 simm10_lsl1 = 68, 10676 simm10_lsl2 = 69, 10677 simm10_lsl3 = 70, 10678 simm11 = 71, 10679 simm12 = 72, 10680 simm16 = 73, 10681 simm16_64 = 74, 10682 simm16_relaxed = 75, 10683 simm18_lsl3 = 76, 10684 simm19_lsl2 = 77, 10685 simm23_lsl2 = 78, 10686 simm32 = 79, 10687 simm32_relaxed = 80, 10688 simm3_lsa2 = 81, 10689 simm4 = 82, 10690 simm5 = 83, 10691 simm6 = 84, 10692 simm7_lsl2 = 85, 10693 simm9 = 86, 10694 simm9_addiusp = 87, 10695 size_ins = 88, 10696 type0 = 89, 10697 type1 = 90, 10698 type2 = 91, 10699 type3 = 92, 10700 type4 = 93, 10701 type5 = 94, 10702 uimm1 = 95, 10703 uimm10 = 96, 10704 uimm16 = 97, 10705 uimm16_64 = 98, 10706 uimm16_64_relaxed = 99, 10707 uimm16_altrelaxed = 100, 10708 uimm16_relaxed = 101, 10709 uimm1_ptr = 102, 10710 uimm2 = 103, 10711 uimm20 = 104, 10712 uimm26 = 105, 10713 uimm2_plus1 = 106, 10714 uimm2_ptr = 107, 10715 uimm3 = 108, 10716 uimm32_coerced = 109, 10717 uimm3_ptr = 110, 10718 uimm3_shift = 111, 10719 uimm4 = 112, 10720 uimm4_andi = 113, 10721 uimm4_ptr = 114, 10722 uimm5 = 115, 10723 uimm5_64 = 116, 10724 uimm5_64_report_uimm6 = 117, 10725 uimm5_inssize_plus1 = 118, 10726 uimm5_lsl2 = 119, 10727 uimm5_plus1 = 120, 10728 uimm5_plus1_report_uimm6 = 121, 10729 uimm5_plus32 = 122, 10730 uimm5_plus32_normalize = 123, 10731 uimm5_plus32_normalize_64 = 124, 10732 uimm5_plus33 = 125, 10733 uimm5_report_uimm6 = 126, 10734 uimm6 = 127, 10735 uimm6_lsl2 = 128, 10736 uimm7 = 129, 10737 uimm8 = 130, 10738 uimm_range_2_64 = 131, 10739 uimmz = 132, 10740 untyped_imm_0 = 133, 10741 vsplat_simm10 = 134, 10742 vsplat_simm5 = 135, 10743 vsplat_uimm1 = 136, 10744 vsplat_uimm2 = 137, 10745 vsplat_uimm3 = 138, 10746 vsplat_uimm4 = 139, 10747 vsplat_uimm5 = 140, 10748 vsplat_uimm6 = 141, 10749 vsplat_uimm8 = 142, 10750 ACC64DSPOpnd = 143, 10751 AFGR64Opnd = 144, 10752 CCROpnd = 145, 10753 COP0Opnd = 146, 10754 COP2Opnd = 147, 10755 COP3Opnd = 148, 10756 DSPROpnd = 149, 10757 FCCRegsOpnd = 150, 10758 FGR32Opnd = 151, 10759 FGR64Opnd = 152, 10760 FGRCCOpnd = 153, 10761 GPR32NonZeroOpnd = 154, 10762 GPR32Opnd = 155, 10763 GPR32ZeroOpnd = 156, 10764 GPR64Opnd = 157, 10765 GPRMM16Opnd = 158, 10766 GPRMM16OpndMoveP = 159, 10767 GPRMM16OpndMovePPairFirst = 160, 10768 GPRMM16OpndMovePPairSecond = 161, 10769 GPRMM16OpndZero = 162, 10770 HI32DSPOpnd = 163, 10771 HWRegsOpnd = 164, 10772 LO32DSPOpnd = 165, 10773 MSA128BOpnd = 166, 10774 MSA128CROpnd = 167, 10775 MSA128DOpnd = 168, 10776 MSA128F16Opnd = 169, 10777 MSA128HOpnd = 170, 10778 MSA128WOpnd = 171, 10779 StrictlyAFGR64Opnd = 172, 10780 StrictlyFGR32Opnd = 173, 10781 StrictlyFGR64Opnd = 174, 10782 ACC128 = 175, 10783 ACC64 = 176, 10784 ACC64DSP = 177, 10785 AFGR64 = 178, 10786 CCR = 179, 10787 COP0 = 180, 10788 COP2 = 181, 10789 COP3 = 182, 10790 CPU16Regs = 183, 10791 CPU16RegsPlusSP = 184, 10792 CPURAReg = 185, 10793 CPUSPReg = 186, 10794 DSPCC = 187, 10795 DSPR = 188, 10796 FCC = 189, 10797 FGR32 = 190, 10798 FGR64 = 191, 10799 FGRCC = 192, 10800 GP32 = 193, 10801 GP64 = 194, 10802 GPR32 = 195, 10803 GPR32NONZERO = 196, 10804 GPR32ZERO = 197, 10805 GPR64 = 198, 10806 GPRMM16 = 199, 10807 GPRMM16MoveP = 200, 10808 GPRMM16MovePPairFirst = 201, 10809 GPRMM16MovePPairSecond = 202, 10810 GPRMM16Zero = 203, 10811 HI32 = 204, 10812 HI32DSP = 205, 10813 HI64 = 206, 10814 HWRegs = 207, 10815 LO32 = 208, 10816 LO32DSP = 209, 10817 LO64 = 210, 10818 MSA128B = 211, 10819 MSA128D = 212, 10820 MSA128F16 = 213, 10821 MSA128H = 214, 10822 MSA128W = 215, 10823 MSA128WEvens = 216, 10824 MSACtrl = 217, 10825 OCTEON_MPL = 218, 10826 OCTEON_P = 219, 10827 SP32 = 220, 10828 SP64 = 221, 10829 OPERAND_TYPE_LIST_END 10830}; 10831} // end namespace OpTypes 10832} // end namespace Mips 10833} // end namespace llvm 10834#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM 10835 10836#ifdef GET_INSTRINFO_OPERAND_TYPE 10837#undef GET_INSTRINFO_OPERAND_TYPE 10838namespace llvm { 10839namespace Mips { 10840LLVM_READONLY 10841static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { 10842 const int Offsets[] = { 10843 0, 10844 1, 10845 1, 10846 1, 10847 2, 10848 3, 10849 4, 10850 5, 10851 5, 10852 8, 10853 12, 10854 13, 10855 17, 10856 20, 10857 20, 10858 21, 10859 23, 10860 25, 10861 25, 10862 26, 10863 27, 10864 29, 10865 29, 10866 35, 10867 36, 10868 36, 10869 38, 10870 39, 10871 39, 10872 39, 10873 39, 10874 39, 10875 39, 10876 41, 10877 44, 10878 44, 10879 47, 10880 50, 10881 53, 10882 56, 10883 59, 10884 62, 10885 65, 10886 68, 10887 71, 10888 74, 10889 75, 10890 76, 10891 78, 10892 80, 10893 83, 10894 85, 10895 89, 10896 91, 10897 93, 10898 95, 10899 97, 10900 99, 10901 101, 10902 103, 10903 105, 10904 107, 10905 108, 10906 110, 10907 112, 10908 114, 10909 119, 10910 124, 10911 129, 10912 131, 10913 136, 10914 141, 10915 145, 10916 148, 10917 151, 10918 154, 10919 157, 10920 160, 10921 163, 10922 166, 10923 169, 10924 172, 10925 175, 10926 178, 10927 181, 10928 184, 10929 186, 10930 188, 10931 189, 10932 190, 10933 191, 10934 193, 10935 195, 10936 197, 10937 199, 10938 200, 10939 203, 10940 205, 10941 208, 10942 210, 10943 213, 10944 216, 10945 219, 10946 223, 10947 227, 10948 231, 10949 235, 10950 240, 10951 244, 10952 249, 10953 253, 10954 258, 10955 262, 10956 267, 10957 271, 10958 275, 10959 278, 10960 281, 10961 284, 10962 287, 10963 290, 10964 294, 10965 298, 10966 301, 10967 304, 10968 307, 10969 309, 10970 311, 10971 313, 10972 315, 10973 317, 10974 319, 10975 321, 10976 323, 10977 325, 10978 327, 10979 329, 10980 331, 10981 333, 10982 336, 10983 338, 10984 341, 10985 344, 10986 347, 10987 350, 10988 353, 10989 356, 10990 359, 10991 362, 10992 365, 10993 368, 10994 371, 10995 374, 10996 375, 10997 378, 10998 382, 10999 385, 11000 389, 11001 391, 11002 393, 11003 395, 11004 397, 11005 399, 11006 401, 11007 403, 11008 405, 11009 407, 11010 409, 11011 411, 11012 413, 11013 415, 11014 417, 11015 419, 11016 421, 11017 423, 11018 426, 11019 428, 11020 430, 11021 432, 11022 434, 11023 436, 11024 439, 11025 442, 11026 445, 11027 449, 11028 456, 11029 460, 11030 464, 11031 468, 11032 472, 11033 476, 11034 483, 11035 486, 11036 492, 11037 495, 11038 498, 11039 501, 11040 504, 11041 507, 11042 513, 11043 516, 11044 522, 11045 525, 11046 528, 11047 531, 11048 534, 11049 537, 11050 543, 11051 546, 11052 552, 11053 555, 11054 558, 11055 561, 11056 564, 11057 567, 11058 573, 11059 576, 11060 582, 11061 585, 11062 588, 11063 591, 11064 594, 11065 597, 11066 603, 11067 606, 11068 612, 11069 615, 11070 618, 11071 621, 11072 624, 11073 627, 11074 633, 11075 636, 11076 642, 11077 645, 11078 648, 11079 651, 11080 654, 11081 657, 11082 663, 11083 666, 11084 672, 11085 675, 11086 678, 11087 681, 11088 684, 11089 687, 11090 693, 11091 696, 11092 702, 11093 705, 11094 708, 11095 711, 11096 714, 11097 717, 11098 723, 11099 726, 11100 732, 11101 735, 11102 738, 11103 741, 11104 744, 11105 747, 11106 753, 11107 756, 11108 762, 11109 765, 11110 768, 11111 771, 11112 774, 11113 777, 11114 783, 11115 786, 11116 792, 11117 795, 11118 798, 11119 801, 11120 804, 11121 807, 11122 813, 11123 814, 11124 815, 11125 816, 11126 819, 11127 822, 11128 825, 11129 828, 11130 831, 11131 834, 11132 837, 11133 840, 11134 843, 11135 846, 11136 849, 11137 852, 11138 855, 11139 858, 11140 861, 11141 864, 11142 867, 11143 870, 11144 873, 11145 876, 11146 879, 11147 882, 11148 885, 11149 888, 11150 891, 11151 894, 11152 897, 11153 900, 11154 903, 11155 906, 11156 909, 11157 912, 11158 915, 11159 918, 11160 919, 11161 923, 11162 927, 11163 931, 11164 935, 11165 939, 11166 940, 11167 941, 11168 942, 11169 945, 11170 948, 11171 951, 11172 954, 11173 957, 11174 960, 11175 963, 11176 966, 11177 969, 11178 972, 11179 975, 11180 978, 11181 981, 11182 984, 11183 987, 11184 990, 11185 992, 11186 995, 11187 998, 11188 1001, 11189 1003, 11190 1004, 11191 1007, 11192 1010, 11193 1013, 11194 1016, 11195 1019, 11196 1022, 11197 1025, 11198 1028, 11199 1031, 11200 1034, 11201 1037, 11202 1040, 11203 1043, 11204 1046, 11205 1049, 11206 1052, 11207 1052, 11208 1055, 11209 1058, 11210 1060, 11211 1062, 11212 1064, 11213 1066, 11214 1068, 11215 1070, 11216 1074, 11217 1078, 11218 1082, 11219 1086, 11220 1090, 11221 1094, 11222 1098, 11223 1102, 11224 1106, 11225 1110, 11226 1114, 11227 1118, 11228 1122, 11229 1126, 11230 1130, 11231 1131, 11232 1132, 11233 1133, 11234 1134, 11235 1135, 11236 1136, 11237 1138, 11238 1141, 11239 1144, 11240 1147, 11241 1150, 11242 1153, 11243 1156, 11244 1160, 11245 1163, 11246 1167, 11247 1170, 11248 1173, 11249 1175, 11250 1177, 11251 1180, 11252 1182, 11253 1184, 11254 1187, 11255 1190, 11256 1192, 11257 1194, 11258 1196, 11259 1198, 11260 1200, 11261 1202, 11262 1204, 11263 1207, 11264 1209, 11265 1212, 11266 1214, 11267 1215, 11268 1218, 11269 1220, 11270 1222, 11271 1224, 11272 1226, 11273 1228, 11274 1230, 11275 1232, 11276 1234, 11277 1236, 11278 1238, 11279 1241, 11280 1243, 11281 1244, 11282 1246, 11283 1248, 11284 1250, 11285 1252, 11286 1255, 11287 1258, 11288 1261, 11289 1263, 11290 1266, 11291 1268, 11292 1271, 11293 1271, 11294 1274, 11295 1277, 11296 1280, 11297 1283, 11298 1286, 11299 1289, 11300 1292, 11301 1295, 11302 1298, 11303 1301, 11304 1304, 11305 1307, 11306 1310, 11307 1313, 11308 1315, 11309 1317, 11310 1319, 11311 1321, 11312 1323, 11313 1326, 11314 1329, 11315 1332, 11316 1335, 11317 1342, 11318 1349, 11319 1350, 11320 1351, 11321 1352, 11322 1353, 11323 1354, 11324 1355, 11325 1356, 11326 1357, 11327 1358, 11328 1359, 11329 1363, 11330 1367, 11331 1371, 11332 1375, 11333 1377, 11334 1379, 11335 1381, 11336 1383, 11337 1385, 11338 1387, 11339 1391, 11340 1395, 11341 1399, 11342 1403, 11343 1406, 11344 1409, 11345 1412, 11346 1415, 11347 1418, 11348 1421, 11349 1424, 11350 1427, 11351 1431, 11352 1435, 11353 1436, 11354 1437, 11355 1440, 11356 1444, 11357 1448, 11358 1452, 11359 1456, 11360 1460, 11361 1464, 11362 1468, 11363 1472, 11364 1476, 11365 1480, 11366 1484, 11367 1488, 11368 1492, 11369 1496, 11370 1500, 11371 1503, 11372 1506, 11373 1509, 11374 1512, 11375 1515, 11376 1518, 11377 1521, 11378 1524, 11379 1524, 11380 1524, 11381 1527, 11382 1530, 11383 1533, 11384 1536, 11385 1539, 11386 1542, 11387 1545, 11388 1548, 11389 1551, 11390 1554, 11391 1557, 11392 1560, 11393 1563, 11394 1566, 11395 1569, 11396 1572, 11397 1575, 11398 1578, 11399 1581, 11400 1583, 11401 1585, 11402 1587, 11403 1589, 11404 1591, 11405 1594, 11406 1597, 11407 1600, 11408 1603, 11409 1606, 11410 1609, 11411 1612, 11412 1615, 11413 1617, 11414 1619, 11415 1621, 11416 1623, 11417 1625, 11418 1628, 11419 1631, 11420 1635, 11421 1639, 11422 1644, 11423 1649, 11424 1654, 11425 1659, 11426 1664, 11427 1669, 11428 1674, 11429 1679, 11430 1684, 11431 1689, 11432 1694, 11433 1699, 11434 1702, 11435 1705, 11436 1708, 11437 1711, 11438 1714, 11439 1715, 11440 1716, 11441 1717, 11442 1718, 11443 1719, 11444 1720, 11445 1721, 11446 1722, 11447 1723, 11448 1724, 11449 1725, 11450 1726, 11451 1727, 11452 1727, 11453 1727, 11454 1730, 11455 1733, 11456 1736, 11457 1739, 11458 1742, 11459 1745, 11460 1748, 11461 1751, 11462 1754, 11463 1757, 11464 1760, 11465 1763, 11466 1766, 11467 1768, 11468 1770, 11469 1772, 11470 1774, 11471 1776, 11472 1778, 11473 1781, 11474 1783, 11475 1785, 11476 1787, 11477 1789, 11478 1792, 11479 1795, 11480 1796, 11481 1799, 11482 1802, 11483 1805, 11484 1808, 11485 1811, 11486 1814, 11487 1817, 11488 1820, 11489 1823, 11490 1826, 11491 1829, 11492 1832, 11493 1835, 11494 1838, 11495 1841, 11496 1844, 11497 1847, 11498 1850, 11499 1853, 11500 1856, 11501 1859, 11502 1862, 11503 1865, 11504 1868, 11505 1871, 11506 1874, 11507 1877, 11508 1880, 11509 1883, 11510 1886, 11511 1889, 11512 1892, 11513 1895, 11514 1898, 11515 1901, 11516 1904, 11517 1907, 11518 1910, 11519 1913, 11520 1916, 11521 1919, 11522 1922, 11523 1925, 11524 1928, 11525 1931, 11526 1934, 11527 1937, 11528 1940, 11529 1943, 11530 1946, 11531 1949, 11532 1952, 11533 1955, 11534 1958, 11535 1961, 11536 1964, 11537 1967, 11538 1970, 11539 1973, 11540 1976, 11541 1979, 11542 1982, 11543 1985, 11544 1988, 11545 1991, 11546 1994, 11547 1998, 11548 2002, 11549 2004, 11550 2006, 11551 2009, 11552 2012, 11553 2015, 11554 2018, 11555 2021, 11556 2024, 11557 2027, 11558 2030, 11559 2033, 11560 2036, 11561 2039, 11562 2042, 11563 2045, 11564 2048, 11565 2052, 11566 2056, 11567 2059, 11568 2062, 11569 2065, 11570 2068, 11571 2071, 11572 2074, 11573 2077, 11574 2080, 11575 2083, 11576 2085, 11577 2087, 11578 2090, 11579 2093, 11580 2096, 11581 2099, 11582 2102, 11583 2105, 11584 2108, 11585 2111, 11586 2114, 11587 2117, 11588 2120, 11589 2123, 11590 2126, 11591 2129, 11592 2132, 11593 2135, 11594 2138, 11595 2140, 11596 2142, 11597 2145, 11598 2148, 11599 2151, 11600 2152, 11601 2153, 11602 2156, 11603 2159, 11604 2160, 11605 2163, 11606 2164, 11607 2165, 11608 2166, 11609 2170, 11610 2174, 11611 2177, 11612 2180, 11613 2183, 11614 2186, 11615 2187, 11616 2188, 11617 2190, 11618 2192, 11619 2194, 11620 2196, 11621 2198, 11622 2200, 11623 2202, 11624 2204, 11625 2206, 11626 2208, 11627 2210, 11628 2212, 11629 2214, 11630 2216, 11631 2219, 11632 2222, 11633 2225, 11634 2228, 11635 2231, 11636 2234, 11637 2237, 11638 2240, 11639 2241, 11640 2244, 11641 2247, 11642 2250, 11643 2253, 11644 2256, 11645 2259, 11646 2261, 11647 2263, 11648 2265, 11649 2267, 11650 2269, 11651 2271, 11652 2273, 11653 2275, 11654 2278, 11655 2281, 11656 2284, 11657 2287, 11658 2290, 11659 2293, 11660 2296, 11661 2298, 11662 2300, 11663 2302, 11664 2304, 11665 2306, 11666 2308, 11667 2310, 11668 2312, 11669 2314, 11670 2316, 11671 2318, 11672 2320, 11673 2322, 11674 2324, 11675 2326, 11676 2328, 11677 2330, 11678 2332, 11679 2334, 11680 2336, 11681 2338, 11682 2340, 11683 2344, 11684 2348, 11685 2352, 11686 2356, 11687 2360, 11688 2364, 11689 2368, 11690 2372, 11691 2376, 11692 2380, 11693 2384, 11694 2388, 11695 2392, 11696 2396, 11697 2400, 11698 2404, 11699 2406, 11700 2408, 11701 2410, 11702 2412, 11703 2414, 11704 2416, 11705 2418, 11706 2420, 11707 2422, 11708 2424, 11709 2426, 11710 2428, 11711 2430, 11712 2433, 11713 2436, 11714 2439, 11715 2442, 11716 2445, 11717 2448, 11718 2450, 11719 2452, 11720 2454, 11721 2456, 11722 2458, 11723 2460, 11724 2462, 11725 2464, 11726 2466, 11727 2468, 11728 2470, 11729 2472, 11730 2474, 11731 2478, 11732 2482, 11733 2486, 11734 2490, 11735 2493, 11736 2496, 11737 2499, 11738 2502, 11739 2505, 11740 2508, 11741 2511, 11742 2514, 11743 2517, 11744 2520, 11745 2523, 11746 2526, 11747 2529, 11748 2532, 11749 2534, 11750 2536, 11751 2538, 11752 2540, 11753 2542, 11754 2544, 11755 2546, 11756 2548, 11757 2551, 11758 2554, 11759 2557, 11760 2559, 11761 2561, 11762 2563, 11763 2565, 11764 2567, 11765 2570, 11766 2573, 11767 2574, 11768 2575, 11769 2576, 11770 2578, 11771 2579, 11772 2580, 11773 2582, 11774 2584, 11775 2588, 11776 2592, 11777 2595, 11778 2598, 11779 2601, 11780 2604, 11781 2607, 11782 2610, 11783 2613, 11784 2616, 11785 2618, 11786 2620, 11787 2622, 11788 2624, 11789 2626, 11790 2628, 11791 2630, 11792 2631, 11793 2632, 11794 2634, 11795 2636, 11796 2636, 11797 2637, 11798 2638, 11799 2639, 11800 2640, 11801 2643, 11802 2646, 11803 2649, 11804 2652, 11805 2655, 11806 2658, 11807 2660, 11808 2662, 11809 2664, 11810 2666, 11811 2668, 11812 2670, 11813 2672, 11814 2674, 11815 2676, 11816 2678, 11817 2680, 11818 2683, 11819 2686, 11820 2689, 11821 2692, 11822 2695, 11823 2698, 11824 2701, 11825 2704, 11826 2706, 11827 2708, 11828 2710, 11829 2712, 11830 2716, 11831 2720, 11832 2724, 11833 2728, 11834 2730, 11835 2732, 11836 2734, 11837 2736, 11838 2739, 11839 2742, 11840 2745, 11841 2748, 11842 2751, 11843 2754, 11844 2757, 11845 2760, 11846 2763, 11847 2766, 11848 2769, 11849 2772, 11850 2775, 11851 2778, 11852 2781, 11853 2784, 11854 2786, 11855 2788, 11856 2790, 11857 2792, 11858 2795, 11859 2798, 11860 2801, 11861 2804, 11862 2807, 11863 2810, 11864 2813, 11865 2816, 11866 2819, 11867 2822, 11868 2825, 11869 2828, 11870 2831, 11871 2834, 11872 2837, 11873 2840, 11874 2842, 11875 2844, 11876 2846, 11877 2848, 11878 2851, 11879 2854, 11880 2857, 11881 2860, 11882 2863, 11883 2866, 11884 2869, 11885 2872, 11886 2875, 11887 2878, 11888 2881, 11889 2884, 11890 2886, 11891 2888, 11892 2890, 11893 2892, 11894 2894, 11895 2896, 11896 2899, 11897 2902, 11898 2905, 11899 2908, 11900 2910, 11901 2912, 11902 2915, 11903 2918, 11904 2921, 11905 2924, 11906 2927, 11907 2930, 11908 2932, 11909 2934, 11910 2937, 11911 2940, 11912 2943, 11913 2946, 11914 2948, 11915 2950, 11916 2953, 11917 2956, 11918 2959, 11919 2962, 11920 2965, 11921 2968, 11922 2971, 11923 2974, 11924 2977, 11925 2980, 11926 2983, 11927 2986, 11928 2989, 11929 2992, 11930 2995, 11931 2998, 11932 3001, 11933 3004, 11934 3007, 11935 3010, 11936 3013, 11937 3016, 11938 3019, 11939 3022, 11940 3025, 11941 3028, 11942 3031, 11943 3034, 11944 3037, 11945 3040, 11946 3043, 11947 3046, 11948 3049, 11949 3052, 11950 3055, 11951 3058, 11952 3061, 11953 3064, 11954 3067, 11955 3070, 11956 3073, 11957 3076, 11958 3079, 11959 3082, 11960 3085, 11961 3088, 11962 3091, 11963 3094, 11964 3097, 11965 3100, 11966 3103, 11967 3106, 11968 3109, 11969 3112, 11970 3115, 11971 3118, 11972 3121, 11973 3124, 11974 3127, 11975 3130, 11976 3133, 11977 3136, 11978 3139, 11979 3142, 11980 3145, 11981 3147, 11982 3149, 11983 3151, 11984 3153, 11985 3155, 11986 3157, 11987 3159, 11988 3161, 11989 3163, 11990 3165, 11991 3167, 11992 3169, 11993 3171, 11994 3173, 11995 3175, 11996 3177, 11997 3179, 11998 3181, 11999 3183, 12000 3185, 12001 3188, 12002 3190, 12003 3192, 12004 3194, 12005 3196, 12006 3198, 12007 3200, 12008 3202, 12009 3204, 12010 3206, 12011 3208, 12012 3210, 12013 3212, 12014 3214, 12015 3216, 12016 3218, 12017 3220, 12018 3222, 12019 3224, 12020 3227, 12021 3230, 12022 3233, 12023 3236, 12024 3239, 12025 3242, 12026 3245, 12027 3248, 12028 3251, 12029 3254, 12030 3257, 12031 3260, 12032 3263, 12033 3266, 12034 3269, 12035 3272, 12036 3275, 12037 3278, 12038 3281, 12039 3284, 12040 3287, 12041 3290, 12042 3293, 12043 3296, 12044 3299, 12045 3302, 12046 3305, 12047 3308, 12048 3311, 12049 3314, 12050 3317, 12051 3320, 12052 3323, 12053 3326, 12054 3329, 12055 3332, 12056 3335, 12057 3338, 12058 3341, 12059 3344, 12060 3347, 12061 3350, 12062 3353, 12063 3356, 12064 3359, 12065 3362, 12066 3365, 12067 3368, 12068 3371, 12069 3374, 12070 3377, 12071 3380, 12072 3383, 12073 3386, 12074 3389, 12075 3392, 12076 3395, 12077 3398, 12078 3401, 12079 3404, 12080 3407, 12081 3410, 12082 3413, 12083 3416, 12084 3419, 12085 3422, 12086 3425, 12087 3428, 12088 3431, 12089 3434, 12090 3437, 12091 3440, 12092 3443, 12093 3446, 12094 3449, 12095 3452, 12096 3455, 12097 3458, 12098 3461, 12099 3464, 12100 3467, 12101 3470, 12102 3473, 12103 3476, 12104 3479, 12105 3482, 12106 3485, 12107 3488, 12108 3491, 12109 3494, 12110 3497, 12111 3500, 12112 3503, 12113 3506, 12114 3509, 12115 3512, 12116 3514, 12117 3516, 12118 3518, 12119 3521, 12120 3524, 12121 3527, 12122 3530, 12123 3533, 12124 3537, 12125 3540, 12126 3543, 12127 3545, 12128 3547, 12129 3549, 12130 3551, 12131 3553, 12132 3556, 12133 3559, 12134 3559, 12135 3559, 12136 3559, 12137 3563, 12138 3567, 12139 3571, 12140 3575, 12141 3576, 12142 3581, 12143 3586, 12144 3591, 12145 3594, 12146 3597, 12147 3600, 12148 3603, 12149 3606, 12150 3609, 12151 3612, 12152 3615, 12153 3618, 12154 3621, 12155 3624, 12156 3627, 12157 3628, 12158 3629, 12159 3633, 12160 3637, 12161 3640, 12162 3642, 12163 3645, 12164 3647, 12165 3650, 12166 3653, 12167 3656, 12168 3657, 12169 3660, 12170 3662, 12171 3665, 12172 3667, 12173 3670, 12174 3673, 12175 3676, 12176 3679, 12177 3681, 12178 3683, 12179 3686, 12180 3689, 12181 3692, 12182 3695, 12183 3698, 12184 3701, 12185 3704, 12186 3707, 12187 3711, 12188 3715, 12189 3719, 12190 3723, 12191 3727, 12192 3731, 12193 3735, 12194 3739, 12195 3743, 12196 3747, 12197 3751, 12198 3755, 12199 3759, 12200 3763, 12201 3767, 12202 3771, 12203 3775, 12204 3779, 12205 3783, 12206 3787, 12207 3791, 12208 3795, 12209 3797, 12210 3801, 12211 3805, 12212 3809, 12213 3813, 12214 3817, 12215 3821, 12216 3825, 12217 3829, 12218 3833, 12219 3837, 12220 3841, 12221 3845, 12222 3849, 12223 3853, 12224 3857, 12225 3861, 12226 3865, 12227 3869, 12228 3873, 12229 3877, 12230 3881, 12231 3885, 12232 3888, 12233 3891, 12234 3894, 12235 3896, 12236 3898, 12237 3900, 12238 3903, 12239 3906, 12240 3908, 12241 3911, 12242 3914, 12243 3917, 12244 3920, 12245 3923, 12246 3926, 12247 3929, 12248 3932, 12249 3935, 12250 3937, 12251 3938, 12252 3939, 12253 3940, 12254 3942, 12255 3944, 12256 3944, 12257 3944, 12258 3944, 12259 3945, 12260 3946, 12261 3947, 12262 3948, 12263 3948, 12264 3948, 12265 3948, 12266 3948, 12267 3948, 12268 3949, 12269 3950, 12270 3951, 12271 3955, 12272 3958, 12273 3961, 12274 3964, 12275 3967, 12276 3970, 12277 3973, 12278 3976, 12279 3979, 12280 3982, 12281 3985, 12282 3988, 12283 3991, 12284 3994, 12285 3997, 12286 4000, 12287 4003, 12288 4006, 12289 4009, 12290 4012, 12291 4015, 12292 4018, 12293 4021, 12294 4024, 12295 4027, 12296 4031, 12297 4035, 12298 4039, 12299 4043, 12300 4045, 12301 4047, 12302 4049, 12303 4051, 12304 4053, 12305 4055, 12306 4058, 12307 4061, 12308 4064, 12309 4067, 12310 4070, 12311 4073, 12312 4076, 12313 4079, 12314 4082, 12315 4085, 12316 4088, 12317 4091, 12318 4094, 12319 4096, 12320 4098, 12321 4101, 12322 4104, 12323 4107, 12324 4110, 12325 4113, 12326 4116, 12327 4119, 12328 4122, 12329 4125, 12330 4128, 12331 4131, 12332 4134, 12333 4137, 12334 4140, 12335 4143, 12336 4146, 12337 4149, 12338 4152, 12339 4155, 12340 4158, 12341 4161, 12342 4164, 12343 4167, 12344 4170, 12345 4173, 12346 4176, 12347 4179, 12348 4182, 12349 4185, 12350 4188, 12351 4191, 12352 4194, 12353 4197, 12354 4200, 12355 4203, 12356 4206, 12357 4208, 12358 4210, 12359 4212, 12360 4214, 12361 4216, 12362 4218, 12363 4220, 12364 4222, 12365 4224, 12366 4226, 12367 4228, 12368 4230, 12369 4232, 12370 4234, 12371 4236, 12372 4238, 12373 4240, 12374 4242, 12375 4244, 12376 4246, 12377 4248, 12378 4250, 12379 4252, 12380 4254, 12381 4256, 12382 4258, 12383 4260, 12384 4262, 12385 4264, 12386 4268, 12387 4272, 12388 4275, 12389 4278, 12390 4281, 12391 4284, 12392 4287, 12393 4290, 12394 4293, 12395 4296, 12396 4298, 12397 4300, 12398 4302, 12399 4304, 12400 4306, 12401 4308, 12402 4310, 12403 4312, 12404 4316, 12405 4320, 12406 4323, 12407 4326, 12408 4329, 12409 4332, 12410 4335, 12411 4338, 12412 4341, 12413 4344, 12414 4347, 12415 4349, 12416 4351, 12417 4353, 12418 4355, 12419 4357, 12420 4359, 12421 4361, 12422 4364, 12423 4366, 12424 4368, 12425 4370, 12426 4372, 12427 4374, 12428 4376, 12429 4379, 12430 4382, 12431 4385, 12432 4388, 12433 4391, 12434 4394, 12435 4397, 12436 4400, 12437 4403, 12438 4406, 12439 4409, 12440 4412, 12441 4414, 12442 4416, 12443 4418, 12444 4420, 12445 4422, 12446 4424, 12447 4426, 12448 4428, 12449 4431, 12450 4434, 12451 4437, 12452 4440, 12453 4443, 12454 4446, 12455 4449, 12456 4452, 12457 4455, 12458 4458, 12459 4461, 12460 4464, 12461 4467, 12462 4470, 12463 4473, 12464 4476, 12465 4479, 12466 4482, 12467 4485, 12468 4487, 12469 4489, 12470 4491, 12471 4493, 12472 4496, 12473 4499, 12474 4501, 12475 4503, 12476 4505, 12477 4507, 12478 4508, 12479 4509, 12480 4511, 12481 4513, 12482 4516, 12483 4519, 12484 4522, 12485 4525, 12486 4528, 12487 4531, 12488 4534, 12489 4537, 12490 4540, 12491 4543, 12492 4546, 12493 4549, 12494 4550, 12495 4551, 12496 4554, 12497 4557, 12498 4560, 12499 4563, 12500 4566, 12501 4569, 12502 4572, 12503 4575, 12504 4578, 12505 4581, 12506 4584, 12507 4587, 12508 4590, 12509 4593, 12510 4596, 12511 4599, 12512 4604, 12513 4608, 12514 4612, 12515 4616, 12516 4620, 12517 4623, 12518 4628, 12519 4633, 12520 4638, 12521 4643, 12522 4646, 12523 4651, 12524 4656, 12525 4657, 12526 4658, 12527 4660, 12528 4661, 12529 4663, 12530 4664, 12531 4666, 12532 4668, 12533 4669, 12534 4671, 12535 4673, 12536 4675, 12537 4677, 12538 4678, 12539 4679, 12540 4680, 12541 4681, 12542 4683, 12543 4685, 12544 4687, 12545 4689, 12546 4691, 12547 4693, 12548 4694, 12549 4695, 12550 4696, 12551 4697, 12552 4698, 12553 4699, 12554 4700, 12555 4701, 12556 4702, 12557 4703, 12558 4704, 12559 4705, 12560 4706, 12561 4707, 12562 4708, 12563 4708, 12564 4708, 12565 4709, 12566 4710, 12567 4713, 12568 4716, 12569 4719, 12570 4722, 12571 4725, 12572 4728, 12573 4731, 12574 4734, 12575 4737, 12576 4740, 12577 4743, 12578 4746, 12579 4749, 12580 4752, 12581 4755, 12582 4758, 12583 4761, 12584 4764, 12585 4767, 12586 4770, 12587 4773, 12588 4776, 12589 4779, 12590 4782, 12591 4784, 12592 4786, 12593 4788, 12594 4790, 12595 4794, 12596 4796, 12597 4800, 12598 4803, 12599 4806, 12600 4809, 12601 4812, 12602 4815, 12603 4818, 12604 4821, 12605 4824, 12606 4827, 12607 4830, 12608 4833, 12609 4836, 12610 4839, 12611 4842, 12612 4845, 12613 4848, 12614 4851, 12615 4854, 12616 4857, 12617 4860, 12618 4863, 12619 4866, 12620 4868, 12621 4870, 12622 4873, 12623 4876, 12624 4879, 12625 4882, 12626 4885, 12627 4888, 12628 4891, 12629 4894, 12630 4897, 12631 4900, 12632 4904, 12633 4908, 12634 4912, 12635 4914, 12636 4917, 12637 4920, 12638 4923, 12639 4925, 12640 4927, 12641 4929, 12642 4932, 12643 4935, 12644 4938, 12645 4941, 12646 4944, 12647 4947, 12648 4950, 12649 4953, 12650 4956, 12651 4959, 12652 4962, 12653 4965, 12654 4968, 12655 4971, 12656 4975, 12657 4979, 12658 4983, 12659 4987, 12660 4991, 12661 4994, 12662 4997, 12663 5000, 12664 5002, 12665 5004, 12666 5008, 12667 5012, 12668 5016, 12669 5020, 12670 5024, 12671 5028, 12672 5031, 12673 5033, 12674 5036, 12675 5039, 12676 5042, 12677 5045, 12678 5048, 12679 5051, 12680 5054, 12681 5057, 12682 5060, 12683 5063, 12684 5066, 12685 5069, 12686 5072, 12687 5074, 12688 5076, 12689 5078, 12690 5081, 12691 5084, 12692 5087, 12693 5090, 12694 5092, 12695 5096, 12696 5100, 12697 5104, 12698 5108, 12699 5112, 12700 5116, 12701 5118, 12702 5122, 12703 5126, 12704 5128, 12705 5132, 12706 5136, 12707 5140, 12708 5144, 12709 5148, 12710 5152, 12711 5156, 12712 5160, 12713 5164, 12714 5166, 12715 5170, 12716 5174, 12717 5178, 12718 5182, 12719 5186, 12720 5190, 12721 5194, 12722 5198, 12723 5202, 12724 5206, 12725 5210, 12726 5214, 12727 5217, 12728 5220, 12729 5223, 12730 5226, 12731 5229, 12732 5232, 12733 5235, 12734 5238, 12735 5241, 12736 5244, 12737 5247, 12738 5250, 12739 5253, 12740 5256, 12741 5259, 12742 5262, 12743 5265, 12744 5268, 12745 5271, 12746 5274, 12747 5277, 12748 5280, 12749 5283, 12750 5286, 12751 5289, 12752 5292, 12753 5295, 12754 5298, 12755 5301, 12756 5304, 12757 5306, 12758 5308, 12759 5310, 12760 5312, 12761 5315, 12762 5317, 12763 5320, 12764 5323, 12765 5326, 12766 5328, 12767 5330, 12768 5332, 12769 5334, 12770 5336, 12771 5339, 12772 5342, 12773 5343, 12774 5344, 12775 5345, 12776 5347, 12777 5349, 12778 5350, 12779 5351, 12780 5352, 12781 5353, 12782 5355, 12783 5357, 12784 5358, 12785 5363, 12786 5366, 12787 5369, 12788 5372, 12789 5375, 12790 5378, 12791 5381, 12792 5384, 12793 5387, 12794 5390, 12795 5393, 12796 5396, 12797 5399, 12798 5402, 12799 5405, 12800 5408, 12801 5411, 12802 5414, 12803 5417, 12804 5420, 12805 5423, 12806 5426, 12807 5429, 12808 5432, 12809 5435, 12810 5438, 12811 5441, 12812 5444, 12813 5447, 12814 5450, 12815 5453, 12816 5456, 12817 5459, 12818 5462, 12819 5465, 12820 5468, 12821 5471, 12822 5474, 12823 5477, 12824 5480, 12825 5483, 12826 5486, 12827 5489, 12828 5491, 12829 5493, 12830 5497, 12831 5501, 12832 5503, 12833 5507, 12834 5511, 12835 5515, 12836 5519, 12837 5523, 12838 5527, 12839 5531, 12840 5535, 12841 5539, 12842 5543, 12843 5547, 12844 5551, 12845 5555, 12846 5559, 12847 5563, 12848 5567, 12849 5571, 12850 5575, 12851 5579, 12852 5583, 12853 5587, 12854 5591, 12855 5595, 12856 5599, 12857 5603, 12858 5607, 12859 5611, 12860 5615, 12861 5619, 12862 5623, 12863 5627, 12864 5631, 12865 5635, 12866 5639, 12867 5643, 12868 5647, 12869 5651, 12870 5655, 12871 5659, 12872 5663, 12873 5665, 12874 5669, 12875 5673, 12876 5677, 12877 5681, 12878 5685, 12879 5689, 12880 5691, 12881 5695, 12882 5699, 12883 5701, 12884 5705, 12885 5709, 12886 5713, 12887 5717, 12888 5721, 12889 5725, 12890 5729, 12891 5733, 12892 5737, 12893 5739, 12894 5743, 12895 5747, 12896 5751, 12897 5755, 12898 5758, 12899 5761, 12900 5763, 12901 5765, 12902 5767, 12903 5769, 12904 5771, 12905 5774, 12906 5776, 12907 5779, 12908 5782, 12909 5785, 12910 5788, 12911 5791, 12912 5794, 12913 5797, 12914 5799, 12915 5802, 12916 5805, 12917 5806, 12918 5807, 12919 5809, 12920 5811, 12921 5812, 12922 5815, 12923 5818, 12924 5819, 12925 5820, 12926 5822, 12927 5824, 12928 5825, 12929 5826, 12930 5827, 12931 5828, 12932 5829, 12933 5830, 12934 5831, 12935 5836, 12936 5839, 12937 5842, 12938 5845, 12939 5848, 12940 5851, 12941 5854, 12942 5857, 12943 5860, 12944 5863, 12945 5866, 12946 5869, 12947 5872, 12948 5875, 12949 5878, 12950 5881, 12951 5884, 12952 5887, 12953 5890, 12954 5893, 12955 5896, 12956 5899, 12957 5902, 12958 5905, 12959 5909, 12960 5913, 12961 5917, 12962 5921, 12963 5923, 12964 5926, 12965 5929, 12966 5932, 12967 5935, 12968 5937, 12969 5939, 12970 5941, 12971 5944, 12972 5947, 12973 5950, 12974 5953, 12975 5956, 12976 5959, 12977 5962, 12978 5965, 12979 5968, 12980 5971, 12981 5974, 12982 5977, 12983 5980, 12984 5983, 12985 5986, 12986 5987, 12987 5988, 12988 5990, 12989 5992, 12990 5994, 12991 5996, 12992 5998, 12993 6000, 12994 6002, 12995 6004, 12996 6006, 12997 6008, 12998 6012, 12999 6016, 13000 6020, 13001 6024, 13002 6028, 13003 6032, 13004 6036, 13005 6040, 13006 6044, 13007 6048, 13008 6051, 13009 6054, 13010 6057, 13011 6060, 13012 6063, 13013 6066, 13014 6068, 13015 6070, 13016 6072, 13017 6074, 13018 6077, 13019 6080, 13020 6083, 13021 6086, 13022 6089, 13023 6092, 13024 6095, 13025 6098, 13026 6101, 13027 6104, 13028 6107, 13029 6110, 13030 6113, 13031 6116, 13032 6119, 13033 6119, 13034 6119, 13035 6119, 13036 6122, 13037 6125, 13038 6128, 13039 6131, 13040 6134, 13041 6137, 13042 6140, 13043 6143, 13044 6145, 13045 6147, 13046 6149, 13047 6151, 13048 6154, 13049 6157, 13050 6160, 13051 6163, 13052 6166, 13053 6169, 13054 6171, 13055 6173, 13056 6175, 13057 6177, 13058 6179, 13059 6181, 13060 6183, 13061 6185, 13062 6187, 13063 6189, 13064 6191, 13065 6193, 13066 6195, 13067 6197, 13068 6199, 13069 6201, 13070 6203, 13071 6205, 13072 6207, 13073 6209, 13074 6211, 13075 6214, 13076 6217, 13077 6220, 13078 6223, 13079 6226, 13080 6229, 13081 6232, 13082 6235, 13083 6238, 13084 6241, 13085 6245, 13086 6249, 13087 6253, 13088 6257, 13089 6260, 13090 6263, 13091 6266, 13092 6269, 13093 6272, 13094 6275, 13095 6278, 13096 6282, 13097 6286, 13098 6288, 13099 6290, 13100 6292, 13101 6294, 13102 6297, 13103 6300, 13104 6303, 13105 6306, 13106 6308, 13107 6310, 13108 6312, 13109 6314, 13110 6316, 13111 6318, 13112 6320, 13113 6322, 13114 6324, 13115 6326, 13116 6328, 13117 6330, 13118 6332, 13119 6334, 13120 6336, 13121 6338, 13122 6340, 13123 6342, 13124 6344, 13125 6347, 13126 6350, 13127 6353, 13128 6356, 13129 6358, 13130 6360, 13131 6362, 13132 6364, 13133 6366, 13134 6368, 13135 6370, 13136 6372, 13137 6374, 13138 6376, 13139 6378, 13140 6380, 13141 6382, 13142 6384, 13143 6386, 13144 6388, 13145 6390, 13146 6390, 13147 6390, 13148 6392, 13149 6394, 13150 6397, 13151 6400, 13152 6403, 13153 6406, 13154 6409, 13155 6412, 13156 6415, 13157 6418, 13158 6421, 13159 6424, 13160 6427, 13161 6430, 13162 6433, 13163 6436, 13164 6439, 13165 6442, 13166 6446, 13167 6450, 13168 6454, 13169 6458, 13170 6462, 13171 6466, 13172 6470, 13173 6474, 13174 6478, 13175 6482, 13176 6485, 13177 6486, 13178 6487, 13179 6488, 13180 6489, 13181 6490, 13182 6491, 13183 6494, 13184 6497, 13185 6500, 13186 6503, 13187 6506, 13188 6509, 13189 6512, 13190 6515, 13191 6517, 13192 6519, 13193 6522, 13194 6525, 13195 6528, 13196 6531, 13197 6533, 13198 6535, 13199 6537, 13200 6539, 13201 6541, 13202 6543, 13203 6546, 13204 6549, 13205 6552, 13206 6555, 13207 6558, 13208 6561, 13209 6564, 13210 6567, 13211 6570, 13212 6573, 13213 6576, 13214 6579, 13215 6582, 13216 6585, 13217 6589, 13218 6593, 13219 6597, 13220 6601, 13221 6604, 13222 6607, 13223 6610, 13224 6613, 13225 6616, 13226 6619, 13227 6622, 13228 6625, 13229 6628, 13230 6631, 13231 6634, 13232 6637, 13233 6640, 13234 6643, 13235 6646, 13236 6649, 13237 6652, 13238 6655, 13239 6658, 13240 6661, 13241 6664, 13242 6667, 13243 6670, 13244 6673, 13245 6676, 13246 6679, 13247 6682, 13248 6685, 13249 6688, 13250 6691, 13251 6694, 13252 6697, 13253 6700, 13254 6703, 13255 6706, 13256 6709, 13257 6712, 13258 6715, 13259 6718, 13260 6721, 13261 6724, 13262 6727, 13263 6730, 13264 6733, 13265 6736, 13266 6739, 13267 6742, 13268 6745, 13269 6748, 13270 6751, 13271 6754, 13272 6757, 13273 6760, 13274 6763, 13275 6766, 13276 6769, 13277 6772, 13278 6775, 13279 6778, 13280 6781, 13281 6784, 13282 6785, 13283 6786, 13284 6790, 13285 6794, 13286 6798, 13287 6802, 13288 6806, 13289 6810, 13290 6814, 13291 6818, 13292 6821, 13293 6824, 13294 6827, 13295 6829, 13296 6831, 13297 6834, 13298 6837, 13299 6840, 13300 6843, 13301 6846, 13302 6849, 13303 6852, 13304 6855, 13305 6858, 13306 6861, 13307 6864, 13308 6867, 13309 6870, 13310 6873, 13311 6876, 13312 6879, 13313 6882, 13314 6885, 13315 6888, 13316 6891, 13317 6894, 13318 6897, 13319 6900, 13320 6903, 13321 6906, 13322 6909, 13323 6912, 13324 6915, 13325 6918, 13326 6921, 13327 6924, 13328 6927, 13329 6930, 13330 6933, 13331 6936, 13332 6939, 13333 6942, 13334 6945, 13335 6948, 13336 6951, 13337 6954, 13338 6957, 13339 6960, 13340 6963, 13341 6966, 13342 6969, 13343 6972, 13344 6975, 13345 6978, 13346 6981, 13347 6984, 13348 6987, 13349 6990, 13350 6993, 13351 6996, 13352 6999, 13353 7002, 13354 7005, 13355 7008, 13356 7011, 13357 7014, 13358 7017, 13359 7020, 13360 7023, 13361 7026, 13362 7029, 13363 7032, 13364 7035, 13365 7038, 13366 7041, 13367 7044, 13368 7047, 13369 7050, 13370 7053, 13371 7056, 13372 7059, 13373 7059, 13374 7059, 13375 7059, 13376 7062, 13377 7065, 13378 7068, 13379 7071, 13380 7074, 13381 7077, 13382 7080, 13383 7083, 13384 7086, 13385 7089, 13386 7092, 13387 7095, 13388 7098, 13389 7101, 13390 7104, 13391 7107, 13392 7110, 13393 7113, 13394 7116, 13395 7119, 13396 7122, 13397 7125, 13398 7128, 13399 7131, 13400 7134, 13401 7137, 13402 7140, 13403 7143, 13404 7146, 13405 7149, 13406 7152, 13407 7155, 13408 7158, 13409 7161, 13410 7164, 13411 7167, 13412 7170, 13413 7173, 13414 7176, 13415 7179, 13416 7182, 13417 7185, 13418 7188, 13419 7191, 13420 7194, 13421 7197, 13422 7200, 13423 7203, 13424 7206, 13425 7209, 13426 7212, 13427 7215, 13428 7218, 13429 7221, 13430 7224, 13431 7227, 13432 7230, 13433 7233, 13434 7236, 13435 7239, 13436 7242, 13437 7245, 13438 7248, 13439 7251, 13440 7254, 13441 7257, 13442 7260, 13443 7263, 13444 7266, 13445 7269, 13446 7272, 13447 7275, 13448 7278, 13449 7281, 13450 7284, 13451 7287, 13452 7290, 13453 7293, 13454 7296, 13455 7299, 13456 7302, 13457 7305, 13458 7308, 13459 7311, 13460 7314, 13461 7317, 13462 7320, 13463 7324, 13464 7327, 13465 7330, 13466 7333, 13467 7336, 13468 7339, 13469 7342, 13470 7345, 13471 7348, 13472 7351, 13473 7354, 13474 7357, 13475 7358, 13476 7360, 13477 7362, 13478 7364, 13479 7365, 13480 7366, 13481 7367, 13482 7368, 13483 7368, 13484 7368, 13485 7371, 13486 7373, 13487 7375, 13488 7378, 13489 7381, 13490 7384, 13491 7386, 13492 7388, 13493 7390, 13494 7392, 13495 7394, 13496 7396, 13497 7399, 13498 7402, 13499 7405, 13500 7408, 13501 7411, 13502 7414, 13503 7417, 13504 7420, 13505 7422, 13506 7424, 13507 7427, 13508 7430, 13509 7432, 13510 7434, 13511 7436, 13512 7438, 13513 7441, 13514 7444, 13515 7447, 13516 7447, 13517 7447, 13518 7447, 13519 7447, 13520 7447, 13521 7447, 13522 7447, 13523 7447, 13524 7447, 13525 7447, 13526 7447, 13527 7447, 13528 7447, 13529 7447, 13530 7447, 13531 7447, 13532 7447, 13533 7447, 13534 7447, 13535 7447, 13536 7447, 13537 7447, 13538 7447, 13539 7447, 13540 7450, 13541 7452, 13542 7454, 13543 7456, 13544 7459, 13545 7462, 13546 7465, 13547 7468, 13548 7470, 13549 7472, 13550 7475, 13551 7477, 13552 7479, 13553 7481, 13554 7483, 13555 7485, 13556 7487, 13557 7489, 13558 7491, 13559 7493, 13560 7495, 13561 7497, 13562 7499, 13563 7501, 13564 7503, 13565 7506, 13566 7509, 13567 7512, 13568 7516, 13569 7520, 13570 7524, 13571 7528, 13572 7528, 13573 7529, 13574 7530, 13575 7532, 13576 7534, 13577 7536, 13578 7538, 13579 7540, 13580 7542, 13581 7545, 13582 7548, 13583 7551, 13584 7554, 13585 7557, 13586 7560, 13587 7563, 13588 7566, 13589 7569, 13590 7572, 13591 7575, 13592 7578, 13593 7581, 13594 }; 13595 const int OpcodeOperandTypes[] = { 13596 -1, 13597 /**/ 13598 /**/ 13599 OpTypes::i32imm, 13600 OpTypes::i32imm, 13601 OpTypes::i32imm, 13602 OpTypes::i32imm, 13603 /**/ 13604 -1, -1, OpTypes::i32imm, 13605 -1, -1, -1, OpTypes::i32imm, 13606 -1, 13607 -1, -1, -1, OpTypes::i32imm, 13608 -1, -1, OpTypes::i32imm, 13609 /**/ 13610 -1, 13611 -1, -1, 13612 -1, -1, 13613 /**/ 13614 OpTypes::i32imm, 13615 OpTypes::i32imm, 13616 OpTypes::i64imm, OpTypes::i32imm, 13617 /**/ 13618 -1, OpTypes::i64imm, OpTypes::i32imm, -1, OpTypes::i32imm, OpTypes::i32imm, 13619 -1, 13620 /**/ 13621 -1, OpTypes::i32imm, 13622 -1, 13623 /**/ 13624 /**/ 13625 /**/ 13626 /**/ 13627 /**/ 13628 -1, -1, 13629 -1, -1, -1, 13630 /**/ 13631 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13632 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13633 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13634 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13635 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13636 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13637 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13638 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13639 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13640 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13641 OpTypes::type0, 13642 OpTypes::type0, 13643 OpTypes::type0, -1, 13644 OpTypes::type0, -1, 13645 OpTypes::type0, OpTypes::type1, -1, 13646 OpTypes::type0, OpTypes::type1, 13647 OpTypes::type0, OpTypes::type0, OpTypes::type1, -1, 13648 OpTypes::type0, OpTypes::type1, 13649 OpTypes::type0, OpTypes::type1, 13650 OpTypes::type0, OpTypes::type1, 13651 OpTypes::type0, OpTypes::type1, 13652 OpTypes::type0, OpTypes::type1, 13653 OpTypes::type0, OpTypes::type1, 13654 OpTypes::type0, OpTypes::type1, 13655 OpTypes::type0, OpTypes::type0, 13656 OpTypes::type0, OpTypes::type0, 13657 OpTypes::type0, 13658 OpTypes::type0, OpTypes::ptype1, 13659 OpTypes::type0, OpTypes::ptype1, 13660 OpTypes::type0, OpTypes::ptype1, 13661 OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 13662 OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 13663 OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, 13664 OpTypes::type0, OpTypes::ptype1, 13665 OpTypes::ptype0, OpTypes::type1, OpTypes::ptype0, OpTypes::ptype2, -1, 13666 OpTypes::type0, OpTypes::type1, OpTypes::type2, OpTypes::type0, OpTypes::type0, 13667 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, OpTypes::type0, 13668 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13669 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13670 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13671 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13672 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13673 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13674 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13675 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13676 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13677 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13678 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13679 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13680 OpTypes::type0, OpTypes::ptype1, OpTypes::type0, 13681 OpTypes::i32imm, OpTypes::i32imm, 13682 OpTypes::type0, -1, 13683 OpTypes::type0, 13684 -1, 13685 -1, 13686 OpTypes::type0, OpTypes::type1, 13687 OpTypes::type0, OpTypes::type1, 13688 OpTypes::type0, -1, 13689 OpTypes::type0, -1, 13690 OpTypes::type0, 13691 OpTypes::type0, OpTypes::type1, -1, 13692 OpTypes::type0, OpTypes::type1, 13693 OpTypes::type0, OpTypes::type0, OpTypes::untyped_imm_0, 13694 OpTypes::type0, OpTypes::type1, 13695 OpTypes::type0, OpTypes::type0, OpTypes::type1, 13696 OpTypes::type0, OpTypes::type0, OpTypes::type1, 13697 OpTypes::type0, OpTypes::type0, OpTypes::type1, 13698 OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 13699 OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, 13700 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 13701 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 13702 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 13703 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 13704 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 13705 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 13706 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 13707 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 13708 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, 13709 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 13710 OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, 13711 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13712 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13713 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13714 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13715 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13716 OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, 13717 OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, 13718 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13719 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13720 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13721 OpTypes::type0, OpTypes::type0, 13722 OpTypes::type0, OpTypes::type0, 13723 OpTypes::type0, OpTypes::type0, 13724 OpTypes::type0, OpTypes::type0, 13725 OpTypes::type0, OpTypes::type0, 13726 OpTypes::type0, OpTypes::type0, 13727 OpTypes::type0, OpTypes::type1, 13728 OpTypes::type0, OpTypes::type1, 13729 OpTypes::type0, OpTypes::type1, 13730 OpTypes::type0, OpTypes::type1, 13731 OpTypes::type0, OpTypes::type1, 13732 OpTypes::type0, OpTypes::type1, 13733 OpTypes::type0, OpTypes::type0, 13734 OpTypes::type0, OpTypes::type0, OpTypes::type1, 13735 OpTypes::type0, OpTypes::type0, 13736 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13737 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13738 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13739 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13740 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13741 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13742 OpTypes::type0, OpTypes::type0, OpTypes::type1, 13743 OpTypes::type0, OpTypes::type0, -1, 13744 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13745 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13746 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13747 OpTypes::type0, OpTypes::type0, OpTypes::type0, 13748 -1, 13749 OpTypes::ptype0, -1, OpTypes::type1, 13750 OpTypes::type0, OpTypes::type0, OpTypes::type1, OpTypes::type2, 13751 OpTypes::type0, OpTypes::type1, OpTypes::type2, 13752 OpTypes::type0, OpTypes::type1, OpTypes::type1, -1, 13753 OpTypes::type0, OpTypes::type1, 13754 OpTypes::type0, OpTypes::type1, 13755 OpTypes::type0, OpTypes::type1, 13756 OpTypes::type0, OpTypes::type1, 13757 OpTypes::type0, OpTypes::type1, 13758 OpTypes::type0, OpTypes::type0, 13759 OpTypes::type0, OpTypes::type0, 13760 OpTypes::type0, OpTypes::type0, 13761 OpTypes::type0, OpTypes::type0, 13762 OpTypes::type0, OpTypes::type0, 13763 OpTypes::type0, OpTypes::type0, 13764 OpTypes::type0, OpTypes::type0, 13765 OpTypes::type0, OpTypes::type0, 13766 OpTypes::type0, OpTypes::type0, 13767 OpTypes::type0, OpTypes::type1, 13768 OpTypes::type0, -1, 13769 OpTypes::type0, -1, 13770 OpTypes::ptype0, OpTypes::type1, OpTypes::i32imm, 13771 OpTypes::type0, -1, 13772 -1, OpTypes::type0, 13773 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 13774 OpTypes::i32imm, OpTypes::i32imm, 13775 OpTypes::i32imm, OpTypes::i32imm, 13776 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 13777 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 13778 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 13779 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, 13780 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13781 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, 13782 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, 13783 OpTypes::GPR64, -1, OpTypes::GPR64, OpTypes::GPR64, 13784 OpTypes::GPR64, -1, OpTypes::GPR64, OpTypes::GPR64, 13785 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, 13786 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13787 OpTypes::GPR32, -1, OpTypes::GPR32, 13788 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13789 OpTypes::GPR32, -1, OpTypes::GPR32, 13790 OpTypes::GPR32, -1, OpTypes::GPR32, 13791 OpTypes::GPR64, -1, OpTypes::GPR64, 13792 OpTypes::GPR64, -1, OpTypes::GPR64, 13793 OpTypes::GPR32, -1, OpTypes::GPR32, 13794 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13795 OpTypes::GPR32, -1, OpTypes::GPR32, 13796 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13797 OpTypes::GPR32, -1, OpTypes::GPR32, 13798 OpTypes::GPR32, -1, OpTypes::GPR32, 13799 OpTypes::GPR64, -1, OpTypes::GPR64, 13800 OpTypes::GPR64, -1, OpTypes::GPR64, 13801 OpTypes::GPR32, -1, OpTypes::GPR32, 13802 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13803 OpTypes::GPR32, -1, OpTypes::GPR32, 13804 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13805 OpTypes::GPR32, -1, OpTypes::GPR32, 13806 OpTypes::GPR32, -1, OpTypes::GPR32, 13807 OpTypes::GPR64, -1, OpTypes::GPR64, 13808 OpTypes::GPR64, -1, OpTypes::GPR64, 13809 OpTypes::GPR32, -1, OpTypes::GPR32, 13810 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13811 OpTypes::GPR32, -1, OpTypes::GPR32, 13812 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13813 OpTypes::GPR32, -1, OpTypes::GPR32, 13814 OpTypes::GPR32, -1, OpTypes::GPR32, 13815 OpTypes::GPR64, -1, OpTypes::GPR64, 13816 OpTypes::GPR64, -1, OpTypes::GPR64, 13817 OpTypes::GPR32, -1, OpTypes::GPR32, 13818 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13819 OpTypes::GPR32, -1, OpTypes::GPR32, 13820 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13821 OpTypes::GPR32, -1, OpTypes::GPR32, 13822 OpTypes::GPR32, -1, OpTypes::GPR32, 13823 OpTypes::GPR64, -1, OpTypes::GPR64, 13824 OpTypes::GPR64, -1, OpTypes::GPR64, 13825 OpTypes::GPR32, -1, OpTypes::GPR32, 13826 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13827 OpTypes::GPR32, -1, OpTypes::GPR32, 13828 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13829 OpTypes::GPR32, -1, OpTypes::GPR32, 13830 OpTypes::GPR32, -1, OpTypes::GPR32, 13831 OpTypes::GPR64, -1, OpTypes::GPR64, 13832 OpTypes::GPR64, -1, OpTypes::GPR64, 13833 OpTypes::GPR32, -1, OpTypes::GPR32, 13834 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13835 OpTypes::GPR32, -1, OpTypes::GPR32, 13836 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13837 OpTypes::GPR32, -1, OpTypes::GPR32, 13838 OpTypes::GPR32, -1, OpTypes::GPR32, 13839 OpTypes::GPR64, -1, OpTypes::GPR64, 13840 OpTypes::GPR64, -1, OpTypes::GPR64, 13841 OpTypes::GPR32, -1, OpTypes::GPR32, 13842 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13843 OpTypes::GPR32, -1, OpTypes::GPR32, 13844 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13845 OpTypes::GPR32, -1, OpTypes::GPR32, 13846 OpTypes::GPR32, -1, OpTypes::GPR32, 13847 OpTypes::GPR64, -1, OpTypes::GPR64, 13848 OpTypes::GPR64, -1, OpTypes::GPR64, 13849 OpTypes::GPR32, -1, OpTypes::GPR32, 13850 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13851 OpTypes::GPR32, -1, OpTypes::GPR32, 13852 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13853 OpTypes::GPR32, -1, OpTypes::GPR32, 13854 OpTypes::GPR32, -1, OpTypes::GPR32, 13855 OpTypes::GPR64, -1, OpTypes::GPR64, 13856 OpTypes::GPR64, -1, OpTypes::GPR64, 13857 OpTypes::GPR32, -1, OpTypes::GPR32, 13858 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13859 OpTypes::GPR32, -1, OpTypes::GPR32, 13860 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13861 OpTypes::GPR32, -1, OpTypes::GPR32, 13862 OpTypes::GPR32, -1, OpTypes::GPR32, 13863 OpTypes::GPR64, -1, OpTypes::GPR64, 13864 OpTypes::GPR64, -1, OpTypes::GPR64, 13865 OpTypes::GPR32, -1, OpTypes::GPR32, 13866 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13867 OpTypes::GPR32, -1, OpTypes::GPR32, 13868 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13869 OpTypes::GPR32, -1, OpTypes::GPR32, 13870 OpTypes::GPR32, -1, OpTypes::GPR32, 13871 OpTypes::GPR64, -1, OpTypes::GPR64, 13872 OpTypes::GPR64, -1, OpTypes::GPR64, 13873 OpTypes::GPR32, -1, OpTypes::GPR32, 13874 OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, 13875 OpTypes::brtarget, 13876 OpTypes::brtarget, 13877 OpTypes::brtarget_mm, 13878 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13879 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13880 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13881 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13882 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13883 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13884 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13885 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13886 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13887 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13888 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13889 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13890 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13891 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13892 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13893 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13894 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13895 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13896 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13897 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13898 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13899 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13900 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13901 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13902 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13903 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13904 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13905 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13906 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13907 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13908 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13909 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13910 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13911 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13912 OpTypes::GPR32Opnd, 13913 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 13914 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 13915 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 13916 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 13917 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 13918 OpTypes::brtarget, 13919 OpTypes::brtarget_mm, 13920 OpTypes::brtarget_mm, 13921 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13922 OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, 13923 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, 13924 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, 13925 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, 13926 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, 13927 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, 13928 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, 13929 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, 13930 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, 13931 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, 13932 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, 13933 OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, 13934 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, 13935 OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 13936 OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 13937 OpTypes::GPR32Opnd, OpTypes::FGRCCOpnd, 13938 OpTypes::cpinst_operand, OpTypes::cpinst_operand, OpTypes::i32imm, 13939 OpTypes::FGR64, OpTypes::MSA128D, OpTypes::uimm1_ptr, 13940 OpTypes::FGR32, OpTypes::MSA128W, OpTypes::uimm2_ptr, 13941 OpTypes::FGRCCOpnd, OpTypes::GPR32Opnd, 13942 OpTypes::simm32, 13943 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm32_relaxed, 13944 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 13945 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 13946 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 13947 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 13948 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 13949 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 13950 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 13951 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, 13952 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 13953 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm32_relaxed, 13954 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 13955 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, 13956 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 13957 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm32_relaxed, 13958 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 13959 /**/ 13960 OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, OpTypes::i32imm, 13961 OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, OpTypes::i32imm, 13962 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 13963 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 13964 OpTypes::MSA128D, OpTypes::MSA128D, 13965 OpTypes::MSA128W, OpTypes::MSA128W, 13966 OpTypes::MSA128D, OpTypes::FGR64, 13967 OpTypes::MSA128W, OpTypes::FGR32, 13968 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::simm16, 13969 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, 13970 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 13971 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 13972 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, 13973 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm1, OpTypes::FGR64Opnd, 13974 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR64Opnd, OpTypes::FGR64Opnd, 13975 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, 13976 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm2, OpTypes::FGR32Opnd, 13977 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR64Opnd, OpTypes::FGR32Opnd, 13978 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 13979 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, 13980 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 13981 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, 13982 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 13983 OpTypes::GPR64Opnd, 13984 OpTypes::GPR64Opnd, 13985 OpTypes::GPR32Opnd, 13986 OpTypes::GPR32Opnd, 13987 OpTypes::calltarget, 13988 OpTypes::GPR32Opnd, 13989 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 13990 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 13991 OpTypes::MSA128F16, -1, OpTypes::simm10, 13992 OpTypes::ACC128, -1, OpTypes::simm16, 13993 OpTypes::ACC64, -1, OpTypes::simm16, 13994 OpTypes::ACC64DSPOpnd, -1, OpTypes::simm16, 13995 OpTypes::DSPCC, -1, OpTypes::simm16, 13996 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, OpTypes::brtarget, 13997 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 13998 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, OpTypes::brtarget, 13999 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, 14000 OpTypes::GPR32Opnd, OpTypes::brtarget, OpTypes::brtarget, 14001 OpTypes::GPR32Opnd, OpTypes::brtarget, 14002 OpTypes::GPR64Opnd, OpTypes::brtarget, 14003 OpTypes::reglist, -1, OpTypes::simm12, 14004 OpTypes::GPR32Opnd, OpTypes::i32imm, 14005 OpTypes::GPR64Opnd, OpTypes::imm64, 14006 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 14007 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 14008 OpTypes::GPR32Opnd, OpTypes::uimm32_coerced, 14009 OpTypes::GPR64Opnd, OpTypes::imm64, 14010 OpTypes::StrictlyFGR64Opnd, OpTypes::imm64, 14011 OpTypes::StrictlyAFGR64Opnd, OpTypes::imm64, 14012 OpTypes::GPR32Opnd, OpTypes::imm64, 14013 OpTypes::StrictlyFGR32Opnd, OpTypes::imm64, 14014 OpTypes::GPR32Opnd, OpTypes::imm64, 14015 OpTypes::CPU16Regs, OpTypes::simm32, OpTypes::simm32, 14016 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14017 OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 14018 OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 14019 OpTypes::GPR32Opnd, 14020 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 14021 OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 14022 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14023 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14024 OpTypes::GPR32, OpTypes::GPR32, 14025 OpTypes::GPR64, OpTypes::GPR64, 14026 OpTypes::FGR64Opnd, OpTypes::MSA128F16, 14027 OpTypes::FGR32Opnd, OpTypes::MSA128F16, 14028 OpTypes::MSA128F16, OpTypes::FGR64Opnd, 14029 OpTypes::MSA128F16, OpTypes::FGR32Opnd, 14030 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 14031 OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 14032 OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, 14033 OpTypes::GPR32Opnd, 14034 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14035 OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, 14036 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 14037 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 14038 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, 14039 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14040 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14041 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14042 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14043 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14044 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14045 /**/ 14046 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, 14047 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, 14048 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14049 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14050 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14051 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14052 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14053 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14054 OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14055 OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14056 OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14057 OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14058 OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14059 OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14060 OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, 14061 OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, 14062 OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, 14063 OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, 14064 OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, 14065 OpTypes::ACC128, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14066 OpTypes::ACC128, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14067 OpTypes::ACC128, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14068 OpTypes::ACC128, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14069 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14070 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14071 OpTypes::GPR32Opnd, 14072 OpTypes::GPR64Opnd, 14073 OpTypes::GPR64Opnd, 14074 OpTypes::GPR32Opnd, 14075 OpTypes::GPR32Opnd, 14076 OpTypes::GPR32Opnd, 14077 OpTypes::GPR32Opnd, 14078 OpTypes::GPR64Opnd, 14079 OpTypes::GPR64Opnd, 14080 OpTypes::GPR32Opnd, 14081 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, 14082 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, 14083 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, 14084 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, 14085 OpTypes::GPR32, OpTypes::ACC64, 14086 OpTypes::GPR64, OpTypes::ACC128, 14087 OpTypes::GPR32, OpTypes::ACC64, 14088 OpTypes::GPR32, OpTypes::ACC64, 14089 OpTypes::GPR64, OpTypes::ACC128, 14090 OpTypes::GPR32, OpTypes::ACC64, 14091 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, 14092 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, 14093 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, 14094 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, 14095 OpTypes::ACC64, OpTypes::GPR32, OpTypes::GPR32, 14096 OpTypes::ACC128, OpTypes::GPR64, OpTypes::GPR64, 14097 OpTypes::ACC64DSP, OpTypes::GPR32, OpTypes::GPR32, 14098 OpTypes::ACC64, OpTypes::GPR32, OpTypes::GPR32, 14099 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14100 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14101 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14102 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14103 OpTypes::DSPROpnd, OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14104 OpTypes::DSPROpnd, OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14105 OpTypes::GPR32Opnd, 14106 OpTypes::GPR64Opnd, 14107 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14108 OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14109 OpTypes::FGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14110 OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14111 OpTypes::GPR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14112 OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14113 OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14114 OpTypes::FGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14115 OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14116 OpTypes::GPR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14117 OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14118 OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14119 OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14120 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14121 OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14122 OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14123 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, 14124 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, 14125 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, 14126 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14127 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14128 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 14129 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14130 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 14131 /**/ 14132 /**/ 14133 OpTypes::AFGR64Opnd, -1, OpTypes::simm16, 14134 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14135 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 14136 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32, 14137 OpTypes::GPR32NonZeroOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14138 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, 14139 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14140 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14141 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32, 14142 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, 14143 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14144 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm32_coerced, 14145 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, 14146 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32, 14147 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, 14148 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm32_coerced, 14149 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, 14150 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, 14151 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, 14152 OpTypes::GPR32, OpTypes::MSA128B, 14153 OpTypes::GPR32, OpTypes::MSA128D, 14154 OpTypes::GPR32, OpTypes::MSA128H, 14155 OpTypes::GPR32, OpTypes::MSA128B, 14156 OpTypes::GPR32, OpTypes::MSA128W, 14157 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, 14158 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14159 OpTypes::ACC128, -1, OpTypes::simm16, 14160 OpTypes::ACC64, -1, OpTypes::simm16, 14161 OpTypes::ACC64DSPOpnd, -1, OpTypes::simm16, 14162 OpTypes::DSPCC, -1, OpTypes::simm16, 14163 OpTypes::MSA128F16, -1, OpTypes::simm10, 14164 OpTypes::reglist, -1, OpTypes::simm12, 14165 OpTypes::GPR32, OpTypes::MSA128B, 14166 OpTypes::GPR32, OpTypes::MSA128D, 14167 OpTypes::GPR32, OpTypes::MSA128H, 14168 OpTypes::GPR32, OpTypes::MSA128B, 14169 OpTypes::GPR32, OpTypes::MSA128W, 14170 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 14171 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 14172 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14173 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14174 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14175 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14176 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14177 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14178 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14179 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14180 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14181 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14182 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14183 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14184 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14185 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14186 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14187 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14188 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14189 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14190 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14191 OpTypes::calltarget, 14192 OpTypes::GPR64Opnd, 14193 OpTypes::GPR64Opnd, 14194 OpTypes::GPR32Opnd, 14195 OpTypes::GPR32Opnd, 14196 OpTypes::GPR32Opnd, 14197 OpTypes::GPR64Opnd, 14198 OpTypes::GPR32Opnd, 14199 OpTypes::GPR64Opnd, 14200 OpTypes::GPR32Opnd, 14201 OpTypes::GPR32Opnd, 14202 OpTypes::calltarget, 14203 OpTypes::calltarget, 14204 /**/ 14205 /**/ 14206 OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14207 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32, 14208 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14209 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, 14210 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14211 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 14212 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 14213 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 14214 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 14215 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 14216 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14217 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14218 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14219 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14220 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14221 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14222 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14223 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14224 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14225 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14226 OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, 14227 OpTypes::GPRMM16Opnd, OpTypes::simm23_lsl2, 14228 OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, 14229 OpTypes::GPRMM16Opnd, OpTypes::uimm6_lsl2, 14230 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::simm3_lsa2, 14231 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm4, 14232 OpTypes::simm9_addiusp, 14233 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 14234 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14235 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14236 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14237 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14238 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14239 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14240 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14241 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14242 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14243 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14244 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14245 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14246 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14247 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14248 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14249 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14250 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14251 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14252 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14253 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14254 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14255 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14256 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14257 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14258 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14259 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14260 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14261 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14262 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 14263 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 14264 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14265 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14266 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14267 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14268 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14269 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14270 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14271 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14272 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14273 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14274 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14275 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14276 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14277 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, 14278 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, 14279 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, 14280 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 14281 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14282 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14283 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14284 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14285 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14286 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14287 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14288 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14289 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14290 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14291 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14292 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14293 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16_relaxed, 14294 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 14295 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16_relaxed, 14296 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 14297 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14298 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14299 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2, 14300 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2, 14301 OpTypes::GPR32Opnd, OpTypes::simm16, 14302 OpTypes::GPR32Opnd, OpTypes::simm16, 14303 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14304 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 14305 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 14306 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14307 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm4_andi, 14308 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm4_andi, 14309 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, 14310 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 14311 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14312 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14313 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14314 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 14315 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_64, 14316 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 14317 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, 14318 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, 14319 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14320 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14321 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14322 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14323 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14324 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14325 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14326 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14327 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 14328 OpTypes::GPR32Opnd, OpTypes::simm16, 14329 OpTypes::GPR32Opnd, OpTypes::simm16, 14330 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 14331 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14332 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14333 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14334 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14335 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14336 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14337 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14338 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14339 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14340 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14341 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14342 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14343 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14344 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14345 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14346 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14347 OpTypes::CPU16Regs, OpTypes::simm16, 14348 OpTypes::CPU16Regs, OpTypes::simm16, 14349 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14350 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 14351 OpTypes::CPU16Regs, OpTypes::CPU16RegsPlusSP, OpTypes::simm16, 14352 OpTypes::simm16, 14353 OpTypes::simm16, 14354 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14355 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14356 OpTypes::brtarget10_mm, 14357 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14358 OpTypes::brtarget, 14359 OpTypes::brtarget26, 14360 OpTypes::brtarget26_mm, 14361 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2, OpTypes::GPR32Opnd, 14362 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2, OpTypes::GPR32Opnd, 14363 OpTypes::GPR64Opnd, OpTypes::uimm5_64_report_uimm6, OpTypes::brtarget, 14364 OpTypes::GPR64Opnd, OpTypes::uimm5_64, OpTypes::brtarget, 14365 OpTypes::GPR64Opnd, OpTypes::uimm5_64_report_uimm6, OpTypes::brtarget, 14366 OpTypes::GPR64Opnd, OpTypes::uimm5_64, OpTypes::brtarget, 14367 OpTypes::brtarget26, 14368 OpTypes::brtarget10_mm, 14369 OpTypes::FGR64Opnd, OpTypes::brtarget, 14370 OpTypes::FGR64Opnd, OpTypes::brtarget_mm, 14371 OpTypes::FCCRegsOpnd, OpTypes::brtarget, 14372 OpTypes::FCCRegsOpnd, OpTypes::brtarget, 14373 OpTypes::FCCRegsOpnd, OpTypes::brtarget_mm, 14374 OpTypes::FGR64Opnd, OpTypes::brtarget, 14375 OpTypes::FGR64Opnd, OpTypes::brtarget_mm, 14376 OpTypes::FCCRegsOpnd, OpTypes::brtarget, 14377 OpTypes::FCCRegsOpnd, OpTypes::brtarget, 14378 OpTypes::FCCRegsOpnd, OpTypes::brtarget_mm, 14379 OpTypes::COP2Opnd, OpTypes::brtarget, 14380 OpTypes::COP2Opnd, OpTypes::brtarget_mm, 14381 OpTypes::COP2Opnd, OpTypes::brtarget, 14382 OpTypes::COP2Opnd, OpTypes::brtarget_mm, 14383 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, 14384 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, 14385 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, 14386 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 14387 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14388 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14389 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14390 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14391 OpTypes::brtarget26_mm, 14392 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14393 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, 14394 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14395 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, 14396 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14397 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14398 OpTypes::GPRMM16Opnd, OpTypes::brtarget7_mm, 14399 OpTypes::GPR32Opnd, OpTypes::brtarget, 14400 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14401 OpTypes::GPR32Opnd, OpTypes::brtarget21, 14402 OpTypes::GPRMM16Opnd, OpTypes::brtarget7_mm, 14403 OpTypes::GPR64Opnd, OpTypes::brtarget21, 14404 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14405 OpTypes::GPR32Opnd, OpTypes::brtarget21_mm, 14406 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14407 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14408 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, 14409 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14410 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14411 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, 14412 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14413 OpTypes::GPR32Opnd, OpTypes::brtarget, 14414 OpTypes::GPR64Opnd, OpTypes::brtarget, 14415 OpTypes::GPR32Opnd, OpTypes::brtarget, 14416 OpTypes::GPR32Opnd, OpTypes::brtarget, 14417 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14418 OpTypes::GPR32Opnd, OpTypes::brtarget, 14419 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14420 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14421 OpTypes::GPR32Opnd, OpTypes::brtarget, 14422 OpTypes::GPR64Opnd, OpTypes::brtarget, 14423 OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14424 OpTypes::GPR32Opnd, OpTypes::brtarget, 14425 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14426 OpTypes::GPR32Opnd, OpTypes::brtarget, 14427 OpTypes::GPR64Opnd, OpTypes::brtarget, 14428 OpTypes::GPR32Opnd, OpTypes::brtarget, 14429 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14430 OpTypes::GPR32Opnd, OpTypes::brtarget, 14431 OpTypes::GPR64Opnd, OpTypes::brtarget, 14432 OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14433 OpTypes::GPR32Opnd, OpTypes::brtarget, 14434 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14435 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, 14436 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, 14437 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, 14438 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 14439 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14440 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14441 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14442 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14443 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, 14444 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, 14445 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, 14446 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 14447 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14448 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14449 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14450 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14451 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14452 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14453 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14454 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14455 OpTypes::GPR32Opnd, OpTypes::brtarget, 14456 OpTypes::GPR64Opnd, OpTypes::brtarget, 14457 OpTypes::GPR32Opnd, OpTypes::brtarget, 14458 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14459 OpTypes::GPR32Opnd, OpTypes::brtarget, 14460 OpTypes::GPR64Opnd, OpTypes::brtarget, 14461 OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14462 OpTypes::GPR32Opnd, OpTypes::brtarget, 14463 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14464 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14465 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, 14466 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14467 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14468 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, 14469 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14470 OpTypes::GPR32Opnd, OpTypes::brtarget, 14471 OpTypes::GPR64Opnd, OpTypes::brtarget, 14472 OpTypes::GPR32Opnd, OpTypes::brtarget, 14473 OpTypes::GPR32Opnd, OpTypes::brtarget, 14474 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14475 OpTypes::GPR32Opnd, OpTypes::brtarget, 14476 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14477 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14478 OpTypes::GPR32Opnd, OpTypes::brtarget, 14479 OpTypes::GPR64Opnd, OpTypes::brtarget, 14480 OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14481 OpTypes::GPR32Opnd, OpTypes::brtarget, 14482 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14483 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, 14484 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14485 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, 14486 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14487 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14488 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, 14489 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14490 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, 14491 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, 14492 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, 14493 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, 14494 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, 14495 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 14496 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14497 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14498 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14499 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14500 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14501 OpTypes::GPRMM16Opnd, OpTypes::brtarget7_mm, 14502 OpTypes::GPR32Opnd, OpTypes::brtarget, 14503 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14504 OpTypes::GPR32Opnd, OpTypes::brtarget21, 14505 OpTypes::GPRMM16Opnd, OpTypes::brtarget7_mm, 14506 OpTypes::GPR64Opnd, OpTypes::brtarget21, 14507 OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14508 OpTypes::GPR32Opnd, OpTypes::brtarget21_mm, 14509 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_mm, 14510 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14511 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtargetr6, 14512 OpTypes::MSA128BOpnd, OpTypes::brtarget, 14513 OpTypes::MSA128DOpnd, OpTypes::brtarget, 14514 OpTypes::MSA128HOpnd, OpTypes::brtarget, 14515 OpTypes::MSA128BOpnd, OpTypes::brtarget, 14516 OpTypes::MSA128WOpnd, OpTypes::brtarget, 14517 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, 14518 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtargetr6, 14519 OpTypes::brtarget, 14520 OpTypes::brtarget1SImm16, 14521 OpTypes::brtarget_mm, 14522 OpTypes::uimm10, OpTypes::uimm10, 14523 OpTypes::uimm4, 14524 OpTypes::uimm4, 14525 OpTypes::uimm10, OpTypes::uimm10, 14526 OpTypes::uimm10, OpTypes::uimm10, 14527 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, 14528 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14529 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, 14530 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, 14531 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, 14532 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 14533 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14534 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14535 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14536 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14537 OpTypes::MSA128BOpnd, OpTypes::brtarget, 14538 OpTypes::MSA128DOpnd, OpTypes::brtarget, 14539 OpTypes::MSA128HOpnd, OpTypes::brtarget, 14540 OpTypes::MSA128BOpnd, OpTypes::brtarget, 14541 OpTypes::MSA128WOpnd, OpTypes::brtarget, 14542 OpTypes::CPU16Regs, OpTypes::brtarget, 14543 OpTypes::CPU16Regs, OpTypes::brtarget, 14544 OpTypes::brtarget, 14545 OpTypes::brtarget, 14546 OpTypes::CPU16Regs, OpTypes::brtarget, 14547 OpTypes::CPU16Regs, OpTypes::brtarget, 14548 /**/ 14549 OpTypes::simm16, 14550 OpTypes::simm16, 14551 OpTypes::simm16, 14552 OpTypes::simm16, 14553 -1, OpTypes::simm16, OpTypes::uimm5, 14554 -1, OpTypes::simm9, OpTypes::uimm5, 14555 -1, OpTypes::simm9, OpTypes::uimm5, 14556 -1, OpTypes::simm12, OpTypes::uimm5, 14557 -1, OpTypes::simm12, OpTypes::uimm5, 14558 -1, OpTypes::simm9, OpTypes::uimm5, 14559 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14560 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14561 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14562 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14563 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 14564 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 14565 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 14566 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 14567 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14568 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14569 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14570 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, 14571 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, 14572 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, 14573 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, 14574 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14575 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14576 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14577 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14578 OpTypes::GPR32Opnd, OpTypes::CCROpnd, 14579 OpTypes::GPR32Opnd, OpTypes::CCROpnd, 14580 OpTypes::GPR32Opnd, OpTypes::COP2Opnd, 14581 OpTypes::GPR32Opnd, OpTypes::MSA128CROpnd, 14582 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5, 14583 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5, 14584 OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5, 14585 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5, 14586 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14587 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14588 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14589 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14590 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, 14591 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, 14592 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, 14593 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, 14594 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, 14595 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, 14596 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, 14597 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 14598 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14599 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14600 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14601 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14602 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14603 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14604 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14605 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14606 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14607 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14608 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14609 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14610 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, 14611 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, 14612 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, 14613 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, 14614 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, 14615 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, 14616 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, 14617 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 14618 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14619 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14620 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14621 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14622 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14623 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14624 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14625 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14626 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14627 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14628 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14629 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14630 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14631 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14632 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14633 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14634 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14635 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14636 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14637 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14638 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14639 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14640 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14641 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14642 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14643 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14644 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14645 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14646 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14647 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14648 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14649 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14650 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14651 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14652 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14653 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14654 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14655 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14656 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14657 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14658 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14659 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14660 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14661 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14662 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14663 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14664 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14665 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14666 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14667 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 14668 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14669 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14670 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14671 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14672 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14673 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14674 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14675 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14676 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14677 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14678 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14679 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14680 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14681 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14682 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14683 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14684 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14685 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14686 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14687 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14688 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14689 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14690 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14691 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14692 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14693 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14694 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14695 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14696 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14697 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14698 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14699 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14700 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14701 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14702 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14703 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14704 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14705 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14706 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14707 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14708 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14709 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14710 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14711 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14712 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14713 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14714 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14715 OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14716 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14717 OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14718 OpTypes::GPR32Opnd, OpTypes::MSA128BOpnd, OpTypes::uimm4_ptr, 14719 OpTypes::GPR64Opnd, OpTypes::MSA128DOpnd, OpTypes::uimm1_ptr, 14720 OpTypes::GPR32Opnd, OpTypes::MSA128HOpnd, OpTypes::uimm3_ptr, 14721 OpTypes::GPR32Opnd, OpTypes::MSA128WOpnd, OpTypes::uimm2_ptr, 14722 OpTypes::GPR32Opnd, OpTypes::MSA128BOpnd, OpTypes::uimm4_ptr, 14723 OpTypes::GPR32Opnd, OpTypes::MSA128HOpnd, OpTypes::uimm3_ptr, 14724 OpTypes::GPR32Opnd, OpTypes::MSA128WOpnd, OpTypes::uimm2_ptr, 14725 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14726 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14727 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14728 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14729 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14730 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14731 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14732 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14733 OpTypes::CCROpnd, OpTypes::GPR32Opnd, 14734 OpTypes::CCROpnd, OpTypes::GPR32Opnd, 14735 OpTypes::COP2Opnd, OpTypes::GPR32Opnd, 14736 OpTypes::MSA128CROpnd, OpTypes::GPR32Opnd, 14737 OpTypes::AFGR64Opnd, OpTypes::FGR32Opnd, 14738 OpTypes::AFGR64Opnd, OpTypes::FGR32Opnd, 14739 OpTypes::AFGR64Opnd, OpTypes::FGR32Opnd, 14740 OpTypes::AFGR64Opnd, OpTypes::FGR32Opnd, 14741 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14742 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14743 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14744 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14745 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14746 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14747 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14748 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14749 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14750 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14751 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14752 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14753 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14754 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 14755 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 14756 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 14757 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 14758 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 14759 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 14760 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 14761 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 14762 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14763 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14764 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14765 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 14766 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 14767 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 14768 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 14769 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14770 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14771 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14772 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14773 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14774 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14775 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14776 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14777 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14778 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14779 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14780 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14781 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14782 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14783 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14784 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14785 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14786 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14787 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14788 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14789 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14790 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14791 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14792 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14793 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14794 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14795 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14796 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14797 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14798 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14799 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14800 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14801 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14802 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14803 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14804 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14805 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14806 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14807 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14808 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14809 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14810 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14811 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14812 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14813 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14814 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14815 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14816 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14817 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14818 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14819 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14820 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14821 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14822 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14823 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14824 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14825 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14826 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14827 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14828 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14829 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14830 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14831 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14832 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14833 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14834 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14835 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14836 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14837 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14838 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14839 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14840 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14841 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14842 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14843 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14844 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14845 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14846 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14847 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14848 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14849 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14850 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14851 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14852 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14853 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14854 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14855 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14856 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14857 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14858 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14859 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14860 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14861 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14862 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14863 OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 14864 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14865 OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 14866 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14867 OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 14868 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 14869 OpTypes::CPU16Regs, OpTypes::simm16, 14870 OpTypes::CPU16Regs, OpTypes::simm16, 14871 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14872 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm16_64, 14873 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm16_64, 14874 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14875 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_altrelaxed, 14876 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm3, 14877 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_altrelaxed, 14878 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16, 14879 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14880 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14881 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14882 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14883 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14884 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14885 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14886 /**/ 14887 /**/ 14888 /**/ 14889 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5_report_uimm6, OpTypes::uimm5_plus1_report_uimm6, 14890 OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5_report_uimm6, OpTypes::uimm5_plus1, 14891 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5_plus33, 14892 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5_plus32, OpTypes::uimm5_plus1, 14893 OpTypes::GPR32Opnd, 14894 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, OpTypes::uimm5_inssize_plus1, OpTypes::GPR64Opnd, 14895 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm_range_2_64, OpTypes::GPR64Opnd, 14896 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5_plus32, OpTypes::uimm5_inssize_plus1, OpTypes::GPR64Opnd, 14897 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14898 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14899 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14900 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 14901 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14902 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14903 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14904 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14905 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14906 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 14907 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14908 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14909 OpTypes::GPR32Opnd, 14910 OpTypes::GPR32Opnd, 14911 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm2_plus1, 14912 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm2_plus1, 14913 OpTypes::GPR64Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 14914 OpTypes::GPR64Opnd, OpTypes::FGR64Opnd, 14915 OpTypes::GPR64Opnd, OpTypes::COP2Opnd, OpTypes::uimm3, 14916 OpTypes::GPR64Opnd, OpTypes::uimm16, 14917 OpTypes::GPR64Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 14918 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14919 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14920 OpTypes::GPR32Opnd, 14921 OpTypes::COP0Opnd, OpTypes::GPR64Opnd, OpTypes::uimm3, 14922 OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, 14923 OpTypes::COP2Opnd, OpTypes::GPR64Opnd, OpTypes::uimm3, 14924 OpTypes::GPR64Opnd, OpTypes::uimm16, 14925 OpTypes::COP0Opnd, OpTypes::GPR64Opnd, OpTypes::uimm3, 14926 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14927 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14928 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14929 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14930 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14931 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14932 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14933 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14934 OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14935 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14936 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14937 OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14938 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14939 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14940 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14941 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14942 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14943 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14944 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14945 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14946 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14947 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14948 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14949 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14950 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14951 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14952 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14953 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14954 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14955 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14956 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14957 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14958 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14959 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14960 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14961 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14962 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14963 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14964 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14965 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14966 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14967 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14968 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14969 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14970 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14971 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14972 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14973 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 14974 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 14975 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 14976 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14977 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14978 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14979 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14980 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14981 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14982 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14983 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 14984 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, 14985 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, 14986 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, 14987 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14988 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14989 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 14990 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, 14991 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, 14992 OpTypes::GPR64, OpTypes::GPR32, 14993 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, 14994 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, 14995 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, 14996 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, 14997 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, 14998 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, 14999 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, 15000 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15001 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15002 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15003 OpTypes::GPR32Opnd, 15004 OpTypes::GPR32Opnd, 15005 OpTypes::GPR32Opnd, 15006 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 15007 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 15008 /**/ 15009 /**/ 15010 /**/ 15011 OpTypes::GPR32Opnd, 15012 OpTypes::GPR32Opnd, 15013 OpTypes::GPR32Opnd, 15014 OpTypes::GPR32Opnd, 15015 /**/ 15016 /**/ 15017 /**/ 15018 /**/ 15019 /**/ 15020 OpTypes::GPR32Opnd, 15021 OpTypes::GPR32Opnd, 15022 OpTypes::GPR32Opnd, 15023 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_plus1, 15024 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15025 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15026 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15027 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15028 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15029 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15030 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15031 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15032 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15033 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15034 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15035 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15036 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15037 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15038 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15039 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, 15040 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15041 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15042 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15043 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15044 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15045 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15046 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15047 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, 15048 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5, 15049 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5, 15050 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_plus1, 15051 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_plus1, 15052 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15053 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15054 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15055 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15056 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15057 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15058 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15059 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15060 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15061 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15062 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15063 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15064 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15065 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15066 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15067 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15068 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15069 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15070 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15071 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15072 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15073 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15074 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15075 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15076 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15077 OpTypes::AFGR64, OpTypes::AFGR64, OpTypes::condcode, 15078 OpTypes::AFGR64, OpTypes::AFGR64, OpTypes::condcode, 15079 OpTypes::FGR64, OpTypes::FGR64, OpTypes::condcode, 15080 OpTypes::FGR32, OpTypes::FGR32, OpTypes::condcode, 15081 OpTypes::FGR32, OpTypes::FGR32, OpTypes::condcode, 15082 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15083 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15084 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15085 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15086 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15087 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15088 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15089 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15090 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15091 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15092 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15093 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15094 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15095 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15096 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15097 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15098 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15099 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15100 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15101 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15102 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15103 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15104 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15105 OpTypes::MSA128HOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15106 OpTypes::MSA128WOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15107 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15108 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15109 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, 15110 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, 15111 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, 15112 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, 15113 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15114 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15115 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15116 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15117 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, 15118 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, 15119 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, 15120 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, 15121 OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, 15122 OpTypes::MSA128DOpnd, OpTypes::GPR64Opnd, 15123 OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, 15124 OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, 15125 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15126 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15127 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15128 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15129 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 15130 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 15131 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 15132 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 15133 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 15134 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 15135 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15136 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15137 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15138 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15139 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15140 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15141 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15142 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15143 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15144 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15145 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15146 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15147 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15148 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15149 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15150 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15151 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15152 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15153 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15154 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15155 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15156 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15157 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15158 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15159 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15160 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15161 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15162 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15163 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15164 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15165 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15166 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15167 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15168 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15169 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15170 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15171 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15172 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15173 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15174 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15175 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15176 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15177 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15178 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15179 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15180 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15181 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15182 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15183 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15184 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15185 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15186 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15187 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15188 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15189 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15190 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15191 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15192 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15193 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15194 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15195 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15196 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15197 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15198 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15199 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15200 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15201 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15202 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15203 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15204 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15205 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15206 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15207 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15208 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15209 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15210 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15211 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15212 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15213 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15214 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15215 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15216 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15217 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15218 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15219 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15220 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15221 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15222 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15223 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15224 OpTypes::MSA128HOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15225 OpTypes::MSA128WOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15226 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15227 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15228 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15229 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15230 OpTypes::GPR32Opnd, 15231 OpTypes::GPR32Opnd, 15232 OpTypes::GPR32Opnd, OpTypes::uimm2, 15233 OpTypes::GPR32Opnd, OpTypes::uimm2, 15234 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15235 OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15236 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15237 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15238 OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15239 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15240 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15241 OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15242 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15243 OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15244 OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15245 OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15246 OpTypes::uimm10, 15247 OpTypes::uimm10, 15248 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15249 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15250 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15251 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15252 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15253 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15254 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15255 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15256 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15257 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15258 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15259 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15260 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15261 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15262 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15263 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15264 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_inssize_plus1, OpTypes::GPR32Opnd, 15265 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, OpTypes::uimm4, 15266 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR64Opnd, OpTypes::uimm1, 15267 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 15268 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, OpTypes::uimm2, 15269 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15270 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm4, OpTypes::MSA128BOpnd, OpTypes::uimmz, 15271 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm1, OpTypes::MSA128DOpnd, OpTypes::uimmz, 15272 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm3, OpTypes::MSA128HOpnd, OpTypes::uimmz, 15273 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm2, OpTypes::MSA128WOpnd, OpTypes::uimmz, 15274 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15275 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_inssize_plus1, OpTypes::GPR32Opnd, 15276 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_inssize_plus1, OpTypes::GPR32Opnd, 15277 OpTypes::jmptarget, 15278 OpTypes::calltarget, 15279 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15280 OpTypes::GPR32Opnd, 15281 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15282 OpTypes::GPR32Opnd, 15283 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15284 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15285 OpTypes::GPR32Opnd, 15286 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15287 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15288 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15289 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15290 OpTypes::calltarget_mm, 15291 OpTypes::calltarget, 15292 OpTypes::calltarget, 15293 OpTypes::calltarget_mm, 15294 OpTypes::GPR32Opnd, OpTypes::calloffset16, 15295 OpTypes::GPR64Opnd, OpTypes::calloffset16, 15296 OpTypes::GPR32Opnd, OpTypes::calloffset16, 15297 OpTypes::GPR32Opnd, OpTypes::jmpoffset16, 15298 OpTypes::GPR64Opnd, OpTypes::jmpoffset16, 15299 OpTypes::GPR32Opnd, OpTypes::jmpoffset16, 15300 OpTypes::GPR32Opnd, 15301 OpTypes::GPR32Opnd, 15302 OpTypes::GPR64Opnd, 15303 OpTypes::uimm5_lsl2, 15304 OpTypes::GPR32Opnd, 15305 OpTypes::GPR32Opnd, 15306 OpTypes::uimm5_lsl2, 15307 OpTypes::GPR32Opnd, 15308 OpTypes::GPR64Opnd, 15309 OpTypes::GPR64Opnd, 15310 OpTypes::GPR32Opnd, 15311 OpTypes::GPR32Opnd, 15312 OpTypes::jmptarget_mm, 15313 OpTypes::uimm26, 15314 OpTypes::uimm26, 15315 /**/ 15316 /**/ 15317 OpTypes::CPU16Regs, 15318 OpTypes::CPU16Regs, 15319 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15320 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15321 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15322 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15323 OpTypes::GPRMM16Opnd, -1, OpTypes::simm4, 15324 OpTypes::GPR32Opnd, -1, -1, 15325 OpTypes::GPR32Opnd, -1, -1, 15326 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15327 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15328 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15329 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15330 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15331 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15332 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15333 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15334 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15335 OpTypes::AFGR64Opnd, -1, OpTypes::simm16, 15336 OpTypes::FGR64Opnd, -1, OpTypes::simm16, 15337 OpTypes::FGR64Opnd, -1, OpTypes::simm16, 15338 OpTypes::AFGR64Opnd, -1, OpTypes::simm16, 15339 OpTypes::COP2Opnd, -1, OpTypes::simm16, 15340 OpTypes::COP2Opnd, OpTypes::GPR32, OpTypes::simm11, 15341 OpTypes::COP2Opnd, -1, OpTypes::simm11, 15342 OpTypes::COP3Opnd, -1, OpTypes::simm16, 15343 OpTypes::MSA128BOpnd, OpTypes::vsplat_simm10, 15344 OpTypes::MSA128DOpnd, OpTypes::vsplat_simm10, 15345 OpTypes::MSA128HOpnd, OpTypes::vsplat_simm10, 15346 OpTypes::MSA128WOpnd, OpTypes::vsplat_simm10, 15347 OpTypes::GPR64Opnd, -1, OpTypes::simm16, OpTypes::GPR64Opnd, 15348 OpTypes::GPR64Opnd, OpTypes::simm18_lsl3, 15349 OpTypes::GPR64Opnd, -1, OpTypes::simm16, OpTypes::GPR64Opnd, 15350 OpTypes::AFGR64Opnd, -1, -1, 15351 OpTypes::FGR64Opnd, -1, -1, 15352 OpTypes::MSA128BOpnd, -1, OpTypes::simm10, 15353 OpTypes::MSA128DOpnd, -1, OpTypes::simm10_lsl3, 15354 OpTypes::MSA128HOpnd, -1, OpTypes::simm10_lsl1, 15355 OpTypes::MSA128WOpnd, -1, OpTypes::simm10_lsl2, 15356 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15357 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15358 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15359 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15360 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15361 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15362 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15363 OpTypes::GPRMM16Opnd, -1, OpTypes::simm4, 15364 OpTypes::GPR32Opnd, -1, -1, 15365 OpTypes::GPR32Opnd, -1, -1, 15366 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15367 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15368 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15369 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15370 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15371 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15372 OpTypes::GPRMM16Opnd, OpTypes::li16_imm, 15373 OpTypes::GPRMM16Opnd, OpTypes::li16_imm, 15374 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15375 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15376 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15377 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15378 OpTypes::GPR64Opnd, -1, OpTypes::simm9, 15379 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15380 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15381 OpTypes::GPR32Opnd, -1, OpTypes::simm12, 15382 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15383 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15384 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2_plus1, 15385 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2_plus1, 15386 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2_plus1, 15387 OpTypes::GPR32Opnd, OpTypes::uimm16, 15388 OpTypes::AFGR64Opnd, -1, -1, 15389 OpTypes::FGR64Opnd, -1, -1, 15390 OpTypes::FGR64Opnd, -1, -1, 15391 OpTypes::GPR32Opnd, OpTypes::uimm16_relaxed, 15392 OpTypes::GPR64Opnd, OpTypes::uimm16_64_relaxed, 15393 OpTypes::GPR32Opnd, OpTypes::uimm16_relaxed, 15394 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15395 OpTypes::GPRMM16Opnd, -1, OpTypes::simm4, 15396 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15397 OpTypes::FGR32Opnd, -1, OpTypes::simm16, 15398 OpTypes::FGR32Opnd, -1, OpTypes::simm16, 15399 OpTypes::COP2Opnd, -1, OpTypes::simm16, 15400 OpTypes::COP2Opnd, OpTypes::GPR32, OpTypes::simm11, 15401 OpTypes::COP2Opnd, -1, OpTypes::simm11, 15402 OpTypes::COP3Opnd, -1, OpTypes::simm16, 15403 OpTypes::DSPROpnd, -1, OpTypes::simm16, 15404 OpTypes::DSPROpnd, -1, OpTypes::simm16, 15405 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15406 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15407 OpTypes::GPRMM16Opnd, -1, OpTypes::simm7_lsl2, 15408 OpTypes::GPR32Opnd, -1, OpTypes::simm16, OpTypes::GPR32Opnd, 15409 OpTypes::GPR64Opnd, -1, OpTypes::simm16, OpTypes::GPR64Opnd, 15410 OpTypes::GPR32Opnd, -1, OpTypes::simm9, OpTypes::GPR32Opnd, 15411 OpTypes::GPR32Opnd, -1, OpTypes::simm9, OpTypes::GPR32Opnd, 15412 OpTypes::GPR32Opnd, -1, OpTypes::simm12, OpTypes::GPR32Opnd, 15413 OpTypes::reglist16, -1, OpTypes::uimm8, 15414 OpTypes::reglist16, -1, OpTypes::uimm8, 15415 OpTypes::reglist, -1, OpTypes::simm12, 15416 OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, 15417 OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, 15418 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm12, 15419 OpTypes::GPR32Opnd, -1, OpTypes::simm16, OpTypes::GPR32Opnd, 15420 OpTypes::GPR64Opnd, -1, OpTypes::simm16, OpTypes::GPR64Opnd, 15421 OpTypes::GPR32Opnd, -1, OpTypes::simm9, OpTypes::GPR32Opnd, 15422 OpTypes::GPR32Opnd, -1, OpTypes::simm9, OpTypes::GPR32Opnd, 15423 OpTypes::GPR32Opnd, -1, OpTypes::simm12, OpTypes::GPR32Opnd, 15424 OpTypes::GPR32Opnd, -1, OpTypes::simm5, 15425 OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, 15426 OpTypes::GPR32Opnd, -1, OpTypes::simm12, 15427 OpTypes::GPR32Opnd, -1, -1, 15428 OpTypes::FGR32Opnd, -1, -1, 15429 OpTypes::FGR32Opnd, -1, -1, 15430 OpTypes::GPR32Opnd, -1, -1, 15431 OpTypes::GPR32Opnd, -1, -1, 15432 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15433 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15434 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15435 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 15436 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 15437 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 15438 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 15439 OpTypes::CPU16Regs, OpTypes::simm16, 15440 OpTypes::CPU16Regs, OpTypes::simm16, 15441 OpTypes::CPU16Regs, OpTypes::simm16, 15442 OpTypes::CPU16Regs, OpTypes::pcrel16, OpTypes::i32imm, 15443 OpTypes::CPU16Regs, OpTypes::pcrel16, OpTypes::i32imm, 15444 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 15445 OpTypes::CPU16Regs, OpTypes::CPU16RegsPlusSP, OpTypes::simm16, 15446 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15447 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15448 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15449 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15450 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15451 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15452 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15453 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15454 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15455 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15456 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15457 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15458 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15459 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15460 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15461 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15462 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15463 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15464 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15465 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15466 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15467 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15468 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15469 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15470 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15471 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15472 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15473 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15474 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15475 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15476 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15477 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15478 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15479 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15480 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15481 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15482 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15483 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, 15484 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, 15485 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, 15486 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, 15487 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, 15488 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, 15489 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, 15490 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 15491 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15492 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15493 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15494 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15495 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15496 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15497 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15498 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15499 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15500 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15501 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15502 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15503 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15504 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15505 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15506 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15507 OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 15508 OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 15509 OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 15510 OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, 15511 OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 15512 OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 15513 OpTypes::GPR32Opnd, OpTypes::COP2Opnd, OpTypes::uimm3, 15514 OpTypes::GPR32Opnd, OpTypes::COP2Opnd, 15515 OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 15516 OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 15517 OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 15518 OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, 15519 OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, 15520 OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, 15521 OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, 15522 OpTypes::GPR32Opnd, OpTypes::COP2Opnd, 15523 OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 15524 OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, 15525 OpTypes::GPR32Opnd, 15526 OpTypes::GPR32Opnd, 15527 OpTypes::GPR64Opnd, 15528 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15529 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15530 OpTypes::GPR32Opnd, 15531 OpTypes::GPR32Opnd, 15532 OpTypes::GPR32Opnd, 15533 OpTypes::GPR64Opnd, 15534 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15535 OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15536 OpTypes::GPR32Opnd, 15537 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm1, OpTypes::uimm3, OpTypes::uimm1, 15538 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15539 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15540 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15541 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15542 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, 15543 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, 15544 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, 15545 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, 15546 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, 15547 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, 15548 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, 15549 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 15550 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15551 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15552 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15553 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15554 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15555 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15556 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15557 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15558 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15559 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15560 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15561 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15562 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15563 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15564 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15565 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15566 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15567 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15568 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15569 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15570 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15571 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15572 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15573 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15574 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15575 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15576 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15577 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15578 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15579 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15580 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15581 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15582 OpTypes::GPRMM16OpndMovePPairFirst, OpTypes::GPRMM16OpndMovePPairSecond, OpTypes::GPRMM16OpndMoveP, OpTypes::GPRMM16OpndMoveP, 15583 OpTypes::GPRMM16OpndMovePPairFirst, OpTypes::GPRMM16OpndMovePPairSecond, OpTypes::GPRMM16OpndMoveP, OpTypes::GPRMM16OpndMoveP, 15584 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15585 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, 15586 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, 15587 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, 15588 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, 15589 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR64Opnd, 15590 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, 15591 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, 15592 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, 15593 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, OpTypes::FGR64Opnd, 15594 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, 15595 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15596 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR64Opnd, OpTypes::FGR32Opnd, 15597 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, 15598 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, 15599 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, 15600 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15601 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, 15602 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15603 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 15604 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 15605 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, 15606 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, 15607 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, 15608 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, 15609 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR64Opnd, 15610 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, 15611 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, 15612 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, 15613 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, OpTypes::FGR64Opnd, 15614 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, 15615 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15616 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR64Opnd, OpTypes::FGR32Opnd, 15617 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, 15618 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, 15619 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, 15620 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15621 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, 15622 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15623 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 15624 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, 15625 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15626 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15627 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15628 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15629 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15630 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15631 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15632 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15633 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15634 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15635 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15636 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15637 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15638 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15639 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15640 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15641 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15642 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15643 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15644 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15645 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15646 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15647 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15648 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15649 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15650 OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 15651 OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 15652 OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, 15653 OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, 15654 OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, 15655 OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, 15656 OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, 15657 OpTypes::COP2Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 15658 OpTypes::COP2Opnd, OpTypes::GPR32Opnd, 15659 OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 15660 OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 15661 OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 15662 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, 15663 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, 15664 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, 15665 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, 15666 OpTypes::COP2Opnd, OpTypes::GPR32Opnd, 15667 OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 15668 OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, 15669 OpTypes::GPR32Opnd, 15670 OpTypes::GPR64Opnd, 15671 OpTypes::HI32DSPOpnd, OpTypes::GPR32Opnd, 15672 OpTypes::HI32DSPOpnd, OpTypes::GPR32Opnd, 15673 OpTypes::GPR32Opnd, 15674 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15675 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15676 OpTypes::GPR32Opnd, 15677 OpTypes::GPR64Opnd, 15678 OpTypes::LO32DSPOpnd, OpTypes::GPR32Opnd, 15679 OpTypes::LO32DSPOpnd, OpTypes::GPR32Opnd, 15680 OpTypes::GPR32Opnd, 15681 OpTypes::GPR64Opnd, 15682 OpTypes::GPR64Opnd, 15683 OpTypes::GPR64Opnd, 15684 OpTypes::GPR64Opnd, 15685 OpTypes::GPR64Opnd, 15686 OpTypes::GPR64Opnd, 15687 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm1, OpTypes::uimm3, OpTypes::uimm1, 15688 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15689 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15690 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15691 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15692 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15693 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15694 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15695 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15696 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15697 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15698 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15699 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15700 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15701 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15702 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15703 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15704 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15705 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15706 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15707 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15708 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15709 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15710 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15711 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15712 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15713 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15714 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15715 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15716 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15717 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15718 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15719 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15720 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15721 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15722 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15723 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15724 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15725 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15726 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15727 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15728 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15729 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15730 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15731 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15732 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15733 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15734 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15735 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15736 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15737 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15738 OpTypes::CPU16Regs, 15739 OpTypes::CPU16Regs, 15740 OpTypes::GPR32, OpTypes::CPU16Regs, 15741 OpTypes::CPU16Regs, OpTypes::GPR32, 15742 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15743 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15744 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15745 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15746 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15747 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15748 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15749 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15750 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15751 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15752 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15753 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15754 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15755 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15756 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15757 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15758 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15759 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15760 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15761 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15762 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, 15763 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15764 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15765 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15766 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 15767 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 15768 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 15769 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 15770 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15771 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 15772 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 15773 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15774 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, 15775 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 15776 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15777 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15778 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15779 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 15780 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_64, 15781 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 15782 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 15783 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15784 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15785 /**/ 15786 /**/ 15787 /**/ 15788 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15789 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15790 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15791 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15792 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15793 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15794 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15795 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15796 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 15797 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 15798 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 15799 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 15800 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15801 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15802 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15803 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15804 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15805 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15806 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15807 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15808 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15809 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15810 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15811 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15812 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15813 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15814 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15815 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, 15816 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, 15817 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, 15818 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, 15819 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15820 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15821 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15822 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15823 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15824 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15825 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15826 OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15827 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15828 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15829 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15830 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15831 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15832 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15833 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15834 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15835 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15836 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 15837 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, 15838 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, 15839 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, 15840 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, 15841 -1, OpTypes::simm16, OpTypes::uimm5, 15842 -1, OpTypes::simm9, OpTypes::uimm5, 15843 -1, OpTypes::simm9, OpTypes::uimm5, 15844 -1, -1, OpTypes::uimm5, 15845 -1, OpTypes::simm12, OpTypes::uimm5, 15846 -1, OpTypes::simm12, OpTypes::uimm5, 15847 -1, OpTypes::simm9, OpTypes::uimm5, 15848 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, 15849 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, 15850 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, 15851 OpTypes::GPR32Opnd, OpTypes::DSPROpnd, 15852 OpTypes::GPR32Opnd, OpTypes::uimm10, 15853 OpTypes::GPR32Opnd, OpTypes::uimm7, 15854 OpTypes::GPR32Opnd, OpTypes::HWRegsOpnd, OpTypes::uimm8, 15855 OpTypes::GPR64Opnd, OpTypes::HWRegsOpnd, OpTypes::uimm8, 15856 OpTypes::GPR32Opnd, OpTypes::HWRegsOpnd, OpTypes::uimm8, 15857 OpTypes::GPR32Opnd, OpTypes::HWRegsOpnd, OpTypes::uimm3, 15858 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15859 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15860 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15861 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15862 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15863 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15864 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15865 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15866 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15867 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15868 OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15869 OpTypes::DSPROpnd, OpTypes::simm10, 15870 OpTypes::DSPROpnd, OpTypes::simm10, 15871 OpTypes::DSPROpnd, OpTypes::uimm8, 15872 OpTypes::DSPROpnd, OpTypes::uimm8, 15873 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15874 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15875 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15876 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15877 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 15878 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15879 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15880 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 15881 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15882 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15883 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 15884 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 15885 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 15886 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 15887 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15888 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 15889 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15890 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15891 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15892 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15893 OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, 15894 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15895 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15896 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15897 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15898 /**/ 15899 /**/ 15900 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15901 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15902 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm3, 15903 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm6, 15904 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm4, 15905 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm5, 15906 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm3, 15907 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm6, 15908 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm4, 15909 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm5, 15910 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15911 OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, 15912 OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, 15913 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15914 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15915 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15916 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15917 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15918 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15919 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15920 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15921 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15922 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, -1, OpTypes::simm9, 15923 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15924 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15925 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm12, 15926 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15927 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15928 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15929 OpTypes::uimm20, 15930 OpTypes::uimm4, 15931 OpTypes::uimm4, 15932 OpTypes::uimm10, 15933 OpTypes::uimm20, 15934 OpTypes::uimm20, 15935 OpTypes::AFGR64Opnd, -1, OpTypes::simm16, 15936 OpTypes::FGR64Opnd, -1, OpTypes::simm16, 15937 OpTypes::FGR64Opnd, -1, OpTypes::simm16, 15938 OpTypes::AFGR64Opnd, -1, OpTypes::simm16, 15939 OpTypes::COP2Opnd, -1, OpTypes::simm16, 15940 OpTypes::COP2Opnd, OpTypes::GPR32, OpTypes::simm11, 15941 OpTypes::COP2Opnd, -1, OpTypes::simm11, 15942 OpTypes::COP3Opnd, -1, OpTypes::simm16, 15943 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15944 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15945 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15946 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15947 OpTypes::AFGR64Opnd, -1, -1, 15948 OpTypes::FGR64Opnd, -1, -1, 15949 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15950 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15951 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15952 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15953 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15954 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15955 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15956 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15957 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15958 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15959 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15960 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15961 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15962 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15963 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15964 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15965 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15966 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15967 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15968 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15969 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15970 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 15971 OpTypes::FGR32Opnd, OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15972 OpTypes::FGR32Opnd, OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 15973 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 15974 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm10_64, 15975 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 15976 OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, 15977 OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, 15978 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 15979 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15980 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 15981 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm8, 15982 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm8, 15983 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm8, 15984 OpTypes::ACC64DSPOpnd, OpTypes::simm6, OpTypes::ACC64DSPOpnd, 15985 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15986 OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, 15987 OpTypes::ACC64DSPOpnd, OpTypes::simm6, OpTypes::ACC64DSPOpnd, 15988 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15989 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15990 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15991 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15992 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15993 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 15994 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15995 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 15996 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 15997 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 15998 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, 15999 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, 16000 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 16001 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 16002 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16003 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16004 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16005 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16006 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16007 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16008 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16009 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16010 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16011 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16012 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16013 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16014 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 16015 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 16016 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, 16017 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, 16018 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 16019 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 16020 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, 16021 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, 16022 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16023 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16024 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16025 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16026 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16027 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, 16028 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 16029 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, 16030 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, 16031 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, 16032 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 16033 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 16034 OpTypes::uimm16, 16035 OpTypes::uimm16, 16036 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm4, 16037 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm1, 16038 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm3, 16039 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm2, 16040 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, 16041 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR32Opnd, 16042 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, 16043 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, 16044 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16045 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm3_shift, 16046 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm3_shift, 16047 OpTypes::GPR64, OpTypes::GPR32, 16048 OpTypes::GPR64, OpTypes::GPR64, 16049 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, 16050 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, 16051 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, 16052 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 16053 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16054 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16055 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16056 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16057 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16058 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16059 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16060 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16061 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16062 OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 16063 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16064 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 16065 OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::simm16_64, 16066 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 16067 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 16068 OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::simm16_64, 16069 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, 16070 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16071 OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 16072 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16073 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 16074 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm10_64, 16075 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm4, 16076 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm1, 16077 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm3, 16078 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm2, 16079 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, 16080 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR32Opnd, 16081 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, 16082 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, 16083 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16084 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, 16085 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, 16086 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, 16087 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 16088 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm3, 16089 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm6, 16090 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm4, 16091 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm5, 16092 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16093 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16094 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16095 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16096 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16097 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16098 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16099 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16100 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16101 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16102 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16103 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16104 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm3_shift, 16105 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm3_shift, 16106 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, 16107 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, 16108 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, 16109 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 16110 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm3, 16111 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm6, 16112 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm4, 16113 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm5, 16114 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16115 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16116 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16117 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16118 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16119 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16120 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16121 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16122 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16123 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, 16124 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16125 /**/ 16126 /**/ 16127 /**/ 16128 OpTypes::MSA128BOpnd, -1, OpTypes::simm10, 16129 OpTypes::MSA128DOpnd, -1, OpTypes::simm10_lsl3, 16130 OpTypes::MSA128HOpnd, -1, OpTypes::simm10_lsl1, 16131 OpTypes::MSA128WOpnd, -1, OpTypes::simm10_lsl2, 16132 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16133 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16134 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16135 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16136 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16137 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16138 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16139 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16140 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16141 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16142 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16143 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16144 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16145 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16146 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16147 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16148 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16149 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16150 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16151 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16152 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16153 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16154 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16155 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16156 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16157 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16158 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16159 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16160 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16161 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16162 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16163 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 16164 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 16165 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16166 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16167 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16168 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16169 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16170 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16171 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16172 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16173 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16174 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16175 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16176 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16177 OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, 16178 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, 16179 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, 16180 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, 16181 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, 16182 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16183 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16184 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16185 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16186 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16187 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16188 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16189 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16190 OpTypes::AFGR64Opnd, -1, -1, 16191 OpTypes::FGR64Opnd, -1, -1, 16192 OpTypes::FGR64Opnd, -1, -1, 16193 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 16194 OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, 16195 OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, 16196 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 16197 OpTypes::FGR32Opnd, -1, OpTypes::simm16, 16198 OpTypes::FGR32Opnd, -1, OpTypes::simm16, 16199 OpTypes::COP2Opnd, -1, OpTypes::simm16, 16200 OpTypes::COP2Opnd, OpTypes::GPR32, OpTypes::simm11, 16201 OpTypes::COP2Opnd, -1, OpTypes::simm11, 16202 OpTypes::COP3Opnd, -1, OpTypes::simm16, 16203 OpTypes::DSPROpnd, -1, OpTypes::simm16, 16204 OpTypes::DSPROpnd, -1, OpTypes::simm16, 16205 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 16206 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 16207 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 16208 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 16209 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 16210 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 16211 OpTypes::GPR32Opnd, -1, OpTypes::simm12, 16212 OpTypes::reglist16, -1, OpTypes::uimm8, 16213 OpTypes::reglist16, -1, OpTypes::uimm8, 16214 OpTypes::reglist, -1, OpTypes::simm12, 16215 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm12, 16216 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 16217 OpTypes::GPR64Opnd, -1, OpTypes::simm16, 16218 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 16219 OpTypes::GPR32Opnd, -1, OpTypes::simm9, 16220 OpTypes::GPR32Opnd, -1, OpTypes::simm12, 16221 OpTypes::GPR32Opnd, -1, OpTypes::simm5, 16222 OpTypes::GPR32Opnd, -1, OpTypes::simm5, 16223 OpTypes::FGR32Opnd, -1, -1, 16224 OpTypes::FGR32Opnd, -1, -1, 16225 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 16226 OpTypes::GPR32Opnd, -1, OpTypes::simm16, 16227 OpTypes::uimm5, 16228 -1, OpTypes::simm16, 16229 -1, OpTypes::simm16, 16230 -1, OpTypes::simm16, 16231 OpTypes::uimm5, 16232 OpTypes::uimm5, 16233 OpTypes::uimm20, 16234 OpTypes::uimm10, 16235 /**/ 16236 /**/ 16237 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 16238 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 16239 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 16240 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 16241 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::uimm5, 16242 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 16243 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 16244 OpTypes::CPU16Regs, OpTypes::simm16, 16245 OpTypes::CPU16Regs, OpTypes::simm16, 16246 OpTypes::CPU16Regs, OpTypes::simm16, 16247 OpTypes::CPU16Regs, OpTypes::simm16, 16248 OpTypes::CPU16Regs, OpTypes::CPU16Regs, 16249 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::uimm5, 16250 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 16251 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::uimm5, 16252 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 16253 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 16254 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, 16255 OpTypes::CPU16Regs, OpTypes::CPU16RegsPlusSP, OpTypes::simm16, 16256 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, 16257 OpTypes::GPR32Opnd, OpTypes::simm16, 16258 OpTypes::GPR32Opnd, OpTypes::simm16, 16259 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, 16260 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, 16261 OpTypes::GPR32Opnd, OpTypes::simm16, 16262 OpTypes::GPR32Opnd, OpTypes::simm16, 16263 OpTypes::GPR32Opnd, OpTypes::simm16, 16264 OpTypes::GPR32Opnd, OpTypes::simm16, 16265 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, 16266 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, 16267 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, 16268 /**/ 16269 /**/ 16270 /**/ 16271 /**/ 16272 /**/ 16273 /**/ 16274 /**/ 16275 /**/ 16276 /**/ 16277 /**/ 16278 /**/ 16279 /**/ 16280 /**/ 16281 /**/ 16282 /**/ 16283 /**/ 16284 /**/ 16285 /**/ 16286 /**/ 16287 /**/ 16288 /**/ 16289 /**/ 16290 /**/ 16291 /**/ 16292 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, 16293 OpTypes::GPR32Opnd, OpTypes::simm16, 16294 OpTypes::GPR32Opnd, OpTypes::simm16, 16295 OpTypes::GPR32Opnd, OpTypes::simm16, 16296 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, 16297 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, 16298 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, 16299 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, 16300 OpTypes::GPR32Opnd, OpTypes::simm16, 16301 OpTypes::GPR32Opnd, OpTypes::simm16, 16302 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, 16303 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 16304 OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, 16305 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 16306 OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, 16307 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 16308 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 16309 OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, 16310 OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, 16311 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 16312 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 16313 OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, 16314 OpTypes::GPR32Opnd, OpTypes::simm16, 16315 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16316 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16317 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 16318 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 16319 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 16320 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16321 OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, 16322 OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, 16323 OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, 16324 /**/ 16325 OpTypes::uimm10, 16326 OpTypes::uimm10, 16327 OpTypes::GPR32Opnd, OpTypes::uimm10, 16328 OpTypes::GPR32Opnd, OpTypes::uimm7, 16329 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16330 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16331 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16332 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16333 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16334 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 16335 OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, 16336 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, 16337 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, 16338 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 16339 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16340 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16341 OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, 16342 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 16343 OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_64, 16344 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, 16345 OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, 16346 OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, 16347 }; 16348 return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; 16349} 16350} // end namespace Mips 16351} // end namespace llvm 16352#endif // GET_INSTRINFO_OPERAND_TYPE 16353 16354#ifdef GET_INSTRMAP_INFO 16355#undef GET_INSTRMAP_INFO 16356namespace llvm { 16357 16358namespace Mips { 16359 16360enum Arch { 16361 Arch_dsp, 16362 Arch_mmdsp, 16363 Arch_mipsr6, 16364 Arch_micromipsr6, 16365 Arch_se, 16366 Arch_micromips 16367}; 16368 16369// Dsp2MicroMips 16370LLVM_READONLY 16371int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) { 16372static const uint16_t Dsp2MicroMipsTable[][3] = { 16373 { Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM }, 16374 { Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 }, 16375 { Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM }, 16376 { Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 }, 16377 { Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 }, 16378 { Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 }, 16379 { Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 }, 16380 { Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM }, 16381 { Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM }, 16382 { Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM }, 16383 { Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM }, 16384 { Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 }, 16385 { Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 }, 16386 { Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 }, 16387 { Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM }, 16388 { Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 }, 16389 { Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM }, 16390 { Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM }, 16391 { Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 }, 16392 { Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 }, 16393 { Mips::BITREV, Mips::BITREV, Mips::BITREV_MM }, 16394 { Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM }, 16395 { Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 }, 16396 { Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 }, 16397 { Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 }, 16398 { Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM }, 16399 { Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM }, 16400 { Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM }, 16401 { Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM }, 16402 { Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM }, 16403 { Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM }, 16404 { Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM }, 16405 { Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM }, 16406 { Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM }, 16407 { Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 }, 16408 { Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 }, 16409 { Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM }, 16410 { Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM }, 16411 { Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM }, 16412 { Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM }, 16413 { Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 }, 16414 { Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 }, 16415 { Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 }, 16416 { Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 }, 16417 { Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM }, 16418 { Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM }, 16419 { Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM }, 16420 { Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM }, 16421 { Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 }, 16422 { Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 }, 16423 { Mips::EXTP, Mips::EXTP, Mips::EXTP_MM }, 16424 { Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM }, 16425 { Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM }, 16426 { Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM }, 16427 { Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM }, 16428 { Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM }, 16429 { Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM }, 16430 { Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM }, 16431 { Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM }, 16432 { Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM }, 16433 { Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM }, 16434 { Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM }, 16435 { Mips::INSV, Mips::INSV, Mips::INSV_MM }, 16436 { Mips::LBUX, Mips::LBUX, Mips::LBUX_MM }, 16437 { Mips::LHX, Mips::LHX, Mips::LHX_MM }, 16438 { Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM }, 16439 { Mips::LWX, Mips::LWX, Mips::LWX_MM }, 16440 { Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM }, 16441 { Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM }, 16442 { Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM }, 16443 { Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM }, 16444 { Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM }, 16445 { Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM }, 16446 { Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM }, 16447 { Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM }, 16448 { Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM }, 16449 { Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM }, 16450 { Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM }, 16451 { Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM }, 16452 { Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM }, 16453 { Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM }, 16454 { Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM }, 16455 { Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM }, 16456 { Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM }, 16457 { Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM }, 16458 { Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM }, 16459 { Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 }, 16460 { Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 }, 16461 { Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 }, 16462 { Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM }, 16463 { Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 }, 16464 { Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM }, 16465 { Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM }, 16466 { Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 }, 16467 { Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 }, 16468 { Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM }, 16469 { Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM }, 16470 { Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM }, 16471 { Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM }, 16472 { Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM }, 16473 { Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM }, 16474 { Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM }, 16475 { Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM }, 16476 { Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM }, 16477 { Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM }, 16478 { Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM }, 16479 { Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM }, 16480 { Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM }, 16481 { Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM }, 16482 { Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM }, 16483 { Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM }, 16484 { Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM }, 16485 { Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 }, 16486 { Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 }, 16487 { Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 }, 16488 { Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 }, 16489 { Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM }, 16490 { Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM }, 16491 { Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM }, 16492 { Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM }, 16493 { Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM }, 16494 { Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM }, 16495 { Mips::SHILO, Mips::SHILO, Mips::SHILO_MM }, 16496 { Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM }, 16497 { Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM }, 16498 { Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM }, 16499 { Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM }, 16500 { Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM }, 16501 { Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM }, 16502 { Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM }, 16503 { Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM }, 16504 { Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM }, 16505 { Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM }, 16506 { Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 }, 16507 { Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM }, 16508 { Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 }, 16509 { Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM }, 16510 { Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM }, 16511 { Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 }, 16512 { Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM }, 16513 { Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 }, 16514 { Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM }, 16515 { Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 }, 16516 { Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM }, 16517 { Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 }, 16518 { Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM }, 16519 { Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 }, 16520 { Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 }, 16521 { Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 }, 16522 { Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 }, 16523 { Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM }, 16524 { Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM }, 16525 { Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM }, 16526 { Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 }, 16527 { Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 }, 16528 { Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 }, 16529 { Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM }, 16530 { Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 }, 16531 { Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM }, 16532 { Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM }, 16533}; // End of Dsp2MicroMipsTable 16534 16535 unsigned mid; 16536 unsigned start = 0; 16537 unsigned end = 160; 16538 while (start < end) { 16539 mid = start + (end - start)/2; 16540 if (Opcode == Dsp2MicroMipsTable[mid][0]) { 16541 break; 16542 } 16543 if (Opcode < Dsp2MicroMipsTable[mid][0]) 16544 end = mid; 16545 else 16546 start = mid + 1; 16547 } 16548 if (start == end) 16549 return -1; // Instruction doesn't exist in this table. 16550 16551 if (inArch == Arch_dsp) 16552 return Dsp2MicroMipsTable[mid][1]; 16553 if (inArch == Arch_mmdsp) 16554 return Dsp2MicroMipsTable[mid][2]; 16555 return -1;} 16556 16557// MipsR62MicroMipsR6 16558LLVM_READONLY 16559int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) { 16560static const uint16_t MipsR62MicroMipsR6Table[][3] = { 16561 { Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 }, 16562 { Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 }, 16563 { Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 }, 16564 { Mips::AUI, Mips::AUI, Mips::AUI_MMR6 }, 16565 { Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 }, 16566 { Mips::BALC, Mips::BALC, Mips::BALC_MMR6 }, 16567 { Mips::BC, Mips::BC, Mips::BC_MMR6 }, 16568 { Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 }, 16569 { Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 }, 16570 { Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 }, 16571 { Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 }, 16572 { Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 }, 16573 { Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 }, 16574 { Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 }, 16575 { Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 }, 16576 { Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 }, 16577 { Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 }, 16578 { Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 }, 16579 { Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 }, 16580 { Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 }, 16581 { Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 }, 16582 { Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 }, 16583 { Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 }, 16584 { Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 }, 16585 { Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 }, 16586 { Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 }, 16587 { Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 }, 16588 { Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 }, 16589 { Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 }, 16590 { Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 }, 16591 { Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 }, 16592 { Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 }, 16593 { Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 }, 16594 { Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 }, 16595 { Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 }, 16596 { Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 }, 16597 { Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 }, 16598 { Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 }, 16599 { Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 }, 16600 { Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 }, 16601 { Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 }, 16602 { Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 }, 16603 { Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 }, 16604 { Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 }, 16605 { Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 }, 16606 { Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 }, 16607 { Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 }, 16608 { Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 }, 16609 { Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 }, 16610 { Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 }, 16611 { Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 }, 16612 { Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 }, 16613 { Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 }, 16614 { Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 }, 16615 { Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 }, 16616 { Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 }, 16617 { Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 }, 16618 { Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 }, 16619 { Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 }, 16620 { Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 }, 16621 { Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 }, 16622 { Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 }, 16623 { Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 }, 16624 { Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U }, 16625 { Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U }, 16626 { Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U }, 16627 { Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U }, 16628 { Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U }, 16629 { Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U }, 16630 { Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U }, 16631 { Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U }, 16632 { Mips::DIV, Mips::DIV, Mips::DIV_MMR6 }, 16633 { Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 }, 16634 { Mips::DVP, Mips::DVP, Mips::DVP_MMR6 }, 16635 { Mips::EVP, Mips::EVP, Mips::EVP_MMR6 }, 16636 { Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 }, 16637 { Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 }, 16638 { Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 }, 16639 { Mips::JIC, Mips::JIC, Mips::JIC_MMR6 }, 16640 { Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 }, 16641 { Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 }, 16642 { Mips::MOD, Mips::MOD, Mips::MOD_MMR6 }, 16643 { Mips::MODU, Mips::MODU, Mips::MODU_MMR6 }, 16644 { Mips::MUH, Mips::MUH, Mips::MUH_MMR6 }, 16645 { Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 }, 16646 { Mips::MULU, Mips::MULU, Mips::MULU_MMR6 }, 16647 { Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 }, 16648 { Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 }, 16649 { Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 }, 16650 { Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 }, 16651 { Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 }, 16652 { Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 }, 16653 { Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 }, 16654 { Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 }, 16655 { Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 }, 16656 { Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 }, 16657}; // End of MipsR62MicroMipsR6Table 16658 16659 unsigned mid; 16660 unsigned start = 0; 16661 unsigned end = 96; 16662 while (start < end) { 16663 mid = start + (end - start)/2; 16664 if (Opcode == MipsR62MicroMipsR6Table[mid][0]) { 16665 break; 16666 } 16667 if (Opcode < MipsR62MicroMipsR6Table[mid][0]) 16668 end = mid; 16669 else 16670 start = mid + 1; 16671 } 16672 if (start == end) 16673 return -1; // Instruction doesn't exist in this table. 16674 16675 if (inArch == Arch_mipsr6) 16676 return MipsR62MicroMipsR6Table[mid][1]; 16677 if (inArch == Arch_micromipsr6) 16678 return MipsR62MicroMipsR6Table[mid][2]; 16679 return -1;} 16680 16681// Std2MicroMips 16682LLVM_READONLY 16683int Std2MicroMips(uint16_t Opcode, enum Arch inArch) { 16684static const uint16_t Std2MicroMipsTable[][3] = { 16685 { Mips::ADD, Mips::ADD, Mips::ADD_MM }, 16686 { Mips::ADDi, Mips::ADDi, Mips::ADDi_MM }, 16687 { Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM }, 16688 { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM }, 16689 { Mips::AND, Mips::AND, Mips::AND_MM }, 16690 { Mips::ANDi, Mips::ANDi, Mips::ANDi_MM }, 16691 { Mips::BC1F, Mips::BC1F, Mips::BC1F_MM }, 16692 { Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U }, 16693 { Mips::BC1T, Mips::BC1T, Mips::BC1T_MM }, 16694 { Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U }, 16695 { Mips::BEQ, Mips::BEQ, Mips::BEQ_MM }, 16696 { Mips::BEQL, Mips::BEQL, (uint16_t)-1U }, 16697 { Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM }, 16698 { Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM }, 16699 { Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U }, 16700 { Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U }, 16701 { Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM }, 16702 { Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U }, 16703 { Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM }, 16704 { Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U }, 16705 { Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM }, 16706 { Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM }, 16707 { Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U }, 16708 { Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U }, 16709 { Mips::BNE, Mips::BNE, Mips::BNE_MM }, 16710 { Mips::BNEL, Mips::BNEL, (uint16_t)-1U }, 16711 { Mips::BREAK, Mips::BREAK, Mips::BREAK_MM }, 16712 { Mips::CACHE, Mips::CACHE, Mips::CACHE_MM }, 16713 { Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM }, 16714 { Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM }, 16715 { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM }, 16716 { Mips::CFC1, Mips::CFC1, Mips::CFC1_MM }, 16717 { Mips::CLO, Mips::CLO, Mips::CLO_MM }, 16718 { Mips::CLZ, Mips::CLZ, Mips::CLZ_MM }, 16719 { Mips::CTC1, Mips::CTC1, Mips::CTC1_MM }, 16720 { Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM }, 16721 { Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM }, 16722 { Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM }, 16723 { Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM }, 16724 { Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM }, 16725 { Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM }, 16726 { Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM }, 16727 { Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM }, 16728 { Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM }, 16729 { Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM }, 16730 { Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM }, 16731 { Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM }, 16732 { Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM }, 16733 { Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM }, 16734 { Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM }, 16735 { Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM }, 16736 { Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM }, 16737 { Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM }, 16738 { Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM }, 16739 { Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM }, 16740 { Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM }, 16741 { Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM }, 16742 { Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM }, 16743 { Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM }, 16744 { Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM }, 16745 { Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM }, 16746 { Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM }, 16747 { Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM }, 16748 { Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM }, 16749 { Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM }, 16750 { Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM }, 16751 { Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM }, 16752 { Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM }, 16753 { Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM }, 16754 { Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM }, 16755 { Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM }, 16756 { Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM }, 16757 { Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM }, 16758 { Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM }, 16759 { Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM }, 16760 { Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM }, 16761 { Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM }, 16762 { Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM }, 16763 { Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM }, 16764 { Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM }, 16765 { Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM }, 16766 { Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM }, 16767 { Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM }, 16768 { Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM }, 16769 { Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM }, 16770 { Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM }, 16771 { Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM }, 16772 { Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM }, 16773 { Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM }, 16774 { Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM }, 16775 { Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM }, 16776 { Mips::DERET, Mips::DERET, Mips::DERET_MM }, 16777 { Mips::DI, Mips::DI, Mips::DI_MM }, 16778 { Mips::EHB, Mips::EHB, Mips::EHB_MM }, 16779 { Mips::EI, Mips::EI, Mips::EI_MM }, 16780 { Mips::ERET, Mips::ERET, Mips::ERET_MM }, 16781 { Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U }, 16782 { Mips::EXT, Mips::EXT, Mips::EXT_MM }, 16783 { Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM }, 16784 { Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM }, 16785 { Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM }, 16786 { Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM }, 16787 { Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM }, 16788 { Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM }, 16789 { Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM }, 16790 { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM }, 16791 { Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM }, 16792 { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM }, 16793 { Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM }, 16794 { Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM }, 16795 { Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM }, 16796 { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM }, 16797 { Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM }, 16798 { Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM }, 16799 { Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM }, 16800 { Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM }, 16801 { Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM }, 16802 { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM }, 16803 { Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM }, 16804 { Mips::INS, Mips::INS, Mips::INS_MM }, 16805 { Mips::J, Mips::J, Mips::J_MM }, 16806 { Mips::JAL, Mips::JAL, Mips::JAL_MM }, 16807 { Mips::JALX, Mips::JALX, Mips::JALX_MM }, 16808 { Mips::JR, Mips::JR, Mips::JR_MM }, 16809 { Mips::LB, Mips::LB, Mips::LB_MM }, 16810 { Mips::LBE, Mips::LBE, Mips::LBE_MM }, 16811 { Mips::LBu, Mips::LBu, Mips::LBu_MM }, 16812 { Mips::LBuE, Mips::LBuE, Mips::LBuE_MM }, 16813 { Mips::LDC1, Mips::LDC1, Mips::LDC1_MM }, 16814 { Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM }, 16815 { Mips::LH, Mips::LH, Mips::LH_MM }, 16816 { Mips::LHE, Mips::LHE, Mips::LHE_MM }, 16817 { Mips::LHu, Mips::LHu, Mips::LHu_MM }, 16818 { Mips::LHuE, Mips::LHuE, Mips::LHuE_MM }, 16819 { Mips::LLE, Mips::LLE, Mips::LLE_MM }, 16820 { Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM }, 16821 { Mips::LUi, Mips::LUi, Mips::LUi_MM }, 16822 { Mips::LW, Mips::LW, Mips::LW_MM }, 16823 { Mips::LWC1, Mips::LWC1, Mips::LWC1_MM }, 16824 { Mips::LWE, Mips::LWE, Mips::LWE_MM }, 16825 { Mips::LWL, Mips::LWL, Mips::LWL_MM }, 16826 { Mips::LWLE, Mips::LWLE, Mips::LWLE_MM }, 16827 { Mips::LWR, Mips::LWR, Mips::LWR_MM }, 16828 { Mips::LWRE, Mips::LWRE, Mips::LWRE_MM }, 16829 { Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM }, 16830 { Mips::LWu, Mips::LWu, Mips::LWU_MM }, 16831 { Mips::MADD, Mips::MADD, Mips::MADD_MM }, 16832 { Mips::MADDU, Mips::MADDU, Mips::MADDU_MM }, 16833 { Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM }, 16834 { Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM }, 16835 { Mips::MFC1, Mips::MFC1, Mips::MFC1_MM }, 16836 { Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM }, 16837 { Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM }, 16838 { Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM }, 16839 { Mips::MFHI, Mips::MFHI, Mips::MFHI_MM }, 16840 { Mips::MFLO, Mips::MFLO, Mips::MFLO_MM }, 16841 { Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM }, 16842 { Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM }, 16843 { Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM }, 16844 { Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM }, 16845 { Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM }, 16846 { Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM }, 16847 { Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM }, 16848 { Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM }, 16849 { Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM }, 16850 { Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM }, 16851 { Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM }, 16852 { Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM }, 16853 { Mips::MSUB, Mips::MSUB, Mips::MSUB_MM }, 16854 { Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM }, 16855 { Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM }, 16856 { Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM }, 16857 { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM }, 16858 { Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM }, 16859 { Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM }, 16860 { Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM }, 16861 { Mips::MTHI, Mips::MTHI, Mips::MTHI_MM }, 16862 { Mips::MTLO, Mips::MTLO, Mips::MTLO_MM }, 16863 { Mips::MUL, Mips::MUL, Mips::MUL_MM }, 16864 { Mips::MULT, Mips::MULT, Mips::MULT_MM }, 16865 { Mips::MULTu, Mips::MULTu, Mips::MULTu_MM }, 16866 { Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM }, 16867 { Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM }, 16868 { Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM }, 16869 { Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM }, 16870 { Mips::NOR, Mips::NOR, Mips::NOR_MM }, 16871 { Mips::OR, Mips::OR, Mips::OR_MM }, 16872 { Mips::ORi, Mips::ORi, Mips::ORi_MM }, 16873 { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM }, 16874 { Mips::PREF, Mips::PREF, Mips::PREF_MM }, 16875 { Mips::PREFE, Mips::PREFE, Mips::PREFE_MM }, 16876 { Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM }, 16877 { Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM }, 16878 { Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM }, 16879 { Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM }, 16880 { Mips::ROTR, Mips::ROTR, Mips::ROTR_MM }, 16881 { Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM }, 16882 { Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM }, 16883 { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM }, 16884 { Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM }, 16885 { Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM }, 16886 { Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM }, 16887 { Mips::SB, Mips::SB, Mips::SB_MM }, 16888 { Mips::SBE, Mips::SBE, Mips::SBE_MM }, 16889 { Mips::SCE, Mips::SCE, Mips::SCE_MM }, 16890 { Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM }, 16891 { Mips::SDC1, Mips::SDC1, Mips::SDC1_MM }, 16892 { Mips::SDIV, Mips::SDIV, Mips::SDIV_MM }, 16893 { Mips::SEB, Mips::SEB, Mips::SEB_MM }, 16894 { Mips::SEH, Mips::SEH, Mips::SEH_MM }, 16895 { Mips::SH, Mips::SH, Mips::SH_MM }, 16896 { Mips::SHE, Mips::SHE, Mips::SHE_MM }, 16897 { Mips::SLL, Mips::SLL, Mips::SLL_MM }, 16898 { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM }, 16899 { Mips::SLT, Mips::SLT, Mips::SLT_MM }, 16900 { Mips::SLTi, Mips::SLTi, Mips::SLTi_MM }, 16901 { Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM }, 16902 { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM }, 16903 { Mips::SRA, Mips::SRA, Mips::SRA_MM }, 16904 { Mips::SRAV, Mips::SRAV, Mips::SRAV_MM }, 16905 { Mips::SRL, Mips::SRL, Mips::SRL_MM }, 16906 { Mips::SRLV, Mips::SRLV, Mips::SRLV_MM }, 16907 { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM }, 16908 { Mips::SUB, Mips::SUB, Mips::SUB_MM }, 16909 { Mips::SUBu, Mips::SUBu, Mips::SUBu_MM }, 16910 { Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM }, 16911 { Mips::SW, Mips::SW, Mips::SW_MM }, 16912 { Mips::SWC1, Mips::SWC1, Mips::SWC1_MM }, 16913 { Mips::SWE, Mips::SWE, Mips::SWE_MM }, 16914 { Mips::SWL, Mips::SWL, Mips::SWL_MM }, 16915 { Mips::SWLE, Mips::SWLE, Mips::SWLE_MM }, 16916 { Mips::SWR, Mips::SWR, Mips::SWR_MM }, 16917 { Mips::SWRE, Mips::SWRE, Mips::SWRE_MM }, 16918 { Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM }, 16919 { Mips::SYNC, Mips::SYNC, Mips::SYNC_MM }, 16920 { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM }, 16921 { Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM }, 16922 { Mips::TEQ, Mips::TEQ, Mips::TEQ_MM }, 16923 { Mips::TEQI, Mips::TEQI, Mips::TEQI_MM }, 16924 { Mips::TGE, Mips::TGE, Mips::TGE_MM }, 16925 { Mips::TGEI, Mips::TGEI, Mips::TGEI_MM }, 16926 { Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM }, 16927 { Mips::TGEU, Mips::TGEU, Mips::TGEU_MM }, 16928 { Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM }, 16929 { Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM }, 16930 { Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM }, 16931 { Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM }, 16932 { Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM }, 16933 { Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM }, 16934 { Mips::TLBP, Mips::TLBP, Mips::TLBP_MM }, 16935 { Mips::TLBR, Mips::TLBR, Mips::TLBR_MM }, 16936 { Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM }, 16937 { Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM }, 16938 { Mips::TLT, Mips::TLT, Mips::TLT_MM }, 16939 { Mips::TLTI, Mips::TLTI, Mips::TLTI_MM }, 16940 { Mips::TLTU, Mips::TLTU, Mips::TLTU_MM }, 16941 { Mips::TNE, Mips::TNE, Mips::TNE_MM }, 16942 { Mips::TNEI, Mips::TNEI, Mips::TNEI_MM }, 16943 { Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM }, 16944 { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM }, 16945 { Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM }, 16946 { Mips::UDIV, Mips::UDIV, Mips::UDIV_MM }, 16947 { Mips::WAIT, Mips::WAIT, Mips::WAIT_MM }, 16948 { Mips::WSBH, Mips::WSBH, Mips::WSBH_MM }, 16949 { Mips::XOR, Mips::XOR, Mips::XOR_MM }, 16950 { Mips::XORi, Mips::XORi, Mips::XORi_MM }, 16951}; // End of Std2MicroMipsTable 16952 16953 unsigned mid; 16954 unsigned start = 0; 16955 unsigned end = 266; 16956 while (start < end) { 16957 mid = start + (end - start)/2; 16958 if (Opcode == Std2MicroMipsTable[mid][0]) { 16959 break; 16960 } 16961 if (Opcode < Std2MicroMipsTable[mid][0]) 16962 end = mid; 16963 else 16964 start = mid + 1; 16965 } 16966 if (start == end) 16967 return -1; // Instruction doesn't exist in this table. 16968 16969 if (inArch == Arch_se) 16970 return Std2MicroMipsTable[mid][1]; 16971 if (inArch == Arch_micromips) 16972 return Std2MicroMipsTable[mid][2]; 16973 return -1;} 16974 16975// Std2MicroMipsR6 16976LLVM_READONLY 16977int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) { 16978static const uint16_t Std2MicroMipsR6Table[][3] = { 16979 { Mips::ADD, Mips::ADD, Mips::ADD_MMR6 }, 16980 { Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 }, 16981 { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 }, 16982 { Mips::AND, Mips::AND, Mips::AND_MMR6 }, 16983 { Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 }, 16984 { Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 }, 16985 { Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 }, 16986 { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 }, 16987 { Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U }, 16988 { Mips::DI, Mips::DI, Mips::DI_MMR6 }, 16989 { Mips::EI, Mips::EI, Mips::EI_MMR6 }, 16990 { Mips::EXT, Mips::EXT, Mips::EXT_MMR6 }, 16991 { Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U }, 16992 { Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 }, 16993 { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 }, 16994 { Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 }, 16995 { Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U }, 16996 { Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U }, 16997 { Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U }, 16998 { Mips::INS, Mips::INS, Mips::INS_MMR6 }, 16999 { Mips::LDC1, Mips::LDC1, (uint16_t)-1U }, 17000 { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 }, 17001 { Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 }, 17002 { Mips::LW, Mips::LW, Mips::LW_MMR6 }, 17003 { Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 }, 17004 { Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 }, 17005 { Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 }, 17006 { Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U }, 17007 { Mips::NOR, Mips::NOR, Mips::NOR_MMR6 }, 17008 { Mips::OR, Mips::OR, Mips::OR_MMR6 }, 17009 { Mips::ORi, Mips::ORi, Mips::ORI_MMR6 }, 17010 { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 }, 17011 { Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 }, 17012 { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 }, 17013 { Mips::SB, Mips::SB, Mips::SB_MMR6 }, 17014 { Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 }, 17015 { Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 }, 17016 { Mips::SEB, Mips::SEB, (uint16_t)-1U }, 17017 { Mips::SEH, Mips::SEH, (uint16_t)-1U }, 17018 { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 }, 17019 { Mips::SUB, Mips::SUB, Mips::SUB_MMR6 }, 17020 { Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 }, 17021 { Mips::SW, Mips::SW, Mips::SW_MMR6 }, 17022 { Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 }, 17023 { Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 }, 17024 { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 }, 17025 { Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 }, 17026 { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 }, 17027 { Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 }, 17028 { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 }, 17029 { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 }, 17030}; // End of Std2MicroMipsR6Table 17031 17032 unsigned mid; 17033 unsigned start = 0; 17034 unsigned end = 51; 17035 while (start < end) { 17036 mid = start + (end - start)/2; 17037 if (Opcode == Std2MicroMipsR6Table[mid][0]) { 17038 break; 17039 } 17040 if (Opcode < Std2MicroMipsR6Table[mid][0]) 17041 end = mid; 17042 else 17043 start = mid + 1; 17044 } 17045 if (start == end) 17046 return -1; // Instruction doesn't exist in this table. 17047 17048 if (inArch == Arch_se) 17049 return Std2MicroMipsR6Table[mid][1]; 17050 if (inArch == Arch_micromipsr6) 17051 return Std2MicroMipsR6Table[mid][2]; 17052 return -1;} 17053 17054} // end namespace Mips 17055} // end namespace llvm 17056#endif // GET_INSTRMAP_INFO 17057 17058