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Searched refs:FSIN (Results 1 – 25 of 62) sorted by relevance

123

/external/one-true-awk/
Dawk.h147 #define FSIN 9 macro
Dlex.c79 { "sin", FSIN, BLTIN },
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DConstrainedOps.def80 FUNCTION(sin, 1, 1, experimental_constrained_sin, FSIN)
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
DBasicTTIImpl.h745 ISDs.push_back(ISD::FSIN); in getIntrinsicInstrCost()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator
DBasicTTIImpl.h1223 ISDs.push_back(ISD::FSIN);
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp159 case ISD::FSIN: return "fsin"; in getOperationName()
DLegalizeFloatTypes.cpp102 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1039 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
1882 case ISD::FSIN: in PromoteFloatResult()
DLegalizeDAG.cpp2180 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2181 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3149 case ISD::FSIN: in ExpandNode()
3817 case ISD::FSIN: in ConvertNodeToLibcall()
4229 case ISD::FSIN: in PromoteNode()
DLegalizeVectorOps.cpp309 case ISD::FSIN: in LegalizeOp()
DLegalizeVectorTypes.cpp93 case ISD::FSIN: in ScalarizeVectorResult()
652 case ISD::FSIN: in SplitVectorResult()
2166 case ISD::FSIN: in WidenVectorResult()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.cpp81 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW, in WebAssemblyTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp196 case ISD::FSIN: return "fsin"; in getOperationName()
DLegalizeFloatTypes.cpp117 case ISD::FSIN: R = SoftenFloatRes_FSIN(N); break; in SoftenFloatResult()
1174 case ISD::FSIN: ExpandFloatRes_FSIN(N, Lo, Hi); break; in ExpandFloatResult()
2120 case ISD::FSIN: in PromoteFloatResult()
DLegalizeDAG.cpp2259 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN in useSinCos()
2260 ? ISD::FCOS : ISD::FSIN; in useSinCos()
3192 case ISD::FSIN: in ExpandNode()
3960 case ISD::FSIN: in ConvertNodeToLibcall()
4509 case ISD::FSIN: in PromoteNode()
DLegalizeVectorOps.cpp420 case ISD::FSIN: in LegalizeOp()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp145 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
488 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
775 case ISD::FSIN: in LowerTrig()
/external/AFLplusplus/dictionaries/
Dx86.dict284 "FSIN"
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp108 setOperationAction(ISD::FSIN, MVT::f32, Custom); in R600TargetLowering()
625 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
949 case ISD::FSIN: in LowerTrig()
DSIISelLowering.cpp216 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
1241 case ISD::FSIN: in LowerOperation()
2375 case ISD::FSIN: in LowerTrig()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ScheduleAtom.td891 def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp154 setOperationAction(ISD::FSIN, MVT::f128, Expand); in AArch64TargetLowering()
252 setOperationAction(ISD::FSIN, MVT::f32, Expand); in AArch64TargetLowering()
253 setOperationAction(ISD::FSIN, MVT::f64, Expand); in AArch64TargetLowering()
282 setOperationAction(ISD::FSIN, MVT::f16, Promote); in AArch64TargetLowering()
328 setOperationAction(ISD::FSIN, MVT::v4f16, Expand); in AArch64TargetLowering()
360 setOperationAction(ISD::FSIN, MVT::v8f16, Expand); in AArch64TargetLowering()
538 setOperationAction(ISD::FSIN, MVT::v1f64, Expand); in AArch64TargetLowering()
651 setOperationAction(ISD::FSIN, VT, Expand); in addTypeForNEON()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1666 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1671 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1676 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1616 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1621 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1626 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()

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