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Searched refs:LD_W (Results 1 – 19 of 19) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsSERegisterInfo.cpp74 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
91 case Mips::LD_W: in getLoadStoreOffsetAlign()
DMipsSEInstrInfo.cpp288 Opc = Mips::LD_W; in loadRegFromStack()
DMipsMSAInstrInfo.td3216 def LD_W: LD_W_ENC, LD_W_DESC;
3527 def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSERegisterInfo.cpp74 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
134 case Mips::LD_W: in getLoadStoreOffsetAlign()
DMipsInstructionSelector.cpp239 return isStore ? Mips::ST_W : Mips::LD_W; in selectLoadStoreOpCode()
DMipsSEInstrInfo.cpp357 Opc = Mips::LD_W; in loadRegFromStack()
DMipsMSAInstrInfo.td3256 def LD_W: LD_W_ENC, LD_W_DESC;
3567 def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>;
/external/webp/src/dsp/
Dmsa_macro.h60 #define LD_W(RTYPE, psrc) *((RTYPE*)(psrc)) macro
61 #define LD_UW(...) LD_W(v4u32, __VA_ARGS__)
62 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
275 out0 = LD_W(RTYPE, psrc); \
276 out1 = LD_W(RTYPE, psrc + stride); \
283 out2 = LD_W(RTYPE, psrc + 2 * stride); \
/external/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h27 #define LD_W(RTYPE, psrc) *((const RTYPE *)(psrc)) macro
28 #define LD_UW(...) LD_W(v4u32, __VA_ARGS__)
29 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp1494 case Mips::LD_W: in DecodeMSA128Mem()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp1737 case Mips::LD_W: in DecodeMSA128Mem()
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc965 58744179U, // LD_W
2754 0U, // LD_W
DMipsGenDisassemblerTables.inc3184 /* 10923 */ MCD_OPC_Decode, 180, 7, 190, 1, // Opcode: LD_W
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc1772 UINT64_C(2013265954), // LD_W
2991 case Mips::LD_W:
11234 CEFBS_HasStdEnc_HasMSA, // LD_W = 1759
DMipsGenAsmWriter.inc3000 25190433U, // LD_W
5754 0U, // LD_W
DMipsGenDAGISel.inc1315 /* 2337*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
1318 // Dst: (LD_W:{ *:[v4i32] } addrimm10lsl2:{ *:[iPTR] }:$addr)
1361 /* 2439*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::LD_W), 0|OPFL_Chain|OPFL_MemRefs,
1364 // Dst: (LD_W:{ *:[v4f32] } addrimm10lsl2:{ *:[iPTR] }:$addr)
DMipsGenInstrInfo.inc1774 LD_W = 1759,
6620 …ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1759 = LD_W
DMipsGenDisassemblerTables.inc5506 /* 13416 */ MCD::OPC_Decode, 223, 13, 178, 2, // Opcode: LD_W
DMipsGenAsmMatcher.inc6827 …{ 5472 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_Has…