| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-misched-basic-A53.ll | 5 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
7 ; specifying a subtarget, the MADD will remain near the end of the block.
|
| /external/pcre/src/sljit/ |
| D | sljitNativeARM_64.c | 109 #define MADD 0x9b000000 macro
841 return push_inst(compiler, (MADD ^ inv_bits) | RD(dst) | RN(arg1) | RM(arg2) | RT2(TMP_ZERO)); in emit_op_imm()
848 FAIL_IF(push_inst(compiler, MADD | RD(dst) | RN(arg1) | RM(arg2) | RT2(TMP_ZERO))); in emit_op_imm()
1306 FAIL_IF(push_inst(compiler, MADD | RD(SLJIT_R0) | RN(SLJIT_R0) | RM(SLJIT_R1) | RT2(TMP_ZERO))); in sljit_emit_op0()
1312 …FAIL_IF(push_inst(compiler, (MADD ^ inv_bits) | RD(SLJIT_R1) | RN(SLJIT_R0) | RM(SLJIT_R1) | RT2(T… in sljit_emit_op0()
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 645 TmpInst.setOpcode(Mips::MADD);
684 TmpInst.setOpcode(Mips::MADD);
|
| D | MipsGenSubtargetInfo.inc | 1105 {DBGFIELD("MADD") 1, false, false, 12, 2, 1, 1, 0, 0}, // #845
2789 {DBGFIELD("MADD") 1, false, false, 48, 3, 5, 1, 0, 0}, // #845
|
| D | MipsGenMCCodeEmitter.inc | 1863 UINT64_C(1879048192), // MADD
5985 case Mips::MADD:
11325 CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1850
|
| D | MipsGenAsmWriter.inc | 3091 20523U, // MADD
5845 0U, // MADD
|
| D | MipsGenInstrInfo.inc | 1865 MADD = 1850,
3625 MADD = 845,
6711 …Effects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #1850 = MADD
16831 { Mips::MADD, Mips::MADD, Mips::MADD_MM },
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | P9InstrResources.td | 401 (instregex "MADD(HD|HDU|LD|LD8)$"),
475 (instregex "F(N)?MADD(S)?_rec$"),
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 200 def : InstRW<[P5600WriteAL2MAdd], (instrs MADD, MADDU, MSUB, MSUBU,
|
| D | MipsInstrInfo.td | 2379 // MADD*/MSUB*
2380 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
2398 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
|
| D | MicroMipsInstrInfo.td | 1116 def PseudoMADD_MM : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
|
| D | MipsScheduleGeneric.td | 147 def : InstRW<[GenericWriteHILO], (instrs MADD, MADDU, MSUB, MSUBU)>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 190 // MUL/MNEG are aliases for MADD/MSUB.
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 189 // MUL/MNEG are aliases for MADD/MSUB.
|
| D | AArch64InstrInfo.td | 718 defm MADD : MulAccum<0, "madd", add>;
|
| D | AArch64InstrFormats.td | 1449 // MADD/MSUB generation is decided by MachineCombiner.cpp
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 2008 // MADD*/MSUB*
2009 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
2026 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1043 20269U, // MADD
2832 0U, // MADD
5084 // DEXT, DEXTM, DEXTU, DINS, DINSM, DINSU, EXT, EXT_MM, INS, INS_MM, MADD...
|
| D | MipsGenDisassemblerTables.inc | 1454 /* 3583 */ MCD_OPC_Decode, 130, 8, 43, // Opcode: MADD
|
| /external/OpenCSD/decoder/tests/snapshots/juno_r1_1/ds-5-dumps/ |
| D | Trace_Report_0x15_cpu_5_2015Sep17_105126.txt | 120 EL1N:0xFFFFFFC0000C5424 9B011441 MADD x1,x2,x1,x5
134 EL1N:0xFFFFFFC0000C545C 9B041442 MADD x2,x2,x4,x5
139 EL1N:0xFFFFFFC0000C5470 9B010C00 MADD x0,x0,x1,x3
|
| D | Trace_Report_0x10_cpu_0_2015Sep17_104900.txt | 10723 EL1N:0xFFFFFFC0000C5424 9B011441 MADD x1,x2,x1,x5
10737 EL1N:0xFFFFFFC0000C545C 9B041442 MADD x2,x2,x4,x5
10742 EL1N:0xFFFFFFC0000C5470 9B010C00 MADD x0,x0,x1,x3
22735 EL1N:0xFFFFFFC0000C5424 9B011441 MADD x1,x2,x1,x5
22749 EL1N:0xFFFFFFC0000C545C 9B041442 MADD x2,x2,x4,x5
22754 EL1N:0xFFFFFFC0000C5470 9B010C00 MADD x0,x0,x1,x3
31154 EL1N:0xFFFFFFC0000C5424 9B011441 MADD x1,x2,x1,x5
31168 EL1N:0xFFFFFFC0000C545C 9B041442 MADD x2,x2,x4,x5
31173 EL1N:0xFFFFFFC0000C5470 9B010C00 MADD x0,x0,x1,x3
38371 EL1N:0xFFFFFFC0000C5424 9B011441 MADD x1,x2,x1,x5
[all …]
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1489 MADD = MADD_w, enumerator
|
| D | assembler-aarch64.cc | 900 DataProcessing3Source(rd, rn, rm, AppropriateZeroRegFor(rd), MADD); in mul()
908 DataProcessing3Source(rd, rn, rm, ra, MADD); in madd()
|
| /external/OpenCSD/decoder/tests/snapshots-ete/002-ack_test_scr/ |
| D | test_TARMAC | 4018 1644 clk cpu0 IT (1608) 000943d4:0000100943d4 9b08255d O EL3h_s : MADD x29,x10,x8,x9
4105 1681 clk cpu0 IT (1645) 00094490:000010094490 9b082548 O EL3h_s : MADD x8,x10,x8,x9
4207 1725 clk cpu0 IT (1689) 00094580:000010094580 9b0826b3 O EL3h_s : MADD x19,x21,x8,x9
4261 1749 clk cpu0 IT (1713) 000945d0:0000100945d0 9b0866b3 O EL3h_s : MADD x19,x21,x8,x25
4293 1763 clk cpu0 IT (1727) 00094638:000010094638 9b0866a8 O EL3h_s : MADD x8,x21,x8,x25
4317 1772 clk cpu0 IT (1736) 0009465c:00001009465c 9b0862b3 O EL3h_s : MADD x19,x21,x8,x24
4996 2043 clk cpu0 IT (2007) 00090c40:000010090c40 9b095eb6 O EL3h_s : MADD x22,x21,x9,x23
4998 2044 clk cpu0 IT (2008) 00090c44:000010090c44 9b085a88 O EL3h_s : MADD x8,x20,x8,x22
5026 2056 clk cpu0 IT (2020) 00090c64:000010090c64 9b095ea9 O EL3h_s : MADD x9,x21,x9,x23
5028 2057 clk cpu0 IT (2021) 00090c68:000010090c68 9b082688 O EL3h_s : MADD x8,x20,x8,x9
[all …]
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1889 ### MADD ### subsection
|