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Searched refs:OpIdx (Results 1 – 25 of 165) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp70 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
76 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
82 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
88 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
94 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
101 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
107 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
124 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp62 uint32_t getLdStUImm12OpValue(const MCInst &MI, unsigned OpIdx,
68 uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
74 uint32_t getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
80 uint32_t getCondBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
86 uint32_t getLoadLiteralOpValue(const MCInst &MI, unsigned OpIdx,
93 uint32_t getMemExtendOpValue(const MCInst &MI, unsigned OpIdx,
99 uint32_t getTestBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
105 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
116 uint32_t getVecShifterOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp93 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
97 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
110 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
115 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
120 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
137 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
143 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp81 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
85 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
103 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
108 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
113 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
125 uint32_t getThumbBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
131 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all …]
/external/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp186 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints() argument
190 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); in getRegBankFromConstraints()
223 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) { in getInstrMappingImpl() local
224 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
243 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, TRI); in getInstrMappingImpl()
273 Mapping.setOperandMapping(OpIdx, RegSize, *CurRegBank); in getInstrMappingImpl()
288 for (unsigned OpIdx = 0, End = MI.getNumOperands(); OpIdx != End; ++OpIdx) { in getInstrMappingImpl() local
289 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
296 ->getOperandMapping(OpIdx) in getInstrMappingImpl()
300 Mapping.setOperandMapping(OpIdx, RegSize, *RegBank); in getInstrMappingImpl()
[all …]
DRegBankSelect.cpp365 for (unsigned OpIdx = 0, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; in computeMapping() local
366 ++OpIdx) { in computeMapping()
367 const MachineOperand &MO = MI.getOperand(OpIdx); in computeMapping()
373 DEBUG(dbgs() << "Opd" << OpIdx); in computeMapping()
375 InstrMapping.getOperandMapping(OpIdx); in computeMapping()
384 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, in computeMapping()
391 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert)); in computeMapping()
482 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local
483 MachineOperand &MO = MI.getOperand(OpIdx); in applyMapping()
485 InstrMapping.getOperandMapping(OpIdx); in applyMapping()
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc911 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
921 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
922 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
923 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
935 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
945 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
946 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
947 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
959 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
969 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp113 const MachineInstr &MI, unsigned OpIdx, const TargetInstrInfo &TII, in getRegBankFromConstraints() argument
119 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, TRI); in getRegBankFromConstraints()
124 Register Reg = MI.getOperand(OpIdx).getReg(); in getRegBankFromConstraints()
183 for (unsigned OpIdx = 0, EndIdx = MI.getNumOperands(); OpIdx != EndIdx; in getInstrMappingImpl() local
184 ++OpIdx) { in getInstrMappingImpl()
185 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
204 CurRegBank = getRegBankFromConstraints(MI, OpIdx, TII, MRI); in getInstrMappingImpl()
233 for (; OpIdx != EndIdx; ++OpIdx) { in getInstrMappingImpl()
234 const MachineOperand &MO = MI.getOperand(OpIdx); in getInstrMappingImpl()
251 OperandsMapping[OpIdx] = ValMapping; in getInstrMappingImpl()
[all …]
DCallLowering.cpp78 void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx, in setArgFlags() argument
83 if (Attrs.hasAttribute(OpIdx, Attribute::ZExt)) in setArgFlags()
85 if (Attrs.hasAttribute(OpIdx, Attribute::SExt)) in setArgFlags()
87 if (Attrs.hasAttribute(OpIdx, Attribute::InReg)) in setArgFlags()
89 if (Attrs.hasAttribute(OpIdx, Attribute::StructRet)) in setArgFlags()
91 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftSelf)) in setArgFlags()
93 if (Attrs.hasAttribute(OpIdx, Attribute::SwiftError)) in setArgFlags()
95 if (Attrs.hasAttribute(OpIdx, Attribute::ByVal)) in setArgFlags()
97 if (Attrs.hasAttribute(OpIdx, Attribute::InAlloca)) in setArgFlags()
103 auto Ty = Attrs.getAttribute(OpIdx, Attribute::ByVal).getValueAsType(); in setArgFlags()
[all …]
DRegBankSelect.cpp467 for (unsigned OpIdx = 0, EndOpIdx = InstrMapping.getNumOperands(); in computeMapping() local
468 OpIdx != EndOpIdx; ++OpIdx) { in computeMapping()
469 const MachineOperand &MO = MI.getOperand(OpIdx); in computeMapping()
475 LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n'); in computeMapping()
477 InstrMapping.getOperandMapping(OpIdx); in computeMapping()
486 RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this, in computeMapping()
493 RepairingPlacement(MI, OpIdx, *TRI, *this, RepairingPlacement::Insert)); in computeMapping()
594 unsigned OpIdx = RepairPt.getOpIdx(); in applyMapping() local
595 MachineOperand &MO = MI.getOperand(OpIdx); in applyMapping()
597 InstrMapping.getOperandMapping(OpIdx); in applyMapping()
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc744 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
749 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
759 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
760 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
761 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
772 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
777 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
786 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
787 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
788 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc1238 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1239 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1252 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1253 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
1266 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1
1267 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // R2
1280 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
1281 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
1294 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // R1
1295 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // R2
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h88 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
94 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
120 << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx in executeMatchTable()
186 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
192 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
196 << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", " in executeMatchTable()
471 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
482 << ", OpIdx=" << OpIdx << ")\n"); in executeMatchTable()
485 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
520 int64_t OpIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/RISCV/
DRISCVGenGlobalISel.inc354 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
362 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
363 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
371 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
379 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
380 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
413 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
421 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
422 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs1
738 GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // rs1
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc868 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
869 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
880 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
881 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
888 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
895 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
896 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
925 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
926 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
938 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DBreakFalseDeps.cpp81 bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
86 bool shouldBreakDependence(MachineInstr *, unsigned OpIdx, unsigned Pref);
107 bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx, in pickBestRegisterForUndef() argument
109 MachineOperand &MO = MI->getOperand(OpIdx); in pickBestRegisterForUndef()
126 TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF); in pickBestRegisterForUndef()
163 bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, in shouldBreakDependence() argument
165 Register reg = MI->getOperand(OpIdx).getReg(); in shouldBreakDependence()
230 unsigned OpIdx = UndefReads.back().second; in processUndefReads() local
237 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg())) in processUndefReads()
238 TII->breakPartialRegDependency(*UndefMI, OpIdx, TRI); in processUndefReads()
[all …]
DMachineInstr.cpp783 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, in findInlineAsmFlagIdx() argument
786 assert(OpIdx < getNumOperands() && "OpIdx out of range"); in findInlineAsmFlagIdx()
789 if (OpIdx < InlineAsm::MIOp_FirstOperand) in findInlineAsmFlagIdx()
801 if (i + NumOps > OpIdx) { in findInlineAsmFlagIdx()
831 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() argument
840 return TII->getRegClass(getDesc(), OpIdx, TRI, MF); in getRegClassConstraint()
842 if (!getOperand(OpIdx).isReg()) in getRegClassConstraint()
847 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
848 OpIdx = DefIdx; in getRegClassConstraint()
851 int FlagIdx = findInlineAsmFlagIdx(OpIdx); in getRegClassConstraint()
[all …]
/external/llvm/utils/TableGen/
DCodeEmitterGen.cpp86 unsigned OpIdx; in AddCodeToMergeInOperand() local
87 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { in AddCodeToMergeInOperand()
89 OpIdx = CGI.Operands[OpIdx].MIOperandNo; in AddCodeToMergeInOperand()
90 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && in AddCodeToMergeInOperand()
113 OpIdx = NumberedOp++; in AddCodeToMergeInOperand()
116 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx); in AddCodeToMergeInOperand()
127 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); in AddCodeToMergeInOperand()
133 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; in AddCodeToMergeInOperand()
192 unsigned OpIdx; in getInstructionCase() local
193 if (!CGI.Operands.hasOperandNamed(Vals[i].getName(), OpIdx)) in getInstructionCase()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64AddressTypePromotion.cpp208 static bool shouldSExtOperand(const Instruction *Inst, int OpIdx) { in shouldSExtOperand() argument
209 return !(isa<SelectInst>(Inst) && OpIdx == 0); in shouldSExtOperand()
311 for (int OpIdx = 0, EndOpIdx = Inst->getNumOperands(); OpIdx != EndOpIdx; in propagateSignExtension() local
312 ++OpIdx) { in propagateSignExtension()
313 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n'); in propagateSignExtension()
314 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() || in propagateSignExtension()
315 !shouldSExtOperand(Inst, OpIdx)) { in propagateSignExtension()
320 Value *Opnd = Inst->getOperand(OpIdx); in propagateSignExtension()
323 Inst->setOperand(OpIdx, ConstantInt::getSigned(SExt->getType(), in propagateSignExtension()
330 Inst->setOperand(OpIdx, UndefValue::get(SExt->getType())); in propagateSignExtension()
[all …]
DAArch64PromoteConstant.cpp251 unsigned OpIdx) { in shouldConvertUse() argument
254 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2) in shouldConvertUse()
258 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
262 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
265 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
269 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
273 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
277 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp403 unsigned OpIdx = 0; in ExpandVLD() local
405 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
406 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
422 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
425 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
432 SrcOpIdx = OpIdx++; in ExpandVLD()
435 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
436 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp481 unsigned OpIdx = 0; in ExpandVLD() local
483 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
484 Register DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
512 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
515 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
516 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
527 const MachineOperand &AM6Offset = MI.getOperand(OpIdx++); in ExpandVLD()
554 SrcOpIdx = OpIdx++; in ExpandVLD()
558 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
559 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64StackTaggingPreRA.cpp179 unsigned OpIdx = TII->getLoadStoreImmIdx(UseI->getOpcode()) - 1; in uncheckUsesOf() local
180 if (UseI->getOperand(OpIdx).isReg() && in uncheckUsesOf()
181 UseI->getOperand(OpIdx).getReg() == TaggedReg) { in uncheckUsesOf()
182 UseI->getOperand(OpIdx).ChangeToFrameIndex(FI); in uncheckUsesOf()
183 UseI->getOperand(OpIdx).setTargetFlags(AArch64II::MO_TAGGED); in uncheckUsesOf()
/external/llvm/include/llvm/CodeGen/GlobalISel/
DRegisterBankInfo.h168 void setOperandMapping(unsigned OpIdx, unsigned MaskSize,
217 getVRegsMem(unsigned OpIdx);
252 void createVRegs(unsigned OpIdx);
264 void setVRegs(unsigned OpIdx, unsigned PartialMapIdx, unsigned NewVReg);
279 getVRegs(unsigned OpIdx, bool ForDebug = false) const;
411 getRegBankFromConstraints(const MachineInstr &MI, unsigned OpIdx,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MC/
DMCInstPrinter.cpp63 const MCRegisterInfo &MRI, unsigned &OpIdx, in matchAliasCondition() argument
73 const MCOperand &Opnd = MI.getOperand(OpIdx); in matchAliasCondition()
74 ++OpIdx; in matchAliasCondition()
127 unsigned OpIdx = 0; in matchAliasPatterns() local
129 return matchAliasCondition(*MI, STI, MRI, OpIdx, M, C); in matchAliasPatterns()

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