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Searched refs:RR (Results 1 – 25 of 309) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DRDFRegisters.cpp97 RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const { in normalize()
98 return RR; in normalize()
162 bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const { in aliasRM() argument
163 assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg)); in aliasRM()
165 bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32)); in aliasRM()
169 if (RR.Mask == LaneBitmask::getAll()) in aliasRM()
171 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
172 if (RC != nullptr && (RR.Mask & RC->LaneMask) == RC->LaneMask) in aliasRM()
180 LaneBitmask M = RR.Mask; in aliasRM()
181 for (MCSubRegIndexIterator SI(RR.Reg, &TRI); SI.isValid(); ++SI) { in aliasRM()
[all …]
DRDFRegisters.h83 bool operator== (const RegisterRef &RR) const {
84 return Reg == RR.Reg && Mask == RR.Mask;
87 bool operator!= (const RegisterRef &RR) const {
88 return !operator==(RR);
91 bool operator< (const RegisterRef &RR) const {
92 return Reg < RR.Reg || (Reg == RR.Reg && Mask < RR.Mask);
113 RegisterRef normalize(RegisterRef RR) const;
131 RegisterRef mapTo(RegisterRef RR, unsigned R) const;
153 bool aliasRM(RegisterRef RR, RegisterRef RM) const;
163 bool hasAliasOf(RegisterRef RR) const;
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DHexagonExpandCondsets.cpp182 bool operator== (RegisterRef RR) const { in operator ==()
183 return Reg == RR.Reg && Sub == RR.Sub; in operator ==()
185 bool operator!= (RegisterRef RR) const { return !operator==(RR); } in operator !=()
186 bool operator< (RegisterRef RR) const { in operator <()
187 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); in operator <()
201 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
235 bool isIntReg(RegisterRef RR, unsigned &BW);
294 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, in addRefToMap() argument
296 unsigned Mask = getMaskForSub(RR.Sub) | Exec; in addRefToMap()
297 ReferenceMap::iterator F = Map.find(RR.Reg); in addRefToMap()
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DRDFGraph.cpp418 void RefNode::setRegRef(RegisterRef RR, DataFlowGraph &G) { in setRegRef() argument
421 Ref.PR = G.pack(RR); in setRegRef()
814 RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) { in newPhiUse() argument
817 PUA.Addr->setRegRef(RR, *this); in newPhiUse()
830 RegisterRef RR, uint16_t Flags) { in newDef() argument
833 DA.Addr->setRegRef(RR, *this); in newDef()
907 RegisterRef RR = *I; in build() local
910 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags); in build()
932 for (RegisterRef RR : EHRegs) { in build() local
936 NodeAddr<DefNode*> DA = newDef(PA, RR, PhiFlags); in build()
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DBitTracker.cpp329 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth()
338 if (Register::isVirtualRegister(RR.Reg)) { in getRegBitWidth()
339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub); in getRegBitWidth()
342 assert(Register::isPhysicalRegister(RR.Reg)); in getRegBitWidth()
344 (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub); in getRegBitWidth()
348 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR, in getCell() argument
350 uint16_t BW = getRegBitWidth(RR); in getCell()
354 if (Register::isPhysicalRegister(RR.Reg)) in getCell()
357 assert(Register::isVirtualRegister(RR.Reg)); in getCell()
360 const TargetRegisterClass *C = MRI.getRegClass(RR.Reg); in getCell()
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DRDFCopy.cpp121 auto MinPhysReg = [this] (RegisterRef RR) -> unsigned { in run() argument
123 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); in run()
124 if ((RC.LaneMask & RR.Mask) == RC.LaneMask) in run()
125 return RR.Reg; in run()
126 for (MCSubRegIndexIterator S(RR.Reg, &TRI); S.isValid(); ++S) in run()
127 if (RR.Mask == TRI.getSubRegIndexLaneMask(S.getSubRegIndex())) in run()
/external/mesa3d/src/gallium/auxiliary/gallivm/
Df.cpp62 boost::math::ntl::RR exp2(const boost::math::ntl::RR& x) in exp2()
67 boost::math::ntl::RR log2(const boost::math::ntl::RR& x) in log2()
72 boost::math::ntl::RR f(const boost::math::ntl::RR& x, int variant) in f()
88 const boost::math::tools::polynomial<boost::math::ntl::RR>& n, in show_extra()
89 const boost::math::tools::polynomial<boost::math::ntl::RR>& d, in show_extra()
90 const boost::math::ntl::RR& x_offset, in show_extra()
91 const boost::math::ntl::RR& y_offset, in show_extra()
/external/llvm/lib/Target/Hexagon/
DHexagonRDF.cpp37 bool HexagonRegisterAliasInfo::covers(const RegisterSet &RRs, RegisterRef RR) in covers()
39 if (RRs.count(RR)) in covers()
42 if (!TargetRegisterInfo::isPhysicalRegister(RR.Reg)) { in covers()
43 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg)); in covers()
45 bool HasLo = RRs.count({RR.Reg, Hexagon::subreg_loreg}); in covers()
46 bool HasHi = RRs.count({RR.Reg, Hexagon::subreg_hireg}); in covers()
51 if (RR.Sub == 0) { in covers()
53 unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg); in covers()
54 unsigned Hi = TRI.getSubReg(RR.Reg, Hexagon::subreg_hireg); in covers()
59 return RegisterAliasInfo::covers(RRs, RR); in covers()
DRDFGraph.cpp382 return Ref.RR; in getRegRef()
389 void RefNode::setRegRef(RegisterRef RR) { in setRegRef() argument
392 Ref.RR = RR; in setRegRef()
593 bool RegisterAliasInfo::covers(const RegisterSet &RRs, RegisterRef RR) const { in covers()
594 if (RRs.count(RR)) in covers()
601 if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) { in covers()
602 if (RR.Sub != 0) in covers()
603 return RRs.count({RR.Reg, 0}); in covers()
608 unsigned Reg = RR.Sub == 0 ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub); in covers()
617 std::vector<RegisterRef> RegisterAliasInfo::getAliasSet(RegisterRef RR) const { in getAliasSet()
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DHexagonExpandCondsets.cpp219 bool operator== (RegisterRef RR) const { in operator ==()
220 return Reg == RR.Reg && Sub == RR.Sub; in operator ==()
222 bool operator!= (RegisterRef RR) const { return !operator==(RR); } in operator !=()
223 bool operator< (RegisterRef RR) const { in operator <()
224 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); in operator <()
236 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
272 bool isIntReg(RegisterRef RR, unsigned &BW);
323 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, in addRefToMap() argument
325 unsigned Mask = getMaskForSub(RR.Sub) | Exec; in addRefToMap()
326 ReferenceMap::iterator F = Map.find(RR.Reg); in addRefToMap()
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DRDFGraph.h374 RegisterRef(const RegisterRef &RR) = default;
375 RegisterRef &operator= (const RegisterRef &RR) = default;
376 bool operator== (const RegisterRef &RR) const {
377 return Reg == RR.Reg && Sub == RR.Sub;
379 bool operator!= (const RegisterRef &RR) const {
380 return !operator==(RR);
382 bool operator< (const RegisterRef &RR) const {
383 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
392 virtual std::vector<RegisterRef> getAliasSet(RegisterRef RR) const;
395 virtual bool covers(const RegisterSet &RRs, RegisterRef RR) const;
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DBitTracker.cpp314 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth()
324 if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) { in getRegBitWidth()
325 const TargetRegisterClass *VC = MRI.getRegClass(RR.Reg); in getRegBitWidth()
329 assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg)); in getRegBitWidth()
330 PhysR = RR.Reg; in getRegBitWidth()
333 unsigned PhysS = (RR.Sub == 0) ? PhysR : TRI.getSubReg(PhysR, RR.Sub); in getRegBitWidth()
340 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR, in getCell() argument
342 uint16_t BW = getRegBitWidth(RR); in getCell()
346 if (TargetRegisterInfo::isPhysicalRegister(RR.Reg)) in getCell()
349 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg)); in getCell()
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DRDFLiveness.cpp111 RegisterRef RR = TA.Addr->getRegRef(); in getAllReachingDefs() local
112 if (RAI.covers(RR, RefRR)) { in getAllReachingDefs()
515 RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef(); in computePhiInfo() local
516 dbgs() << '<' << Print<RegisterRef>(RR, DFG) << '>'; in computePhiInfo()
604 RegisterRef RR = R.first; in computeLiveIns() local
605 if (!isRestricted(PA, UA, RR)) in computeLiveIns()
606 RR = getRestrictedRegRef(UA); in computeLiveIns()
610 if (!RAI.alias(R.first, RR)) in computeLiveIns()
612 for (auto D : getAllReachingDefs(RR, UA)) in computeLiveIns()
613 LOX[RR].insert(D.Id); in computeLiveIns()
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/external/rust/crates/ring/src/arithmetic/
Dmontgomery.rs28 pub enum RR {} enum
37 impl Encoding for RR {} implementation
47 impl ReductionEncoding for RR { implementation
83 impl ProductEncoding for (RR, Unencoded) {
84 type Output = <(Unencoded, RR) as ProductEncoding>::Output;
86 impl ProductEncoding for (RR, RInverse) {
87 type Output = <(RInverse, RR) as ProductEncoding>::Output;
/external/mdnsresponder/mDNSCore/
DDNSCommon.h172 #define GetRRDomainNameTarget(RR) ( … argument
173 …((RR)->rrtype == kDNSType_NS || (RR)->rrtype == kDNSType_CNAME || (RR)->rrtype == kDNSType_PTR || …
174 …((RR)->rrtype == kDNSType_MX || (RR)->rrtype == kDNSType_AFSDB || (RR)->rrtype == kDNSType_RT || …
175 …((RR)->rrtype == kDNSType_SRV ) ? &(RR)->rdata->u.srv.target : mD…
203 #define PutResourceRecord(MSG, P, C, RR) PutResourceRecordTTL((MSG), (P), (C), (RR), (RR)->rrorigin… argument
210 #define PutRR_OS(P, C, RR) PutRR_OS_TTL((P), (C), (RR), (RR)->rroriginalttl) argument
265 #pragma mark - RR List Management & Task Management
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/HardwareUnits/
DResourceManager.cpp194 void ResourceManager::use(const ResourceRef &RR) { in use() argument
196 unsigned RSID = getResourceStateIndex(RR.first); in use()
198 RS.markSubResourceAsUsed(RR.second); in use()
202 Strategies[RSID]->used(RR.second); in use()
209 AvailableProcResUnits ^= RR.first; in use()
217 CurrentUser.markSubResourceAsUsed(RR.first); in use()
218 Strategies[GroupIndex]->used(RR.first); in use()
224 void ResourceManager::release(const ResourceRef &RR) { in release() argument
225 unsigned RSID = getResourceStateIndex(RR.first); in release()
228 RS.releaseSubResource(RR.second); in release()
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/external/vboot_reference/host/lib/
Dutil_misc.c39 BIGNUM *N0inv = NULL, *R = NULL, *RR = NULL; in vb_keyb_from_rsa() local
70 NEW_BIGNUM(RR); in vb_keyb_from_rsa()
98 BN_copy(RR, R); in vb_keyb_from_rsa()
99 BN_mul(RRTemp, RR, R, bn_ctx); in vb_keyb_from_rsa()
100 BN_mod(RR, RRTemp, N, bn_ctx); in vb_keyb_from_rsa()
118 BN_mod(rr, RR, B, bn_ctx); /* rr = RR mod B */ in vb_keyb_from_rsa()
122 BN_rshift(RR, RR, 32); /* RR = RR/B */ in vb_keyb_from_rsa()
/external/boringssl/src/crypto/fipsmodule/bn/
Dmontgomery.c132 BN_init(&ret->RR); in BN_MONT_CTX_new()
143 BN_free(&mont->RR); in BN_MONT_CTX_free()
153 if (!BN_copy(&to->RR, &from->RR) || in BN_MONT_CTX_copy()
230 BN_zero(&mont->RR); in BN_MONT_CTX_set()
231 int ok = BN_set_bit(&mont->RR, lgBigR * 2) && in BN_MONT_CTX_set()
232 BN_mod(&mont->RR, &mont->RR, &mont->N, ctx) && in BN_MONT_CTX_set()
233 bn_resize_words(&mont->RR, mont->N.width); in BN_MONT_CTX_set()
255 if (!bn_mod_exp_base_2_consttime(&mont->RR, lgBigR * 2, &mont->N, ctx) || in BN_MONT_CTX_new_consttime()
256 !bn_resize_words(&mont->RR, mont->N.width)) { in BN_MONT_CTX_new_consttime()
287 return BN_mod_mul_montgomery(ret, a, &mont->RR, mont, ctx); in BN_to_montgomery()
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/external/rust/crates/quiche/deps/boringssl/src/crypto/fipsmodule/bn/
Dmontgomery.c133 BN_init(&ret->RR); in BN_MONT_CTX_new()
144 BN_free(&mont->RR); in BN_MONT_CTX_free()
154 if (!BN_copy(&to->RR, &from->RR) || in BN_MONT_CTX_copy()
228 BN_zero(&mont->RR); in BN_MONT_CTX_set()
229 int ok = BN_set_bit(&mont->RR, lgBigR * 2) && in BN_MONT_CTX_set()
230 BN_mod(&mont->RR, &mont->RR, &mont->N, ctx) && in BN_MONT_CTX_set()
231 bn_resize_words(&mont->RR, mont->N.width); in BN_MONT_CTX_set()
253 if (!bn_mod_exp_base_2_consttime(&mont->RR, lgBigR * 2, &mont->N, ctx) || in BN_MONT_CTX_new_consttime()
254 !bn_resize_words(&mont->RR, mont->N.width)) { in BN_MONT_CTX_new_consttime()
285 return BN_mod_mul_montgomery(ret, a, &mont->RR, mont, ctx); in BN_to_montgomery()
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/external/cronet/third_party/boringssl/src/crypto/fipsmodule/bn/
Dmontgomery.c132 BN_init(&ret->RR); in BN_MONT_CTX_new()
143 BN_free(&mont->RR); in BN_MONT_CTX_free()
153 if (!BN_copy(&to->RR, &from->RR) || in BN_MONT_CTX_copy()
230 BN_zero(&mont->RR); in BN_MONT_CTX_set()
231 int ok = BN_set_bit(&mont->RR, lgBigR * 2) && in BN_MONT_CTX_set()
232 BN_mod(&mont->RR, &mont->RR, &mont->N, ctx) && in BN_MONT_CTX_set()
233 bn_resize_words(&mont->RR, mont->N.width); in BN_MONT_CTX_set()
255 if (!bn_mod_exp_base_2_consttime(&mont->RR, lgBigR * 2, &mont->N, ctx) || in BN_MONT_CTX_new_consttime()
256 !bn_resize_words(&mont->RR, mont->N.width)) { in BN_MONT_CTX_new_consttime()
287 return BN_mod_mul_montgomery(ret, a, &mont->RR, mont, ctx); in BN_to_montgomery()
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/external/vboot_reference/utility/
DdumpRSAPublicKey.c46 BIGNUM *N0inv= NULL, *R = NULL, *RR = NULL, *RRTemp = NULL, *NnumBits = NULL; in output() local
65 RR = BN_new(); in output()
92 BN_copy(RR, R); in output()
93 BN_mul(RRTemp, RR, R, bn_ctx); in output()
94 BN_mod(RR, RRTemp, N, bn_ctx); in output()
113 BN_mod(rr, RR, B, bn_ctx); /* rr = RR mod B */ in output()
118 BN_rshift(RR, RR, 32); /* RR = RR/B */ in output()
/external/clang/test/PCH/
Dcxx-reference.h4 typedef char (&&RR);
12 RR &lrrr = c;
13 RR &&rrrr = 'c';
/external/mbedtls/library/
Dbignum_mod.c107 mbedtls_mpi RR; in set_mont_const_square() local
111 mbedtls_mpi_init( &RR ); in set_mont_const_square()
121 ret = mbedtls_mpi_core_get_mont_r2_unsafe(&RR, &N); in set_mont_const_square()
125 *X = RR.p; in set_mont_const_square()
126 RR.p = NULL; in set_mont_const_square()
131 mbedtls_mpi_free(&RR); in set_mont_const_square()
/external/clang/lib/StaticAnalyzer/Checkers/
DPointerSubChecker.cpp48 const MemRegion *RR = RV.getAsRegion(); in checkPreStmt() local
50 if (!(LR && RR)) in checkPreStmt()
54 const MemRegion *BaseRR = RR->getBaseRegion(); in checkPreStmt()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/Stages/
DExecuteStage.cpp103 for (const ResourceRef &RR : Freed) in cycleStart() local
104 notifyResourceAvailable(RR); in cycleStart()
245 void ExecuteStage::notifyResourceAvailable(const ResourceRef &RR) const { in notifyResourceAvailable()
246 LLVM_DEBUG(dbgs() << "[E] Resource Available: [" << RR.first << '.' in notifyResourceAvailable()
247 << RR.second << "]\n"); in notifyResourceAvailable()
249 Listener->onResourceAvailable(RR); in notifyResourceAvailable()

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