| /external/llvm/test/CodeGen/AArch64/ |
| D | divrem.ll | 3 ; SDIVREM/UDIVREM DAG nodes are generated but expanded when lowering and
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 204 SDIVREM, UDIVREM, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 211 SDIVREM, UDIVREM, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 156 setOperationAction(ISD::SDIVREM, VT, Custom); in AVRTargetLowering()
341 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
343 bool IsSigned = (Opcode == ISD::SDIVREM); in LowerDivRem()
705 case ISD::SDIVREM: in LowerOperation()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.h | 93 SDIVREM, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 186 case ISD::SDIVREM: return "sdivrem"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 269 case ISD::SDIVREM: in LegalizeOp()
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| D | LegalizeIntegerTypes.cpp | 2302 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SDIV()
2303 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SDIV()
2487 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SREM()
2488 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SREM()
|
| D | LegalizeDAG.cpp | 2093 bool isSigned = Opcode == ISD::SDIVREM; in ExpandDivRemLibCall()
3235 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3254 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3966 case ISD::SDIVREM: in ConvertNodeToLibcall()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 150 setOperationAction(ISD::SDIVREM, MVT::i8, Expand); in MSP430TargetLowering()
156 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 98 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 80 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
136 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
213 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
|
| D | MipsISelLowering.cpp | 421 setTargetDAGCombine(ISD::SDIVREM); in MipsTargetLowering()
475 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : in performDivRemCombine()
845 case ISD::SDIVREM: in PerformDAGCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 198 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
205 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
238 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
285 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
459 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 236 case ISD::SDIVREM: return "sdivrem"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 3288 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SDIV()
3289 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SDIV()
3479 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SREM()
3480 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SREM()
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| D | LegalizeDAG.cpp | 2182 bool isSigned = Opcode == ISD::SDIVREM; in ExpandDivRemLibCall()
3280 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
3299 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
4172 case ISD::SDIVREM: in ConvertNodeToLibcall()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 86 setOperationAction(ISD::SDIVREM, VT, Expand); in BPFTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 137 setOperationAction(ISD::SDIVREM, MVT::i8, Promote); in MSP430TargetLowering()
143 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 300 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
385 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
711 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
1551 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 817 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in ARMTargetLowering()
819 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in ARMTargetLowering()
822 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in ARMTargetLowering()
7218 case ISD::SDIVREM: in LowerOperation()
7253 case ISD::SDIVREM: in ReplaceNodeResults()
12009 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemLibcall()
12012 bool isSigned = N->getOpcode() == ISD::SDIVREM || in getDivRemLibcall()
12027 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemArgList()
12030 bool isSigned = N->getOpcode() == ISD::SDIVREM || in getDivRemArgList()
12051 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 981 case ISD::SDIVREM: in isHardwareLoopProfitable()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2314 case ISD::SDIVREM: in Select()
2321 bool isSigned = (Opcode == ISD::SDIVREM || in Select()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 314 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
384 setOperationAction(ISD::SDIVREM, VT, Custom); in AMDGPUTargetLowering()
1134 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
1987 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
|