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Searched refs:SETUGT (Results 1 – 25 of 87) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h862 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
890 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h1059 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
1087 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/external/llvm/lib/CodeGen/
DAnalysis.cpp174 case FCmpInst::FCMP_UGT: return ISD::SETUGT; in getFCmpCondCode()
190 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
210 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAnalysis.cpp213 case FCmpInst::FCMP_UGT: return ISD::SETUGT; in getFCmpCondCode()
229 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
249 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp238 case ISD::SETUGT: in softenSetCCOperands()
1412 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1577 case ISD::SETUGT: in SimplifySetCC()
1600 case ISD::SETUGT: in SimplifySetCC()
1752 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
1782 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) in SimplifySetCC()
1788 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) in SimplifySetCC()
1800 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) in SimplifySetCC()
1809 if (Cond == ISD::SETUGT && in SimplifySetCC()
1877 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp971 case ISD::SETUGT: in PromoteSetCCOperands()
1683 return std::make_pair(ISD::SETUGT, ISD::UMAX); in getExpandedMinMaxOps()
2536 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2836 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
2876 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
2903 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
DSelectionDAGDumper.cpp341 case ISD::SETUGT: return "setugt"; in getOperationName()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td52 defm GT_U : ComparisonInt<SETUGT, "gt_u">;
DWebAssemblyISelLowering.cpp78 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonSelectCCInfo.td30 IntRegs:$fval, SETUGT)),
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp3056 case ISD::SETUGT: in get32BitZExtCompare()
3229 case ISD::SETUGT: in get32BitSExtCompare()
3385 case ISD::SETUGT: in get64BitZExtCompare()
3548 case ISD::SETUGT: in get64BitSExtCompare()
3810 case ISD::SETUGT: in SelectCC()
3837 case ISD::SETUGT: in SelectCC()
3886 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
3918 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
3938 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
3982 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; in getVCmpInst()
[all …]
DPPCInstrQPX.td1004 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGT),
1051 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGT),
1130 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGT)),
1151 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGT)),
1172 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGT)),
DPPCInstrInfo.td3440 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3447 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3631 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3659 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3671 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3699 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3954 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3978 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3999 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
4021 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp381 case ISD::SETUGT: in softenSetCCOperands()
2945 } else if (Cond == ISD::CondCode::SETUGT) { in optimizeSetCCOfSignedTruncationCheck()
3189 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
3370 case ISD::SETUGT: in SimplifySetCC()
3395 case ISD::SETUGT: in SimplifySetCC()
3579 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
3629 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { in SimplifySetCC()
3660 if (Cond == ISD::SETUGT && in SimplifySetCC()
3734 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
3735 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp1380 case ISD::SETUGT: in PromoteSetCCOperands()
2211 return std::make_pair(ISD::SETUGT, ISD::UMAX); in getExpandedMinMaxOps()
2444 Cond = ISD::SETUGT; in ExpandIntRes_UADDSUBO()
3187 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT); in ExpandIntRes_MULFIX()
3848 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
3916 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
DSelectionDAGDumper.cpp418 case ISD::SETUGT: return "setugt"; in getOperationName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td79 defm GT_U : ComparisonInt<SETUGT, "gt_u", 0x4b, 0x56>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInsertSkips.cpp228 case ISD::SETUGT: in kill()
/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td1007 def : Pat<(setcc v4f64:$FRA, v4f64:$FRB, SETUGT),
1054 def : Pat<(setcc v4f32:$FRA, v4f32:$FRB, SETUGT),
1133 def : Pat<(v4f64 (selectcc i1:$lhs, i1:$rhs, v4f64:$tval, v4f64:$fval, SETUGT)),
1154 def : Pat<(v4f32 (selectcc i1:$lhs, i1:$rhs, v4f32:$tval, v4f32:$fval, SETUGT)),
1175 def : Pat<(v4i1 (selectcc i1:$lhs, i1:$rhs, v4i1:$tval, v4i1:$fval, SETUGT)),
DPPCISelDAGToDAG.cpp2113 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
2145 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
2165 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
2209 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; in getVCmpInst()
2217 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break; in getVCmpInst()
2243 case ISD::SETUGT: in getVCmpInst()
DPPCInstrInfo.td3006 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3013 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3157 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3202 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3225 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3270 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
3382 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
3406 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
3427 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
3448 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td93 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
113 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp542 case ISD::SETUGT: in EmitInstrWithCustomInserter()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in MipsSETargetLowering()
199 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering()
290 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAIntType()
326 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAFloatType()
965 case ISD::SETUGT: in isLegalDSPCondCode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp266 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in MipsSETargetLowering()
271 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering()
367 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAIntType()
403 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAFloatType()
962 case ISD::SETUGT: in isLegalDSPCondCode()

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