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Searched refs:SGRF_SOC_CON (Results 1 – 15 of 15) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/secure/
Dsecure.c21 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
25 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(21), in sgrf_ddr_rgn_global_bypass()
66 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
70 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2) + 1), in sgrf_ddr_rgn_config()
74 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
78 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6 + (rgn * 2)), in sgrf_ddr_rgn_config()
84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_GATE); in secure_watchdog_gate()
89 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_PCLK_WDT_UNGATE); in secure_watchdog_ungate()
132 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), SGRF_SOC_CON2_MST_NS); in secure_sgrf_init()
133 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_SOC_CON3_MST_NS); in secure_sgrf_init()
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Dsecure.h30 #define SGRF_SOC_CON(n) ((((n) < 6) ? 0x0 : 0x38) + (n) * 4) macro
/external/arm-trusted-firmware/plat/rockchip/px30/drivers/secure/
Dsecure.c84 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_SLV_S_ALL_NS); in sgrf_init()
85 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SLV_S_ALL_NS); in sgrf_init()
86 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SLV_S_ALL_NS); in sgrf_init()
87 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SLV_S_ALL_NS); in sgrf_init()
88 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(8), 0x00030000); in sgrf_init()
91 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), 0x000f0003); in sgrf_init()
100 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_REQ); in sgrf_init()
102 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), DMA_SOFTRST_RLS); in sgrf_init()
Dsecure.h13 #define SGRF_SOC_CON(i) ((i) * 0x4) macro
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/secure/
Dsecure.c92 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_gate()
104 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), in secure_watchdog_ungate()
138 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), in secure_sgrf_init()
140 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), in secure_sgrf_init()
142 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), in secure_sgrf_init()
Dsecure.h16 #define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\ macro
/external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/
Dpmu.c232 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in pmu_set_sleep_mode()
235 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), in pmu_set_sleep_mode()
314 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), in rockchip_soc_cores_pwr_dm_on()
321 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), in rockchip_soc_cores_pwr_dm_on()
335 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in rockchip_soc_sys_pwr_dm_resume()
338 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), in rockchip_soc_sys_pwr_dm_resume()
/external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/
Dsoc.c135 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), 0xf0000000); in sgrf_init()
136 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(3), SGRF_MST_S_ALL_NS); in sgrf_init()
137 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(4), SGRF_MST_S_ALL_NS); in sgrf_init()
Dsoc.h79 #define SGRF_SOC_CON(n) (0x000 + (n) * 4) macro
/external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/
Dsoc.c80 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS); in sgrf_init()
81 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS); in sgrf_init()
82 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS); in sgrf_init()
Dsoc.h40 #define SGRF_SOC_CON(n) (0x0 + (n) * 4) macro
/external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/pmu/
Dpmu.c322 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), in rockchip_soc_sys_pwr_dm_resume()
341 store_sgrf_soc_con0 = mmio_read_32(SGRF_BASE + SGRF_SOC_CON(0)); in rockchip_soc_sys_pwr_dm_suspend()
364 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(0), SGRF_FAST_BOOT_ENA); in rockchip_soc_sys_pwr_dm_suspend()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dm0_ctl.c24 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), WMSK_BIT(12)); in m0_init()
Dpmu.c1378 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in rockchip_soc_sys_pwr_dm_suspend()
1459 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in rockchip_soc_sys_pwr_dm_resume()
1609 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in plat_rockchip_pmu_init()
/external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/pmu/
Dpmu.c602 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in sram_suspend()
659 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), in plat_rockchip_pmu_init()