Home
last modified time | relevance | path

Searched refs:SLTI (Results 1 – 12 of 12) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/RISCV/
DRISCVGenMCCodeEmitter.inc504 UINT64_C(8211), // SLTI
775 case RISCV::SLTI:
1982 CEFBS_None, // SLTI = 491
DRISCVGenAsmWriter.inc769 4669U, // SLTI
1283 32U, // SLTI
DRISCVGenAsmMatcher.inc2352 …{ 2441 /* slt */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR,…
2353 …{ 2445 /* slti */, RISCV::SLTI, Convert__Reg1_0__Reg1_1__SImm121_2, AMFBS_None, { MCK_GPR, MCK_GPR…
DRISCVGenInstrInfo.inc506 SLTI = 491,
1223 { 491, 3, 1, 4, 2, 0, 0x3ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #491 = SLTI
DRISCVGenDisassemblerTables.inc288 /* 215 */ MCD::OPC_Decode, 235, 3, 31, // Opcode: SLTI
DRISCVGenGlobalISel.inc10148 …imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *…
10149 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
10168 …imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i32] } GPR:{ *…
10169 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
10742 …imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12, SETLT:{ *:[Other] }) => (SLTI:{ *:[i64] } GPR:{ *…
10743 GIR_BuildMI, /*InsnID*/0, /*Opcode*/RISCV::SLTI,
DRISCVGenDAGISel.inc6731 /* 12411*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTI), 0,
6734 … // Dst: (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
6737 /* 12422*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTI), 0,
6740 … // Dst: (SLTI:{ *:[i32] } GPR:{ *:[i32] }:$rs1, (imm:{ *:[i32] })<<P:Predicate_simm12>>:$imm12)
7025 /* 13033*/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTI), 0,
7028 … // Dst: (SLTI:{ *:[i64] } GPR:{ *:[i64] }:$rs1, (imm:{ *:[i64] })<<P:Predicate_simm12>>:$imm12)
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td412 def SLTI : ALU_ri<0b010, "slti">;
737 (SLTI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
840 def : PatGprSimm12<setlt, SLTI>;
/external/llvm/lib/Target/Mips/
DMips16InstrInfo.td1158 // Format: SLTI rx, immediate MIPS16e
1168 // Format: SLTI rx, immediate MIPS16e
1189 // Format: SLTI rx, immediate MIPS16e
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMips16InstrInfo.td1161 // Format: SLTI rx, immediate MIPS16e
1171 // Format: SLTI rx, immediate MIPS16e
1192 // Format: SLTI rx, immediate MIPS16e
/external/pcre/src/sljit/
DsljitNativeMIPS_common.c266 #define SLTI (HI(10)) macro
1705 FAIL_IF(push_inst(compiler, SLTI | S(src1) | TA(OTHER_FLAG) | IMM(src2), OTHER_FLAG)); in emit_single_op()
3101 …PTR_FAIL_IF(push_inst(compiler, (type <= SLJIT_LESS_EQUAL ? SLTIU : SLTI) | S(src1) | T(TMP_REG1) … in sljit_emit_cmp()
3111 …PTR_FAIL_IF(push_inst(compiler, (type <= SLJIT_LESS_EQUAL ? SLTIU : SLTI) | S(src2) | T(TMP_REG1) … in sljit_emit_cmp()
DsljitNativeRISCV_common.c126 #define SLTI (F3(0x2) | OPC(0x13)) macro
1288 FAIL_IF(push_inst(compiler, SLTI | RD(OTHER_FLAG) | RS1(src1) | IMM_I(src2))); in emit_single_op()