SLTU (reference) in projects: external - OpenGrok search results

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Searched refs:SLTU (Results 1 – 12 of 12) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
D	RISCVInstrInfo.td	430 def SLTU : ALU_rr<0b0000000, 0b011, "sltu">, Sched<[WriteIALU, ReadIALU, ReadIALU]>; 600 def : InstAlias<"snez $rd, $rs", (SLTU GPR:$rd, X0, GPR:$rs)>; 607 def : InstAlias<"sgtu $rd, $rs, $rt", (SLTU GPR:$rd, GPR:$rt, GPR:$rs), 0>; 841 def : PatGprGpr<setult, SLTU>; 850 def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>; 851 def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>; 853 (SLTU X0, (XORI GPR:$rs1, simm12:$imm12))>; 854 def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>; 855 def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>; 856 def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
/external/pcre/src/sljit/
D	sljitNativeRISCV_common.c	127 #define SLTU (F7(0x0) \| F3(0x3) \| OPC(0x33)) macro 1223 FAIL_IF(push_inst(compiler, SLTU \| RD(OTHER_FLAG) \| RS1(dst) \| RS2(carry_src_r))); in emit_single_op() 1260 FAIL_IF(push_inst(compiler, SLTU \| RD(EQUAL_FLAG) \| RS1(dst) \| RS2(carry_src_r))); in emit_single_op() 1269 FAIL_IF(push_inst(compiler, SLTU \| RD(OTHER_FLAG) \| RS1(dst) \| RS2(OTHER_FLAG))); in emit_single_op() 1305 FAIL_IF(push_inst(compiler, SLTU \| RD(OTHER_FLAG) \| RS1(src1) \| RS2(src2))); in emit_single_op() 1309 FAIL_IF(push_inst(compiler, SLTU \| RD(OTHER_FLAG) \| RS1(src2) \| RS2(src1))); in emit_single_op() 1365 FAIL_IF(push_inst(compiler, SLTU \| RD(OTHER_FLAG) \| RS1(src1) \| RS2(src2))); in emit_single_op() 1398 FAIL_IF(push_inst(compiler, SLTU \| RD(EQUAL_FLAG) \| RS1(src1) \| RS2(src2))); in emit_single_op() 1404 FAIL_IF(push_inst(compiler, SLTU \| RD(TMP_REG1) \| RS1(dst) \| RS2(OTHER_FLAG))); in emit_single_op()
D	sljitNativeMIPS_common.c	268 #define SLTU (HI(0) \| LO(43)) macro 1640 FAIL_IF(push_inst(compiler, SLTU \| S(dst) \| TA(carry_src_ar) \| DA(OTHER_FLAG), OTHER_FLAG)); in emit_single_op() 1677 FAIL_IF(push_inst(compiler, SLTU \| S(dst) \| TA(carry_src_ar) \| DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op() 1686 FAIL_IF(push_inst(compiler, SLTU \| S(dst) \| TA(OTHER_FLAG) \| DA(OTHER_FLAG), OTHER_FLAG)); in emit_single_op() 1722 FAIL_IF(push_inst(compiler, SLTU \| S(src1) \| T(src2) \| DA(OTHER_FLAG), OTHER_FLAG)); in emit_single_op() 1726 FAIL_IF(push_inst(compiler, SLTU \| S(src2) \| T(src1) \| DA(OTHER_FLAG), OTHER_FLAG)); in emit_single_op() 1782 FAIL_IF(push_inst(compiler, SLTU \| S(src1) \| T(src2) \| DA(OTHER_FLAG), OTHER_FLAG)); in emit_single_op() 1815 FAIL_IF(push_inst(compiler, SLTU \| S(src1) \| T(src2) \| DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op() 1821 FAIL_IF(push_inst(compiler, SLTU \| S(dst) \| TA(OTHER_FLAG) \| D(TMP_REG1), DR(TMP_REG1))); in emit_single_op() 3104 …PTR_FAIL_IF(push_inst(compiler, (type <= SLJIT_LESS_EQUAL ? SLTU : SLT) \| S(src1) \| T(src2) \| D(TM… in sljit_emit_cmp() [all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/RISCV/
D	RISCVGenGlobalISel.inc	10113 …// (setcc:{ :[i32] } GPR:{ :[i32] }:$rs1, 0:{ :[i32] }, SETNE:{ :[Other] }) => (SLTU:{ :[i3… 10114 GIR_BuildMI, /InsnID/0, /Opcode/RISCV::SLTU, 10128 …// (setcc:{ :[i32] } GPR:{ :[i32] }:$rs1, 0:{ :[i32] }, SETNE:{ :[Other] }) => (SLTU:{ :[i3… 10129 GIR_BuildMI, /InsnID/0, /Opcode/RISCV::SLTU, 10280 …imm:{ :[i32] })<<P:Predicate_simm12>>:$imm12, SETNE:{ :[Other] }) => (SLTU:{ :[i32] } X0:{ :… 10287 GIR_BuildMI, /InsnID/0, /Opcode/RISCV::SLTU, 10306 …imm:{ :[i32] })<<P:Predicate_simm12>>:$imm12, SETNE:{ :[Other] }) => (SLTU:{ :[i32] } X0:{ :… 10313 GIR_BuildMI, /InsnID/0, /Opcode/RISCV::SLTU, 10357 …} GPR:{ :[i32] }:$rs1, GPR:{ :[i32] }:$rs2, SETULT:{ :[Other] }) => (SLTU:{ :[i32] } GPR:{ … 10358 GIR_BuildMI, /InsnID/0, /Opcode*/RISCV::SLTU, [all …]
D	RISCVGenAsmWriter.inc	`771 6091U, // SLTU 1285 32U, // SLTU 1669 {RISCV::SLTU, 88, 1 }, 1821 // RISCV::SLTU - 88 2260 // (SLTU GPR:$rd, X0, GPR:$rs) - 340`
D	RISCVGenMCCodeEmitter.inc	`506 UINT64_C(12339), // SLTU 1253 case RISCV::SLTU: 1984 CEFBS_None, // SLTU = 493`
D	RISCVGenDAGISel.inc	6706 /* 12364/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0, 6709 // Dst: (SLTU:{ :[i32] } X0:{ :[i32] }, GPR:{ :[i32] }:$rs1) 6712 /* 12376/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0, 6715 // Dst: (SLTU:{ :[i32] } X0:{ :[i32] }, GPR:{ :[i32] }:$rs1) 6788 /* 12531/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0, 6791 …// Dst: (SLTU:{ :[i32] } X0:{ :[i32] }, (XORI:{ :[i32] } GPR:{ :[i32] }:$rs1, (imm:{ :[i32] }… 6797 /* 12553/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0, 6800 …// Dst: (SLTU:{ :[i32] } X0:{ :[i32] }, (XORI:{ :[i32] } GPR:{ :[i32] }:$rs1, (imm:{ :[i32] }… 6823 /* 12599/ OPC_MorphNodeTo1, TARGET_VAL(RISCV::SLTU), 0, 6826 // Dst: (SLTU:{ :[i32] } GPR:{ :[i32] }:$rs1, GPR:{ :[i32] }:$rs2) [all …]
D	RISCVGenAsmMatcher.inc	`2340 …{ 2408 /* sgtu /, RISCV::SLTU, Convert__Reg1_0__Reg1_2__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR, M… 2355 …{ 2456 / sltu /, RISCV::SLTU, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR, MCK_GPR, M… 2358 …{ 2466 / snez */, RISCV::SLTU, Convert__Reg1_0__regX0__Reg1_1, AMFBS_None, { MCK_GPR, MCK_GPR }, …`
D	RISCVGenInstrInfo.inc	`508 SLTU = 493, 1225 { 493, 3, 1, 4, 1, 0, 0x1ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #493 = SLTU`
D	RISCVGenDisassemblerTables.inc	`731 /* 2225 */ MCD::OPC_Decode, 237, 3, 41, // Opcode: SLTU`
/external/llvm/lib/Target/Mips/
D	Mips16InstrInfo.td	`1215 // Format: SLTU rx, ry MIPS16e`
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
D	Mips16InstrInfo.td	`1218 // Format: SLTU rx, ry MIPS16e`

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