/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 238 SMULO, UMULO, enumerator
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 258 SMULO, UMULO, enumerator
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 232 case ISD::SMULO: return "smulo"; in getOperationName()
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D | LegalizeIntegerTypes.cpp | 136 case ISD::SMULO: in PromoteIntegerResult() 772 if (N->getOpcode() == ISD::SMULO) { in PromoteIntRes_XMULO() 1402 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; in ExpandIntegerResult()
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D | LegalizeDAG.cpp | 3376 case ISD::SMULO: { in ExpandNode() 3386 bool isSigned = Node->getOpcode() == ISD::SMULO; in ExpandNode()
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D | SelectionDAG.cpp | 2128 case ISD::SMULO: in computeKnownBits() 2619 case ISD::SMULO: in ComputeNumSignBits()
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D | SelectionDAGBuilder.cpp | 5512 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break; in visitIntrinsicCall()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCTargetTransformInfo.cpp | 325 case Intrinsic::smul_with_overflow: Opcode = ISD::SMULO; break; in mightUseCTR()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorOps.cpp | 452 case ISD::SMULO: in LegalizeOp() 943 case ISD::SMULO: in Expand()
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D | SelectionDAGDumper.cpp | 296 case ISD::SMULO: return "smulo"; in getOperationName()
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D | LegalizeIntegerTypes.cpp | 145 case ISD::SMULO: in PromoteIntegerResult() 1139 if (N->getOpcode() == ISD::SMULO) { in PromoteIntRes_XMULO() 1904 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break; in ExpandIntegerResult() 3040 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()
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D | LegalizeVectorTypes.cpp | 161 case ISD::SMULO: in ScalarizeVectorResult() 956 case ISD::SMULO: in SplitVectorResult() 2767 case ISD::SMULO: in WidenVectorResult()
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D | TargetLowering.cpp | 7197 } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) { in expandFixedPointMul() 7199 DAG.getNode(ISD::SMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); in expandFixedPointMul() 7468 bool isSigned = Node->getOpcode() == ISD::SMULO; in expandMULO()
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D | SelectionDAG.cpp | 2845 case ISD::SMULO: in computeKnownBits() 3735 case ISD::SMULO: in ComputeNumSignBits() 9330 Opcode == ISD::UMULO || Opcode == ISD::SMULO) && in UnrollVectorOverflowOp()
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D | LegalizeDAG.cpp | 3499 case ISD::SMULO: { in ExpandNode()
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 1708 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering() 2961 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO() 2963 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO() 3082 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 1675 setOperationAction(ISD::SMULO, MVT::i64, Custom); in SparcTargetLowering() 2936 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO() 2938 bool isSigned = (opcode == ISD::SMULO); in LowerUMULO_SMULO() 3057 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); in LowerOperation()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 247 setOperationAction(ISD::SMULO, MVT::i32, Custom); in AArch64TargetLowering() 248 setOperationAction(ISD::SMULO, MVT::i64, Custom); in AArch64TargetLowering() 1644 case ISD::SMULO: in getAArch64XALUOOp() 1647 bool IsSigned = Op.getOpcode() == ISD::SMULO; in getAArch64XALUOOp() 2346 case ISD::SMULO: in LowerOperation() 3639 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerBR_CC() 4088 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerSELECT()
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/external/llvm/test/CodeGen/X86/ |
D | xaluo.ll | 294 ; SMULO
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 669 setOperationAction(ISD::SMULO, VT, Expand); in initActions()
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/external/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 883 setOperationAction(ISD::SMULO, VT, Expand); in initActions()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 381 setOperationAction(ISD::SMULO, MVT::i32, Custom); in AArch64TargetLowering() 382 setOperationAction(ISD::SMULO, MVT::i64, Custom); in AArch64TargetLowering() 2234 case ISD::SMULO: in getAArch64XALUOOp() 2237 bool IsSigned = Op.getOpcode() == ISD::SMULO; in getAArch64XALUOOp() 2340 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)); in isOverflowIntrOpRes() 3193 case ISD::SMULO: in LowerOperation()
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 1588 setOperationAction(ISD::SMULO, VT, Custom); in X86TargetLowering() 15905 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerSELECT() 15918 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerSELECT() 16549 Cond.getOperand(0).getOpcode() == ISD::SMULO || in LowerBRCOND() 16602 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerBRCOND() 16628 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break; in LowerBRCOND() 20516 case ISD::SMULO: in LowerXALUO() 21748 case ISD::SMULO: in LowerOperation()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 4447 case ISD::SMULO: in getARMXALUOOp() 5218 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBRCOND() 5269 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBR_CC()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 1931 setOperationAction(ISD::SMULO, VT, Custom); in X86TargetLowering() 21991 case ISD::SMULO: in getX86XALUOOp() 22281 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT() 22836 Cond.getOperand(0).getOpcode() == ISD::SMULO || in LowerBRCOND() 22889 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerBRCOND() 28638 case ISD::SMULO: in LowerOperation()
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