| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 428 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
432 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
436 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
440 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
445 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
449 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
453 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
457 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
|
| D | ARMISelLowering.cpp | 142 setOperationAction(ISD::SREM, VT, Expand); in addTypeForNEON()
791 setOperationAction(ISD::SREM, MVT::i32, Expand); in ARMTargetLowering()
796 setOperationAction(ISD::SREM, MVT::i64, Custom); in ARMTargetLowering()
7180 case ISD::SREM: return LowerREM(Op.getNode(), DAG); in LowerOperation()
7249 case ISD::SREM: in ReplaceNodeResults()
12010 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemLibcall()
12013 N->getOpcode() == ISD::SREM; in getDivRemLibcall()
12028 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemArgList()
12031 N->getOpcode() == ISD::SREM; in getDivRemArgList()
12103 bool isSigned = N->getOpcode() == ISD::SREM; in LowerREM()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 689 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
693 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
697 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
701 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
706 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
710 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
714 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
718 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
979 case ISD::SREM: in isHardwareLoopProfitable()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 248 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV || in getArithmeticInstrCost()
253 if (ISD == ISD::SDIV || ISD == ISD::SREM) { in getArithmeticInstrCost()
269 if (ISD == ISD::SREM) { in getArithmeticInstrCost()
351 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
355 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
370 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
385 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
389 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
393 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence in getArithmeticInstrCost()
407 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split. in getArithmeticInstrCost()
[all …]
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 202 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
|
| /external/llvm/test/CodeGen/ARM/ |
| D | divmod-eabi.ll | 3 ; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1675 case ISD::SREM: in selectDivRem()
1696 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
1799 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
1800 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
|
| D | MipsSEISelLowering.cpp | 170 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
217 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
267 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2023 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1932 case ISD::SREM: in selectDivRem()
1953 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2054 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
2055 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
|
| D | MipsSEISelLowering.cpp | 242 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
289 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
340 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2058 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 182 case ISD::SREM: return "srem"; in getOperationName()
|
| D | SelectionDAGBuilder.h | 836 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
|
| D | LegalizeVectorOps.cpp | 267 case ISD::SREM: in LegalizeOp()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 701 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
|
| D | SelectionDAGDumper.cpp | 232 case ISD::SREM: return "srem"; in getOperationName()
|
| D | LegalizeDAG.cpp | 3276 case ISD::SREM: { in ExpandNode()
3278 bool isSigned = Node->getOpcode() == ISD::SREM; in ExpandNode()
4148 case ISD::SREM: in ConvertNodeToLibcall()
4324 case ISD::SREM: in PromoteNode()
4342 case ISD::SREM: in PromoteNode()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 151 setOperationAction(ISD::SREM, MVT::i8, Expand); in MSP430TargetLowering()
157 setOperationAction(ISD::SREM, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 82 setOperationAction(ISD::SREM, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 791 case ISD::SREM: in canOpTrap()
1605 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 88 setOperationAction(ISD::SREM, VT, Expand); in BPFTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 138 setOperationAction(ISD::SREM, MVT::i8, Promote); in MSP430TargetLowering()
144 setOperationAction(ISD::SREM, MVT::i16, LibCall); in MSP430TargetLowering()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 970 case ISD::SREM: in canOpTrap()
1682 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 150 setOperationAction(ISD::SREM, MVT::i8, Expand); in AVRTargetLowering()
151 setOperationAction(ISD::SREM, MVT::i16, Expand); in AVRTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 523 setTargetDAGCombine(ISD::SREM); in NVPTXTargetLowering()
4543 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
4552 bool IsSigned = N->getOpcode() == ISD::SREM; in PerformREMCombine()
4771 case ISD::SREM: in PerformDAGCombine()
|