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Searched refs:SchedWrites (Results 1 – 21 of 21) sorted by relevance

/external/llvm/utils/TableGen/
DCodeGenSchedule.h241 std::vector<CodeGenSchedRW> SchedWrites; variable
319 assert(Idx < SchedWrites.size() && "bad SchedWrite index"); in getSchedWrite()
320 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite"); in getSchedWrite()
321 return SchedWrites[Idx]; in getSchedWrite()
DCodeGenSchedule.cpp206 SchedWrites.resize(1); in collectSchedRW()
281 SchedWrites.emplace_back(SchedWrites.size(), *SWI); in collectSchedRW()
289 for (std::vector<CodeGenSchedRW>::iterator WI = SchedWrites.begin(), in collectSchedRW()
290 WE = SchedWrites.end(); WI != WE; ++WI) { in collectSchedRW()
307 for (unsigned WIdx = 0, WEnd = SchedWrites.size(); WIdx != WEnd; ++WIdx) { in collectSchedRW()
309 SchedWrites[WIdx].dump(); in collectSchedRW()
342 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in getSchedRWIdx()
462 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in findRWForSequence()
484 unsigned RWIdx = IsRead ? SchedReads.size() : SchedWrites.size(); in findOrInsertRW()
489 SchedWrites.push_back(SchedRW); in findOrInsertRW()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZSchedule.td22 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
/external/llvm/include/llvm/Target/
DTargetSchedule.td230 // SchedWrites with additive latency. This allows a single operand to
232 // SchedWrites.
268 // be used instead to define subtarget specific SchedWrites and map
270 // itinerary classes to the subtarget's SchedWrites.
323 // A ReadAdvance may be associated with a list of SchedWrites
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSchedule.td234 // SchedWrites with additive latency. This allows a single operand to
236 // SchedWrites.
275 // be used instead to define subtarget specific SchedWrites and map
277 // itinerary classes to the subtarget's SchedWrites.
329 // A ReadAdvance may be associated with a list of SchedWrites
/external/llvm/lib/Target/X86/
DX86ScheduleSLM.td54 // Many SchedWrites are defined in pairs with and without a folded load.
DX86SchedSandyBridge.td67 // Many SchedWrites are defined in pairs with and without a folded load.
DX86ScheduleBtVer2.td72 // Many SchedWrites are defined in pairs with and without a folded load.
DX86Schedule.td32 // Multiclass that produces a linked pair of SchedWrites.
DX86SchedHaswell.td77 // Many SchedWrites are defined in pairs with and without a folded load.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86Schedule.td53 // Multiclass that produces a linked pair of SchedWrites.
64 // Helpers to mark SchedWrites as unsupported.
DX86ScheduleSLM.td57 // Many SchedWrites are defined in pairs with and without a folded load.
DX86ScheduleAtom.td51 // Many SchedWrites are defined in pairs with and without a folded load.
DX86ScheduleBtVer2.td116 // Many SchedWrites are defined in pairs with and without a folded load.
DX86SchedSandyBridge.td81 // Many SchedWrites are defined in pairs with and without a folded load.
DX86ScheduleBdVer2.td185 // Many SchedWrites are defined in pairs with and without a folded load.
DX86SchedBroadwell.td86 // Many SchedWrites are defined in pairs with and without a folded load.
DX86SchedSkylakeClient.td85 // Many SchedWrites are defined in pairs with and without a folded load.
DX86SchedHaswell.td91 // Many SchedWrites are defined in pairs with and without a folded load.
DX86SchedSkylakeServer.td85 // Many SchedWrites are defined in pairs with and without a folded load.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleR52.td142 // Cortex-R52 specific SchedWrites for use with InstRW