| /external/openthread/examples/platforms/cc2538/ |
| D | uart.c | 108 HWREG(UART0_BASE + UART_O_CC) = 0; in otPlatUartEnable()
120 HWREG(UART0_BASE + UART_O_CTL) = 0; in otPlatUartEnable()
124 HWREG(UART0_BASE + UART_O_IBRD) = div / 64; in otPlatUartEnable()
125 HWREG(UART0_BASE + UART_O_FBRD) = div % 64; in otPlatUartEnable()
126 …HWREG(UART0_BASE + UART_O_LCRH) = UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE; in otPlatUartEnable()
129 HWREG(UART0_BASE + UART_O_IM) |= UART_IM_RXIM | UART_IM_RTIM; in otPlatUartEnable()
132 HWREG(UART0_BASE + UART_O_CTL) = UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE; in otPlatUartEnable()
188 while (HWREG(UART0_BASE + UART_O_FR) & UART_FR_TXFF) in otPlatUartFlush()
191 HWREG(UART0_BASE + UART_O_DR) = *sTransmitBuffer++; in otPlatUartFlush()
218 mis = HWREG(UART0_BASE + UART_O_MIS); in UART0IntHandler()
[all …]
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| D | cc2538-reg.h | 268 #define UART0_BASE 0x4000C000 macro
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| /external/arm-trusted-firmware/plat/mediatek/mt6795/aarch64/ |
| D | plat_helpers.S | 105 mov_imm x0, UART0_BASE
120 mov_imm x1, UART0_BASE
134 mov_imm x0, UART0_BASE
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| /external/arm-trusted-firmware/plat/qemu/qemu/include/ |
| D | platform_def.h | 194 #define UART0_BASE 0x09000000 macro
199 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
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| /external/arm-trusted-firmware/plat/qemu/qemu_sbsa/include/ |
| D | platform_def.h | 180 #define UART0_BASE 0x60000000 macro
189 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
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| /external/arm-trusted-firmware/plat/rockchip/rk3368/ |
| D | rk3368_def.h | 38 #define UART0_BASE 0xff180000 macro
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| /external/arm-trusted-firmware/plat/mediatek/mt8195/ |
| D | bl31_plat_setup.c | 75 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); in bl31_early_platform_setup2()
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| /external/arm-trusted-firmware/plat/mediatek/mt8192/ |
| D | bl31_plat_setup.c | 76 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); in bl31_early_platform_setup2()
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| /external/arm-trusted-firmware/plat/rockchip/rk3288/ |
| D | rk3288_def.h | 31 #define UART0_BASE 0xff180000 macro
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| /external/arm-trusted-firmware/plat/mediatek/mt8195/include/ |
| D | platform_def.h | 60 #define UART0_BASE (IO_PHYS + 0x01001100) macro
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| /external/arm-trusted-firmware/plat/rockchip/rk3328/ |
| D | rk3328_def.h | 18 #define UART0_BASE 0xff110000 macro
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| /external/arm-trusted-firmware/plat/mediatek/mt8192/include/ |
| D | platform_def.h | 66 #define UART0_BASE (IO_PHYS + 0x01002000) macro
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/ |
| D | bl31_plat_setup.c | 127 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); in bl31_early_platform_setup2()
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| /external/arm-trusted-firmware/plat/rockchip/px30/ |
| D | px30_def.h | 31 #define UART0_BASE 0xff030000 macro
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| /external/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/ |
| D | addressmap_shared.h | 21 #define UART0_BASE (MMIO_BASE + 0x07180000) macro
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| /external/arm-trusted-firmware/plat/mediatek/mt6795/include/ |
| D | platform_def.h | 42 #define UART0_BASE (PERI_BASE + 0x2000) macro
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| /external/arm-trusted-firmware/plat/rockchip/common/ |
| D | params_setup.c | 83 uart_base = UART0_BASE; in plat_rockchip_dt_process_fdt_uart()
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| /external/arm-trusted-firmware/plat/rockchip/rk3328/drivers/soc/ |
| D | soc.c | 22 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
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| /external/arm-trusted-firmware/plat/mediatek/common/drivers/uart/ |
| D | uart.c | 13 UART0_BASE,
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| /external/arm-trusted-firmware/plat/rockchip/rk3288/drivers/soc/ |
| D | soc.c | 37 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/include/ |
| D | platform_def.h | 99 #define UART0_BASE (IO_PHYS + 0x01002000) macro
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| /external/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/ |
| D | soc.c | 33 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
|