| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 238 SMULO, UMULO, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 258 SMULO, UMULO, enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 233 case ISD::UMULO: return "umulo"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 137 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
786 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
1401 case ISD::UMULO: in ExpandIntegerResult()
2548 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
|
| D | SelectionDAG.cpp | 2129 case ISD::UMULO: in computeKnownBits()
2620 case ISD::UMULO: in ComputeNumSignBits()
|
| D | LegalizeDAG.cpp | 3375 case ISD::UMULO: in ExpandNode()
|
| D | SelectionDAGBuilder.cpp | 5511 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; in visitIntrinsicCall()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 146 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
1153 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
1903 case ISD::UMULO: in ExpandIntegerResult()
3040 unsigned MulOp = Signed ? ISD::SMULO : ISD::UMULO; in ExpandIntRes_MULFIX()
3518 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
3545 SDValue One = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, LHSHigh, RHSLow); in ExpandIntRes_XMULO()
3550 SDValue Two = DAG.getNode(ISD::UMULO, dl, VTHalfMulO, RHSHigh, LHSLow); in ExpandIntRes_XMULO()
|
| D | LegalizeVectorOps.cpp | 453 case ISD::UMULO: in LegalizeOp()
942 case ISD::UMULO: in Expand()
|
| D | SelectionDAGDumper.cpp | 297 case ISD::UMULO: return "umulo"; in getOperationName()
|
| D | LegalizeVectorTypes.cpp | 160 case ISD::UMULO: in ScalarizeVectorResult()
955 case ISD::UMULO: in SplitVectorResult()
2766 case ISD::UMULO: in WidenVectorResult()
|
| D | SelectionDAG.cpp | 2846 case ISD::UMULO: in computeKnownBits()
3736 case ISD::UMULO: in ComputeNumSignBits()
9330 Opcode == ISD::UMULO || Opcode == ISD::SMULO) && in UnrollVectorOverflowOp()
|
| D | TargetLowering.cpp | 7211 } else if (!Signed && isOperationLegalOrCustom(ISD::UMULO, VT)) { in expandFixedPointMul()
7213 DAG.getNode(ISD::UMULO, dl, DAG.getVTList(VT, BoolVT), LHS, RHS); in expandFixedPointMul()
|
| D | LegalizeDAG.cpp | 3498 case ISD::UMULO: in ExpandNode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 324 case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break; in mightUseCTR()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1707 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
2961 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3081 case ISD::UMULO: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1674 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
2936 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3056 case ISD::UMULO: in LowerOperation()
|
| /external/llvm/test/CodeGen/X86/ |
| D | xaluo.ll | 344 ; UMULO
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 670 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 884 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 249 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()
250 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()
1645 case ISD::UMULO: { in getAArch64XALUOOp()
2347 case ISD::UMULO: in LowerOperation()
3639 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerBR_CC()
4088 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerSELECT()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1589 setOperationAction(ISD::UMULO, VT, Custom); in X86TargetLowering()
15905 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerSELECT()
15917 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerSELECT()
15921 if (CondOpcode == ISD::UMULO) in LowerSELECT()
15929 if (CondOpcode == ISD::UMULO) in LowerSELECT()
16550 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { in LowerBRCOND()
16602 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerBRCOND()
16627 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerBRCOND()
16633 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
16641 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 383 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()
384 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()
2235 case ISD::UMULO: { in getAArch64XALUOOp()
2340 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)); in isOverflowIntrOpRes()
3194 case ISD::UMULO: in LowerOperation()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4437 case ISD::UMULO: in getARMXALUOOp()
5218 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBRCOND()
5269 bool OptimizeMul = (Opc == ISD::SMULO || Opc == ISD::UMULO) && in LowerBR_CC()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1932 setOperationAction(ISD::UMULO, VT, Custom); in X86TargetLowering()
21995 case ISD::UMULO: in getX86XALUOOp()
22281 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerSELECT()
22837 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { in LowerBRCOND()
22889 CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) { in LowerBRCOND()
28639 case ISD::UMULO: return LowerXALUO(Op, DAG); in LowerOperation()
|