| /external/llvm/lib/Target/X86/ |
| D | X86InstrMMX.td | 244 Sched<[WriteStore]>;
287 [], IIC_MMX_MOV_REG_MM>, Sched<[WriteStore]>;
296 let SchedRW = [WriteStore] in
334 IIC_MMX_MOVQ_RM>, Sched<[WriteStore]>;
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| D | X86InstrCMovSetCC.td | 92 IIC_SET_M>, TB, Sched<[WriteALU, WriteStore]>;
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| D | X86ScheduleSLM.td | 76 def : WriteRes<WriteStore, [IEC_RSV01, MEC_RSV]>;
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| D | X86SchedSandyBridge.td | 89 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
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| D | X86ScheduleBtVer2.td | 144 def : WriteRes<WriteStore, [JSAGU]>;
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| D | X86InstrInfo.td | 1108 let mayStore = 1, SchedRW = [WriteStore] in {
1175 SchedRW = [WriteStore] in {
1191 let mayStore = 1, SchedRW = [WriteStore] in {
1204 SchedRW = [WriteStore] in {
1218 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1228 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1400 let SchedRW = [WriteStore] in {
1543 let SchedRW = [WriteStore] in {
1571 IIC_MOV_MEM>, Sched<[WriteStore]>;
2096 let SchedRW = [WriteStore] in {
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| D | X86InstrSSE.td | 541 VEX, VEX_LIG, Sched<[WriteStore]>;
551 Sched<[WriteStore]>;
832 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
923 let SchedRW = [WriteStore] in {
1147 let SchedRW = [WriteStore] in {
1256 let SchedRW = [WriteStore] in {
3543 let SchedRW = [WriteStore] in {
3613 } // SchedRW = [WriteStore]
3704 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3712 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
[all …]
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| D | X86InstrFPStack.td | 483 let mayStore = 1, SchedRW = [WriteStore] in {
528 let mayStore = 1, SchedRW = [WriteStore] in {
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| D | X86Schedule.td | 54 def WriteStore : SchedWrite;
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| D | X86SchedHaswell.td | 101 def : WriteRes<WriteStore, [HWPort237, HWPort4]>;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleSLM.td | 86 def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
93 // FIXME: These are probably wrong. They are copy pasted from WriteStore/Load.
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| D | X86InstrFPStack.td | 511 let SchedRW = [WriteStore], Uses = [FPCW] in {
558 let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {
572 let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in {
593 let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {
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| D | X86InstrInfo.td | 1270 let mayStore = 1, SchedRW = [WriteStore] in {
1339 SchedRW = [WriteStore] in {
1358 let mayStore = 1, SchedRW = [WriteStore] in {
1374 SchedRW = [WriteStore] in {
1388 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>;
1398 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
1578 let SchedRW = [WriteStore] in {
1750 let SchedRW = [WriteStore] in {
1778 Sched<[WriteStore]>;
2310 let SchedRW = [WriteStore] in {
[all …]
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| D | X86Schedule.td | 125 def WriteStore : SchedWrite;
128 def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
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| D | X86ScheduleAtom.td | 168 def : WriteRes<WriteStore, [AtomPort0]>;
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| D | X86ScheduleBtVer2.td | 273 def : WriteRes<WriteStore, [JSAGU]>;
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| D | X86SchedSandyBridge.td | 110 def : WriteRes<WriteStore, [SBPort23, SBPort4]>;
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| D | X86ScheduleZnver2.td | 176 def : WriteRes<WriteStore, [Zn2AGU]>;
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| D | X86ScheduleBdVer2.td | 269 def : WriteRes<WriteStore, [PdStore]>;
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| D | X86ScheduleZnver1.td | 177 def : WriteRes<WriteStore, [ZnAGU]>;
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| D | X86SchedBroadwell.td | 205 defm : X86WriteRes<WriteStore, [BWPort237, BWPort4], 1, [1,1], 1>;
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| /external/angle/src/libANGLE/renderer/vulkan/ |
| D | spv_utils.cpp | 1542 spirv::WriteStore(blobOut, id, tempVar, nullptr); in writeInputPreamble()
1589 spirv::WriteStore(blobOut, mFixedVaryingId[id], tempVar, nullptr); in writeOutputPrologue()
2074 spirv::WriteStore(blobOut, ID::XfbExtensionPosition, positionId, nullptr); in writeTransformFeedbackExtensionOutput()
2340 spirv::WriteStore(blobOut, xfbOffsetsVar, xfbOffsetsResult, nullptr); in writeGetOffsetsCall()
2395 spirv::WriteStore(blobOut, xfbOutPtr, asFloat, nullptr); in writeComponentCapture()
2514 spirv::WriteStore(blobOut, positionPointerId, transformedPositionId, nullptr); in writePositionTransformation()
4777 spirv::WriteStore(mSpirvBlobOut, matrixId, compositeId, nullptr); in writeExpandedMatrixInitialization()
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| D | UtilsVk.cpp | 968 spirv::WriteStore(blobOut, outId, imageReadResult, nullptr); in InsertColorUnresolveLoadStore()
992 spirv::WriteStore(blobOut, outId, extractResult, nullptr); in InsertDepthStencilUnresolveLoadStore()
1015 spirv::WriteStore(blobOut, outId, bitcastResult, nullptr); in InsertDepthStencilUnresolveLoadStore()
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| /external/angle/src/compiler/translator/spirv/ |
| D | OutputSPIRV.cpp | 985 spirv::WriteStore(mBuilder.getSpirvCurrentFunctionBlock(), tempVar, loadResult, in accessChainLoad()
1117 spirv::WriteStore(mBuilder.getSpirvCurrentFunctionBlock(), accessChainId, value, nullptr); in accessChainStore()
2136 spirv::WriteStore(mBuilder.getSpirvCurrentFunctionBlock(), tempVarIds[paramIndex], in createFunctionCall()
6098 spirv::WriteStore(mBuilder.getSpirvCurrentFunctionBlock(), variableId, initializerId, in visitDeclaration()
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| /external/angle/src/common/spirv/ |
| D | spirv_instruction_builder_autogen.h | 136 void WriteStore(Blob *blob, IdRef pointer, IdRef object, const spv::MemoryAccessMask *memoryAccess);
|