| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1026 ZEXTLOAD enumerator
1029 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 830 ZEXTLOAD, enumerator
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 103 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
115 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
116 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
117 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
118 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
129 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
135 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
138 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
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| D | R600ISelLowering.cpp | 57 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
58 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
59 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
69 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
73 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
1592 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
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| D | AMDGPUInstructions.td | 252 return L->getExtensionType() == ISD::ZEXTLOAD ||
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 663 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
695 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
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| D | DAGCombiner.cpp | 4780 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { in isAndLoadExtLoad()
4796 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT)) in isAndLoadExtLoad()
4799 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) in isAndLoadExtLoad()
4908 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) { in SearchForAndLoads()
4911 if (Load->getExtensionType() == ISD::ZEXTLOAD && in SearchForAndLoads()
5294 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, in visitAND()
5307 case ISD::ZEXTLOAD: in visitAND()
5320 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, in visitAND()
5410 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) { in visitAND()
5412 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(), in visitAND()
[all …]
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| D | LegalizeDAG.cpp | 749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
762 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
790 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
826 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
907 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, ILoadVT, Chain, in LegalizeLoadOps()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 83 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
84 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
85 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
95 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); in R600TargetLowering()
99 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand); in R600TargetLowering()
1468 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) { in LowerLOAD()
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| D | AMDGPUISelLowering.cpp | 111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
123 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in AMDGPUTargetLowering()
124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in AMDGPUTargetLowering()
125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in AMDGPUTargetLowering()
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in AMDGPUTargetLowering()
137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand); in AMDGPUTargetLowering()
143 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); in AMDGPUTargetLowering()
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand); in AMDGPUTargetLowering()
149 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 251 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
306 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
482 IntExt = ISD::ZEXTLOAD; in tryLoadOfLoadIntrinsic()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 961 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteOperand()
1186 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD in PromoteLoad()
3021 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) { in isAndLoadExtLoad()
3038 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT)) in isAndLoadExtLoad()
3041 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT)) in isAndLoadExtLoad()
3183 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, in visitAND()
3197 case ISD::ZEXTLOAD: in visitAND()
3206 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, in visitAND()
3249 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
3277 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, in visitAND()
[all …]
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| D | SelectionDAGDumper.cpp | 504 case ISD::ZEXTLOAD: OS << ", zext"; break; in print_details()
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| D | LegalizeDAG.cpp | 705 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
720 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
746 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), in LegalizeLoadOps()
787 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, in LegalizeLoadOps()
870 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT, in LegalizeLoadOps()
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| D | TargetLowering.cpp | 1448 if (LN0->getExtensionType() == ISD::ZEXTLOAD) { in SimplifySetCC()
3357 HiExtType = ISD::ZEXTLOAD; in expandUnalignedLoad()
3362 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), in expandUnalignedLoad()
3380 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, in expandUnalignedLoad()
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| D | LegalizeVectorOps.cpp | 607 case ISD::ZEXTLOAD: in ExpandLoad()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 248 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
256 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
263 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) { in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 133 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD}) in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 115 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 78 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
134 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
286 IntExt = ISD::ZEXTLOAD; in tryLoadOfLoadIntrinsic()
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| D | HexagonISelLowering.cpp | 1445 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in HexagonTargetLowering()
1505 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand); in HexagonTargetLowering()
1524 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal); in HexagonTargetLowering()
1527 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
129 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); in XCoreTargetLowering()
447 DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr, in LowerLOAD()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 128 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in XCoreTargetLowering()
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand); in XCoreTargetLowering()
461 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, in LowerLOAD()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in BPFTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 245 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SystemZTargetLowering()
279 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand); in SystemZTargetLowering()
1654 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) { in adjustSubwordCmp()
1665 ISD::ZEXTLOAD); in adjustSubwordCmp()
1694 case ISD::ZEXTLOAD: in isNaturalMemoryOperand()
1849 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) || in adjustICmpTruncate()
|