Searched refs:outinfo (Results 1 – 6 of 6) sorted by relevance
326 radv_vs_output_info *outinfo) in setup_vs_output_info() argument328 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED, in setup_vs_output_info()329 sizeof(outinfo->vs_output_param_offset)); in setup_vs_output_info()331 outinfo->param_exports = 0; in setup_vs_output_info()333 if (outinfo->writes_pointsize || outinfo->writes_viewport_index || outinfo->writes_layer) in setup_vs_output_info()342 if (outinfo->vs_output_param_offset[idx] == AC_EXP_PARAM_UNDEFINED) in setup_vs_output_info()343 outinfo->vs_output_param_offset[idx] = outinfo->param_exports++; in setup_vs_output_info()346 if (outinfo->writes_layer && in setup_vs_output_info()347 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] == AC_EXP_PARAM_UNDEFINED) { in setup_vs_output_info()350 outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = outinfo->param_exports++; in setup_vs_output_info()[all …]
10141 ? ctx->program->info->tes.outinfo.vs_output_param_offset[slot] in export_vs_varying()10142 : ctx->program->info->vs.outinfo.vs_output_param_offset[slot]; in export_vs_varying()10237 radv_vs_output_info *outinfo = (ctx->stage.has(SWStage::TES) && !ctx->stage.has(SWStage::GS)) in create_vs_exports() local10238 ? &ctx->program->info->tes.outinfo in create_vs_exports()10239 : &ctx->program->info->vs.outinfo; in create_vs_exports()10241 if (outinfo->export_prim_id && ctx->stage.hw != HWStage::NGG) { in create_vs_exports()10262 if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index) { in create_vs_exports()
466 vs_info = &info->vs.outinfo; in gather_info_output_decl()473 vs_info = &info->vs.outinfo; in gather_info_output_decl()478 vs_info = &info->tes.outinfo; in gather_info_output_decl()600 info->vs.outinfo.writes_layer = true; in radv_nir_shader_info_pass()603 info->tes.outinfo.writes_layer = true; in radv_nir_shader_info_pass()606 info->vs.outinfo.writes_layer = true; in radv_nir_shader_info_pass()617 info->vs.outinfo.export_prim_id = true; in radv_nir_shader_info_pass()620 info->tes.outinfo.export_prim_id = true; in radv_nir_shader_info_pass()623 info->vs.outinfo.export_prim_id = true; in radv_nir_shader_info_pass()
1707 struct radv_vs_output_info *outinfo, in radv_build_param_exports() argument1730 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset)); in radv_build_param_exports()1731 outinfo->vs_output_param_offset[slot_name] = param_count++; in radv_build_param_exports()1734 outinfo->param_exports = param_count; in radv_build_param_exports()1744 struct radv_vs_output_info *outinfo, in radv_llvm_export_vs() argument1793 if (outinfo->writes_pointsize || in radv_llvm_export_vs()1794 outinfo->writes_layer || in radv_llvm_export_vs()1795 outinfo->writes_viewport_index) { in radv_llvm_export_vs()1796 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) | in radv_llvm_export_vs()1797 (outinfo->writes_layer == true ? 4 : 0)); in radv_llvm_export_vs()[all …]
2024 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id) in gfx10_get_ngg_info()2218 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo; in get_vs_output_info()2220 return &pipeline->gs_copy_shader->info.vs.outinfo; in get_vs_output_info()2222 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo; in get_vs_output_info()2224 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo; in get_vs_output_info()4160 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_vgt_gs_mode() local4177 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) { in radv_pipeline_generate_vgt_gs_mode()4200 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); in radv_pipeline_generate_hw_vs() local4202 clip_dist_mask = outinfo->clip_dist_mask; in radv_pipeline_generate_hw_vs()4203 cull_dist_mask = outinfo->cull_dist_mask; in radv_pipeline_generate_hw_vs()[all …]
270 struct radv_vs_output_info outinfo; member293 struct radv_vs_output_info outinfo; member