| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 59 M(qsub8) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 58 M(qsub8) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 506 0xf3,0x1f,0x22,0xe6 = qsub8 r1, r2, r3
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2851 void qsub8(Condition cond, Register rd, Register rn, Register rm);
2852 void qsub8(Register rd, Register rn, Register rm) { qsub8(al, rd, rn, rm); } in qsub8() function
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| D | disasm-aarch32.h | 1006 void qsub8(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2242 void Disassembler::qsub8(Condition cond, in qsub8() function in vixl::aarch32::Disassembler
21367 qsub8(CurrentCond(), in DecodeT32()
62737 qsub8(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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| D | assembler-aarch32.cc | 8818 void Assembler::qsub8(Condition cond, Register rd, Register rn, Register rm) { in qsub8() function in vixl::aarch32::Assembler
8838 Delegate(kQsub8, &Assembler::qsub8, cond, rd, rn, rm); in qsub8()
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| D | macro-assembler-aarch32.h | 3065 qsub8(cond, rd, rn, rm); in Qsub8()
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1904 qsub8 r1, r2, r3
1912 @ CHECK: qsub8 r1, r2, r3 @ encoding: [0xc2,0xfa,0x13,0xf1]
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| D | basic-arm-instructions.s | 1833 qsub8 r1, r2, r3
1840 @ CHECK: qsub8 r1, r2, r3 @ encoding: [0xf3,0x1f,0x22,0xe6]
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1179 # CHECK: qsub8 r1, r2, r3
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| D | thumb2.txt | 1416 # CHECK: qsub8 r1, r2, r3
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| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 592 { /* ARM_QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */
5872 { /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */
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| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 592 { /* ARM_QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */
5872 { /* ARM_t2QSUB8, ARM_INS_QSUB8: qsub8${p} $rd, $rn, $rm */
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2150 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">;
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| D | ARMInstrInfo.td | 3579 def QSUB8 : AAI<0b01100010, 0b11111111, "qsub8">;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2424 def t2QSUB8 : T2I_pam_intrinsics<0b100, 0b0001, "qsub8", int_arm_qsub8>;
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| D | ARMInstrInfo.td | 3770 def QSUB8 : AAIIntrinsic<0b01100010, 0b11111111, "qsub8", int_arm_qsub8>;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9895 "qdadd\005qdsub\004qsax\004qsub\006qsub16\005qsub8\004rbit\003rev\005rev"
10972 …{ 850 /* qsub8 */, ARM::t2QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_HasD…
10973 …{ 850 /* qsub8 */, ARM::QSUB8, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM, { MCK_Co…
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| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 1822 "llvm.arm.qsub8",
11955 1, // llvm.arm.qsub8
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