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/external/oss-fuzz/infra/build/functions/
Dproject_sync_test.py69 self.schedulers = []
79 self.schedulers.append(job)
88 for job in self.schedulers:
90 self.schedulers.remove(job)
95 for existing_job in self.schedulers:
182 ], cloud_scheduler_client.schedulers)
/external/strace/
Dsched.c44 tcp->auxstr = xlookup(schedulers, (kernel_ulong_t) tcp->u_rval); in SYS_FUNC()
53 printxval(schedulers, tcp->u_arg[1], "SCHED_???"); in SYS_FUNC()
79 printxval(schedulers, tcp->u_arg[0], "SCHED_???"); in SYS_FUNC()
129 printxval(schedulers, attr.sched_policy, "SCHED_???"); in print_sched_attr()
/external/strace/tests/
Dsched_xetattr.c101 printxval(schedulers, attr->sched_policy, NULL); in main()
126 printxval(schedulers, attr->sched_policy, NULL); in main()
147 printxval(schedulers, attr->sched_policy, NULL); in main()
161 printxval(schedulers, attr->sched_policy, NULL); in main()
181 printxval(schedulers, attr->sched_policy, NULL); in main()
/external/strace/tests-mx32/
Dsched_xetattr.c101 printxval(schedulers, attr->sched_policy, NULL); in main()
126 printxval(schedulers, attr->sched_policy, NULL); in main()
147 printxval(schedulers, attr->sched_policy, NULL); in main()
161 printxval(schedulers, attr->sched_policy, NULL); in main()
181 printxval(schedulers, attr->sched_policy, NULL); in main()
/external/strace/tests-m32/
Dsched_xetattr.c101 printxval(schedulers, attr->sched_policy, NULL); in main()
126 printxval(schedulers, attr->sched_policy, NULL); in main()
147 printxval(schedulers, attr->sched_policy, NULL); in main()
161 printxval(schedulers, attr->sched_policy, NULL); in main()
181 printxval(schedulers, attr->sched_policy, NULL); in main()
/external/strace/xlat/
Dschedulers.h11 # error static const struct xlat schedulers in mpers mode
16 const struct xlat schedulers[] = { variable
DMakemodule.am1 …i_function_codes.in xlat/sa_handler_values.in xlat/sched_flags.in xlat/schedulers.in xlat/scmvals.…
2 …thyi_function_codes.h xlat/sa_handler_values.h xlat/sched_flags.h xlat/schedulers.h xlat/scmvals.h…
705 $(top_srcdir)/xlat/schedulers.h: $(top_srcdir)/xlat/schedulers.in $(top_srcdir)/xlat/gen.sh
/external/kotlinx.coroutines/reactive/kotlinx-coroutines-rx2/
Dpackage.list12 io.reactivex.schedulers
/external/kotlinx.coroutines/reactive/kotlinx-coroutines-rx3/
Dpackage.list12 io.reactivex.rxjava3.schedulers
/external/llvm/test/CodeGen/Generic/
D2006-07-03-schedulers.ll6 ; The top-down schedulers are excluded here because they don't yet support
/external/rust/crates/crossbeam-deque/
DREADME.md16 building task schedulers.
/external/webrtc/infra/config/
Drealms.cfg78 principals: "group:project-webrtc-ci-schedulers"
/external/llvm/docs/CommandGuide/
Dlli.rst155 Instruction schedulers available (before register allocation):
/external/kotlinx.coroutines/reactive/kotlinx-coroutines-rx3/test/
DSchedulerTest.kt10 import io.reactivex.rxjava3.schedulers.* in <lambda>()
/external/kotlinx.coroutines/reactive/kotlinx-coroutines-rx2/test/
DSchedulerTest.kt10 import io.reactivex.schedulers.* in <lambda>()
/external/python/cpython2/Doc/library/
Dheapq.rst269 heap. So, a heap is a good structure for implementing schedulers (this is what
272 Various structures for implementing schedulers have been extensively studied,
/external/python/cpython3/Doc/library/
Dheapq.rst281 heap. So, a heap is a good structure for implementing schedulers (this is what
284 Various structures for implementing schedulers have been extensively studied,
Dinspect.rst1355 When implementing coroutine schedulers and for other advanced uses of
/external/llvm/lib/Target/X86/
DX86ScheduleBtVer2.td74 // as two micro-ops when dispatched by the schedulers.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ScheduleAtom.td53 // as two micro-ops when dispatched by the schedulers.
DX86ScheduleBtVer2.td118 // as two micro-ops when dispatched by the schedulers.
DX86ScheduleBdVer2.td187 // as two micro-ops when dispatched by the schedulers.
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMScheduleSwift.td15 // required until SD and PostRA schedulers are replaced by MachineScheduler.
/external/llvm/lib/Target/ARM/
DARMScheduleSwift.td16 // required until SD and PostRA schedulers are replaced by MachineScheduler.
/external/blktrace/btt/doc/
Dbtt.tex321 An important consideration when analyzing block IO schedulers is to

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