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Searched refs:stencil_write_mask (Results 1 – 23 of 23) sorted by relevance

/external/mesa3d/src/intel/vulkan/
Dgen8_cmd_buffer.c394 (cmd_buffer->state.gfx.dynamic.stencil_write_mask.front || in want_stencil_pma_fix()
395 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back) && in want_stencil_pma_fix()
503 .StencilWriteMask = d->stencil_write_mask.front & 0xff, in genX()
506 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff, in genX()
509 (d->stencil_write_mask.front || d->stencil_write_mask.back) && in genX()
569 .StencilWriteMask = d->stencil_write_mask.front & 0xff, in genX()
572 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff, in genX()
578 (d->stencil_write_mask.front || d->stencil_write_mask.back) && in genX()
Dgen7_cmd_buffer.c274 .StencilWriteMask = d->stencil_write_mask.front & 0xff, in genX()
277 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff, in genX()
280 (d->stencil_write_mask.front || d->stencil_write_mask.back) && in genX()
Danv_cmd_buffer.c67 .stencil_write_mask = {
159 ANV_CMP_COPY(stencil_write_mask.front, ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK); in anv_dynamic_state_copy()
160 ANV_CMP_COPY(stencil_write_mask.back, ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK); in anv_dynamic_state_copy()
656 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask; in anv_CmdSetStencilWriteMask()
658 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask; in anv_CmdSetStencilWriteMask()
Danv_pipeline.c1985 dynamic->stencil_write_mask.front = in copy_non_dynamic_state()
1987 dynamic->stencil_write_mask.back = in copy_non_dynamic_state()
Danv_private.h2739 } stencil_write_mask; member
/external/deqp/android/cts/main/vksc-master/
Ddynamic-state.txt32 dEQP-VKSC.dynamic_state.compute_transfer.single.compute.stencil_write_mask.before
33 dEQP-VKSC.dynamic_state.compute_transfer.single.compute.stencil_write_mask.after
82 dEQP-VKSC.dynamic_state.compute_transfer.single.transfer.stencil_write_mask.before
83 dEQP-VKSC.dynamic_state.compute_transfer.single.transfer.stencil_write_mask.after
/external/deqp/android/cts/main/vk-master-2021-03-01/
Ddynamic-state.txt21 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.before
22 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.after
81 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.before
82 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.after
/external/deqp/android/cts/main/vksc-main/
Ddynamic-state.txt67 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.before
68 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.after
117 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.before
118 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.after
/external/deqp/external/vulkancts/mustpass/main/vksc-default/
Ddynamic-state.txt67 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.before
68 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.after
117 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.before
118 dEQP-VKSC.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.after
/external/swiftshader/tests/regres/testlists/vk-default/
Ddynamic-state.txt113 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.before
114 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.after
173 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.before
174 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.after
/external/deqp/external/vulkancts/mustpass/main/vk-default/
Ddynamic-state.txt113 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.before
114 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.after
173 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.before
174 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.after
/external/deqp/android/cts/main/vk-master/
Ddynamic-state.txt113 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.before
114 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.compute.stencil_write_mask.after
173 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.before
174 dEQP-VK.dynamic_state.monolithic.compute_transfer.single.transfer.stencil_write_mask.after
/external/igt-gpu-tools/assembler/
Dbrw_structs.h280 unsigned stencil_write_mask:8; member
316 unsigned stencil_write_mask:8; member
/external/igt-gpu-tools/lib/
Dgen4_render.h565 unsigned int stencil_write_mask:8; member
Dgen6_render.h879 uint32_t stencil_write_mask:8; member
/external/mesa3d/src/broadcom/vulkan/
Dv3dv_cmd_buffer.c42 .stencil_write_mask =
2799 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask, in cmd_buffer_bind_pipeline_static_state()
2800 sizeof(src->stencil_write_mask))) { in cmd_buffer_bind_pipeline_static_state()
2801 dest->stencil_write_mask = src->stencil_write_mask; in cmd_buffer_bind_pipeline_static_state()
3417 config.stencil_write_mask = in emit_stencil()
3418 i == 0 ? dynamic_state->stencil_write_mask.front : in emit_stencil()
3419 dynamic_state->stencil_write_mask.back; in emit_stencil()
4617 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask & 0xff; in v3dv_CmdSetStencilWriteMask()
4619 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask & 0xff; in v3dv_CmdSetStencilWriteMask()
Dv3dv_pipeline.c2148 dynamic->stencil_write_mask.front = pDepthStencilState->front.writeMask; in pipeline_init_dynamic_state()
2149 dynamic->stencil_write_mask.back = pDepthStencilState->back.writeMask; in pipeline_init_dynamic_state()
2428 config.stencil_write_mask = write_mask; in pack_single_stencil_cfg()
Dv3dv_private.h704 } stencil_write_mask; member
/external/mesa3d/src/amd/vulkan/
Dradv_cmd_buffer.c87 .stencil_write_mask = {
186 if (memcmp(&dest->stencil_write_mask, &src->stencil_write_mask, in radv_bind_dynamic_state()
187 sizeof(src->stencil_write_mask))) { in radv_bind_dynamic_state()
188 dest->stencil_write_mask = src->stencil_write_mask; in radv_bind_dynamic_state()
1400 S_028430_STENCILWRITEMASK(d->stencil_write_mask.front) | in radv_emit_stencil()
1405 S_028434_STENCILWRITEMASK_BF(d->stencil_write_mask.back) | in radv_emit_stencil()
4442 bool front_same = state->dynamic.stencil_write_mask.front == writeMask; in radv_CmdSetStencilWriteMask()
4443 bool back_same = state->dynamic.stencil_write_mask.back == writeMask; in radv_CmdSetStencilWriteMask()
4451 state->dynamic.stencil_write_mask.front = writeMask; in radv_CmdSetStencilWriteMask()
4453 state->dynamic.stencil_write_mask.back = writeMask; in radv_CmdSetStencilWriteMask()
Dradv_private.h1170 } stencil_write_mask; member
Dradv_pipeline.c1612 dynamic->stencil_write_mask.front = in radv_pipeline_init_dynamic_state()
1614 dynamic->stencil_write_mask.back = in radv_pipeline_init_dynamic_state()
/external/mesa3d/src/gallium/drivers/v3d/
Dv3dx_state.c223 config.stencil_write_mask = front->writemask; in v3d_create_depth_stencil_alpha_state()
242 config.stencil_write_mask = back->writemask; in v3d_create_depth_stencil_alpha_state()
/external/mesa3d/prebuilt-intermediates/cle/
Dv3d_packet_v33_pack.h2091 uint32_t stencil_write_mask; member
2121 cl[ 5] = __gen_uint(values->stencil_write_mask, 0, 7); in V3D33_STENCIL_CFG_pack()
2132 values->stencil_write_mask = __gen_unpack_uint(cl, 40, 47); in V3D33_STENCIL_CFG_unpack()