1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "vk_format_info.h"
32
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
35
36 #if GEN_GEN == 7 && !GEN_IS_HASWELL
37 static int64_t
clamp_int64(int64_t x,int64_t min,int64_t max)38 clamp_int64(int64_t x, int64_t min, int64_t max)
39 {
40 if (x < min)
41 return min;
42 else if (x < max)
43 return x;
44 else
45 return max;
46 }
47
48 void
gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer * cmd_buffer)49 gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer)
50 {
51 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
52 uint32_t count = cmd_buffer->state.gfx.dynamic.scissor.count;
53 const VkRect2D *scissors = cmd_buffer->state.gfx.dynamic.scissor.scissors;
54
55 /* GEN:BUG:1409725701:
56 * "The viewport-specific state used by the SF unit (SCISSOR_RECT) is
57 * stored as an array of up to 16 elements. The location of first
58 * element of the array, as specified by Pointer to SCISSOR_RECT, should
59 * be aligned to a 64-byte boundary.
60 */
61 uint32_t alignment = 64;
62 struct anv_state scissor_state =
63 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, count * 8, alignment);
64
65 for (uint32_t i = 0; i < count; i++) {
66 const VkRect2D *s = &scissors[i];
67
68 /* Since xmax and ymax are inclusive, we have to have xmax < xmin or
69 * ymax < ymin for empty clips. In case clip x, y, width height are all
70 * 0, the clamps below produce 0 for xmin, ymin, xmax, ymax, which isn't
71 * what we want. Just special case empty clips and produce a canonical
72 * empty clip. */
73 static const struct GEN7_SCISSOR_RECT empty_scissor = {
74 .ScissorRectangleYMin = 1,
75 .ScissorRectangleXMin = 1,
76 .ScissorRectangleYMax = 0,
77 .ScissorRectangleXMax = 0
78 };
79
80 const int max = 0xffff;
81
82 uint32_t y_min = s->offset.y;
83 uint32_t x_min = s->offset.x;
84 uint32_t y_max = s->offset.y + s->extent.height - 1;
85 uint32_t x_max = s->offset.x + s->extent.width - 1;
86
87 /* Do this math using int64_t so overflow gets clamped correctly. */
88 if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) {
89 y_min = clamp_int64((uint64_t) y_min,
90 cmd_buffer->state.render_area.offset.y, max);
91 x_min = clamp_int64((uint64_t) x_min,
92 cmd_buffer->state.render_area.offset.x, max);
93 y_max = clamp_int64((uint64_t) y_max, 0,
94 cmd_buffer->state.render_area.offset.y +
95 cmd_buffer->state.render_area.extent.height - 1);
96 x_max = clamp_int64((uint64_t) x_max, 0,
97 cmd_buffer->state.render_area.offset.x +
98 cmd_buffer->state.render_area.extent.width - 1);
99 } else if (fb) {
100 y_min = clamp_int64((uint64_t) y_min, 0, max);
101 x_min = clamp_int64((uint64_t) x_min, 0, max);
102 y_max = clamp_int64((uint64_t) y_max, 0, fb->height - 1);
103 x_max = clamp_int64((uint64_t) x_max, 0, fb->width - 1);
104 }
105
106 struct GEN7_SCISSOR_RECT scissor = {
107 .ScissorRectangleYMin = y_min,
108 .ScissorRectangleXMin = x_min,
109 .ScissorRectangleYMax = y_max,
110 .ScissorRectangleXMax = x_max
111 };
112
113 if (s->extent.width <= 0 || s->extent.height <= 0) {
114 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8,
115 &empty_scissor);
116 } else {
117 GEN7_SCISSOR_RECT_pack(NULL, scissor_state.map + i * 8, &scissor);
118 }
119 }
120
121 anv_batch_emit(&cmd_buffer->batch,
122 GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
123 ssp.ScissorRectPointer = scissor_state.offset;
124 }
125 }
126 #endif
127
vk_to_gen_index_type(VkIndexType type)128 static uint32_t vk_to_gen_index_type(VkIndexType type)
129 {
130 switch (type) {
131 case VK_INDEX_TYPE_UINT8_EXT:
132 return INDEX_BYTE;
133 case VK_INDEX_TYPE_UINT16:
134 return INDEX_WORD;
135 case VK_INDEX_TYPE_UINT32:
136 return INDEX_DWORD;
137 default:
138 unreachable("invalid index type");
139 }
140 }
141
restart_index_for_type(VkIndexType type)142 static uint32_t restart_index_for_type(VkIndexType type)
143 {
144 switch (type) {
145 case VK_INDEX_TYPE_UINT8_EXT:
146 return UINT8_MAX;
147 case VK_INDEX_TYPE_UINT16:
148 return UINT16_MAX;
149 case VK_INDEX_TYPE_UINT32:
150 return UINT32_MAX;
151 default:
152 unreachable("invalid index type");
153 }
154 }
155
genX(CmdBindIndexBuffer)156 void genX(CmdBindIndexBuffer)(
157 VkCommandBuffer commandBuffer,
158 VkBuffer _buffer,
159 VkDeviceSize offset,
160 VkIndexType indexType)
161 {
162 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
163 ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
164
165 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
166 if (GEN_IS_HASWELL)
167 cmd_buffer->state.restart_index = restart_index_for_type(indexType);
168 cmd_buffer->state.gfx.gen7.index_buffer = buffer;
169 cmd_buffer->state.gfx.gen7.index_type = vk_to_gen_index_type(indexType);
170 cmd_buffer->state.gfx.gen7.index_offset = offset;
171 }
172
173 static uint32_t
get_depth_format(struct anv_cmd_buffer * cmd_buffer)174 get_depth_format(struct anv_cmd_buffer *cmd_buffer)
175 {
176 const struct anv_render_pass *pass = cmd_buffer->state.pass;
177 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
178
179 if (!subpass->depth_stencil_attachment)
180 return D16_UNORM;
181
182 struct anv_render_pass_attachment *att =
183 &pass->attachments[subpass->depth_stencil_attachment->attachment];
184
185 switch (att->format) {
186 case VK_FORMAT_D16_UNORM:
187 case VK_FORMAT_D16_UNORM_S8_UINT:
188 return D16_UNORM;
189
190 case VK_FORMAT_X8_D24_UNORM_PACK32:
191 case VK_FORMAT_D24_UNORM_S8_UINT:
192 return D24_UNORM_X8_UINT;
193
194 case VK_FORMAT_D32_SFLOAT:
195 case VK_FORMAT_D32_SFLOAT_S8_UINT:
196 return D32_FLOAT;
197
198 default:
199 return D16_UNORM;
200 }
201 }
202
203 void
genX(cmd_buffer_flush_dynamic_state)204 genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
205 {
206 struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
207 struct anv_dynamic_state *d = &cmd_buffer->state.gfx.dynamic;
208
209 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
210 ANV_CMD_DIRTY_RENDER_TARGETS |
211 ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH |
212 ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS |
213 ANV_CMD_DIRTY_DYNAMIC_CULL_MODE |
214 ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE)) {
215 uint32_t sf_dw[GENX(3DSTATE_SF_length)];
216 struct GENX(3DSTATE_SF) sf = {
217 GENX(3DSTATE_SF_header),
218 .DepthBufferSurfaceFormat = get_depth_format(cmd_buffer),
219 .LineWidth = d->line_width,
220 .GlobalDepthOffsetConstant = d->depth_bias.bias,
221 .GlobalDepthOffsetScale = d->depth_bias.slope,
222 .GlobalDepthOffsetClamp = d->depth_bias.clamp,
223 .FrontWinding = genX(vk_to_gen_front_face)[d->front_face],
224 .CullMode = genX(vk_to_gen_cullmode)[d->cull_mode],
225 };
226 GENX(3DSTATE_SF_pack)(NULL, sf_dw, &sf);
227
228 anv_batch_emit_merge(&cmd_buffer->batch, sf_dw, pipeline->gen7.sf);
229 }
230
231 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS |
232 ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE)) {
233 struct anv_state cc_state =
234 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
235 GENX(COLOR_CALC_STATE_length) * 4,
236 64);
237 struct GENX(COLOR_CALC_STATE) cc = {
238 .BlendConstantColorRed = d->blend_constants[0],
239 .BlendConstantColorGreen = d->blend_constants[1],
240 .BlendConstantColorBlue = d->blend_constants[2],
241 .BlendConstantColorAlpha = d->blend_constants[3],
242 .StencilReferenceValue = d->stencil_reference.front & 0xff,
243 .BackfaceStencilReferenceValue = d->stencil_reference.back & 0xff,
244 };
245 GENX(COLOR_CALC_STATE_pack)(NULL, cc_state.map, &cc);
246
247 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
248 ccp.ColorCalcStatePointer = cc_state.offset;
249 }
250 }
251
252 if (cmd_buffer->state.gfx.dirty & ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE) {
253 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_LINE_STIPPLE), ls) {
254 ls.LineStipplePattern = d->line_stipple.pattern;
255 ls.LineStippleInverseRepeatCount =
256 1.0f / MAX2(1, d->line_stipple.factor);
257 ls.LineStippleRepeatCount = d->line_stipple.factor;
258 }
259 }
260
261 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
262 ANV_CMD_DIRTY_RENDER_TARGETS |
263 ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK |
264 ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK |
265 ANV_CMD_DIRTY_DYNAMIC_DEPTH_TEST_ENABLE |
266 ANV_CMD_DIRTY_DYNAMIC_DEPTH_WRITE_ENABLE |
267 ANV_CMD_DIRTY_DYNAMIC_DEPTH_COMPARE_OP |
268 ANV_CMD_DIRTY_DYNAMIC_STENCIL_TEST_ENABLE |
269 ANV_CMD_DIRTY_DYNAMIC_STENCIL_OP)) {
270 uint32_t depth_stencil_dw[GENX(DEPTH_STENCIL_STATE_length)];
271
272 struct GENX(DEPTH_STENCIL_STATE) depth_stencil = {
273 .StencilTestMask = d->stencil_compare_mask.front & 0xff,
274 .StencilWriteMask = d->stencil_write_mask.front & 0xff,
275
276 .BackfaceStencilTestMask = d->stencil_compare_mask.back & 0xff,
277 .BackfaceStencilWriteMask = d->stencil_write_mask.back & 0xff,
278
279 .StencilBufferWriteEnable =
280 (d->stencil_write_mask.front || d->stencil_write_mask.back) &&
281 d->stencil_test_enable,
282
283 .DepthTestEnable = d->depth_test_enable,
284 .DepthBufferWriteEnable = d->depth_test_enable && d->depth_write_enable,
285 .DepthTestFunction = genX(vk_to_gen_compare_op)[d->depth_compare_op],
286 .StencilTestEnable = d->stencil_test_enable,
287 .StencilFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.fail_op],
288 .StencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.pass_op],
289 .StencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.front.depth_fail_op],
290 .StencilTestFunction = genX(vk_to_gen_compare_op)[d->stencil_op.front.compare_op],
291 .BackfaceStencilFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.fail_op],
292 .BackfaceStencilPassDepthPassOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.pass_op],
293 .BackfaceStencilPassDepthFailOp = genX(vk_to_gen_stencil_op)[d->stencil_op.back.depth_fail_op],
294 .BackfaceStencilTestFunction = genX(vk_to_gen_compare_op)[d->stencil_op.back.compare_op],
295 };
296 GENX(DEPTH_STENCIL_STATE_pack)(NULL, depth_stencil_dw, &depth_stencil);
297
298 struct anv_state ds_state =
299 anv_cmd_buffer_merge_dynamic(cmd_buffer, depth_stencil_dw,
300 pipeline->gen7.depth_stencil_state,
301 GENX(DEPTH_STENCIL_STATE_length), 64);
302
303 anv_batch_emit(&cmd_buffer->batch,
304 GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
305 dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
306 }
307 }
308
309 if (cmd_buffer->state.gfx.gen7.index_buffer &&
310 cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
311 ANV_CMD_DIRTY_INDEX_BUFFER)) {
312 struct anv_buffer *buffer = cmd_buffer->state.gfx.gen7.index_buffer;
313 uint32_t offset = cmd_buffer->state.gfx.gen7.index_offset;
314
315 #if GEN_IS_HASWELL
316 anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
317 vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
318 vf.CutIndex = cmd_buffer->state.restart_index;
319 }
320 #endif
321
322 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
323 #if !GEN_IS_HASWELL
324 ib.CutIndexEnable = pipeline->primitive_restart;
325 #endif
326 ib.IndexFormat = cmd_buffer->state.gfx.gen7.index_type;
327 ib.MOCS = anv_mocs(cmd_buffer->device,
328 buffer->address.bo,
329 ISL_SURF_USAGE_INDEX_BUFFER_BIT);
330
331 ib.BufferStartingAddress = anv_address_add(buffer->address, offset);
332 ib.BufferEndingAddress = anv_address_add(buffer->address,
333 buffer->size);
334 }
335 }
336
337 if (cmd_buffer->state.gfx.dirty & (ANV_CMD_DIRTY_PIPELINE |
338 ANV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY)) {
339 uint32_t topology;
340 if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
341 topology = d->primitive_topology;
342 else
343 topology = genX(vk_to_gen_primitive_type)[d->primitive_topology];
344
345 cmd_buffer->state.gfx.primitive_topology = topology;
346 }
347
348 cmd_buffer->state.gfx.dirty = 0;
349 }
350
351 void
genX(cmd_buffer_enable_pma_fix)352 genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer,
353 bool enable)
354 {
355 /* The NP PMA fix doesn't exist on gen7 */
356 }
357