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Searched refs:v8f16 (Results 1 – 25 of 62) sorted by relevance

123

/external/llvm/test/CodeGen/AArch64/
Dfp16-vector-load-store.ll53 ; Load to one lane of v8f16
72 ; Simple store of v8f16
91 ; Store from one lane of v8f16
108 declare { <8 x half>, <8 x half> } @llvm.aarch64.neon.ld2.v8f16.p0v8f16(<8 x half>*)
109 declare { <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld3.v8f16.p0v8f16(<8 x half>*)
110 declare { <8 x half>, <8 x half>, <8 x half>, <8 x half> } @llvm.aarch64.neon.ld4.v8f16.p0v8f16(<8 …
111 declare void @llvm.aarch64.neon.st2.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>*)
112 declare void @llvm.aarch64.neon.st3.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>*)
113 declare void @llvm.aarch64.neon.st4.v8f16.p0v8f16(<8 x half>, <8 x half>, <8 x half>, <8 x half>, <…
169 ; Load 2 x v8f16 with de-interleaving
[all …]
Dfp16-vector-nvcast.ll46 ; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src)))
57 ; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src)))
68 ; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src)))
79 ; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src)))
Darm64-aapcs.ll146 ; Check that v8f16 can be passed and returned in registers
160 ; Check that v8f16 can be passed and returned on the stack
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrMVE.td347 def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1, 0b01, "f", ?>;
1093 def : Pat<(v8f16 (fmaxnum (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))),
1094 (v8f16 (MVE_VMAXNMf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>;
1100 def : Pat<(v8f16 (int_arm_mve_max_predicated (v8f16 MQPR:$val1), (v8f16 MQPR:$val2), (i32 0),
1101 (v8i1 VCCR:$mask), (v8f16 MQPR:$inactive))),
1102 (v8f16 (MVE_VMAXNMf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2),
1104 (v8f16 MQPR:$inactive)))>;
1113 def : Pat<(v8f16 (fminnum (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))),
1114 (v8f16 (MVE_VMINNMf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>;
1120 def : Pat<(v8f16 (int_arm_mve_min_predicated (v8f16 MQPR:$val1), (v8f16 MQPR:$val2),
[all …]
DARMCallingConv.td34 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
60 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
95 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
112 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
169 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
186 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
212 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
234 CCIfType<[v2i64, v4i32, v8i16, v8f16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
DARMInstrNEON.td1084 def : Pat<(vector_insert (v8f16 QPR:$src),
1105 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
2153 def : Pat<(store (extractelt (v8f16 QPR:$src), imm:$lane), addrmode6:$addr),
3364 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3367 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8f16 QPR:$Vm), fc)))]>,
4263 v8f16, v8f16, fadd, 1>,
4326 v8f16, v8f16, fmul, 1>,
4334 def VMULslhq : N3VQSL16<0b01, 0b1001, "vmul", "f16", v8f16,
4357 def : Pat<(v8f16 (fmul (v8f16 QPR:$src1),
4358 (v8f16 (ARMvduplane (v8f16 QPR:$src2), imm:$lane)))),
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h109 v8f16 = 54, // 8 x f16 enumerator
251 SimpleTy == MVT::v1i128 || SimpleTy == MVT::v8f16 || in is128BitVector()
358 case v8f16: return f16; in getVectorElementType()
400 case v8f16: in getVectorNumElements()
487 case v8f16: in getSizeInBits()
646 if (NumElements == 8) return MVT::v8f16; in getVectorVT()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc10704 /* 22627*/ OPC_CheckChild0Type, MVT::v8f16,
10723 …1] } VCCR:{ *:[v8i1] }:$p1, (ARMvcmp:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, (ARMvdup:{ *:[v8f16] } H…
10724 …// Dst: (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[…
10738 …1] } VCCR:{ *:[v8i1] }:$p1, (ARMvcmp:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, (ARMvdup:{ *:[v8f16] } H…
10739 …// Dst: (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[…
10753 …1] } VCCR:{ *:[v8i1] }:$p1, (ARMvcmp:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, (ARMvdup:{ *:[v8f16] } H…
10754 …// Dst: (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[…
10768 …1] } VCCR:{ *:[v8i1] }:$p1, (ARMvcmp:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, (ARMvdup:{ *:[v8f16] } H…
10769 …// Dst: (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[…
10783 …1] } VCCR:{ *:[v8i1] }:$p1, (ARMvcmp:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, (ARMvdup:{ *:[v8f16] } H…
[all …]
DARMGenCallingConv.inc76 LocVT == MVT::v8f16 ||
246 LocVT == MVT::v8f16 ||
365 LocVT == MVT::v8f16 ||
432 LocVT == MVT::v8f16 ||
526 LocVT == MVT::v8f16 ||
614 LocVT == MVT::v8f16 ||
717 LocVT == MVT::v8f16 ||
831 LocVT == MVT::v8f16 ||
888 LocVT == MVT::v8f16 ||
DARMGenGlobalISel.inc7976 …// (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (REG_SEQUENCE:…
8785 // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src
8855 // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src
8929 …// (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16]…
9009 …// (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16]…
9113 // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src
9183 // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src
9265 …// (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[…
9365 …// (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[…
9813 // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src
[all …]
DARMGenFastISel.inc503 if (RetVT.SimpleTy != MVT::v8f16)
521 case MVT::v8f16: return fastEmit_ARMISD_VREV32_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
601 if (RetVT.SimpleTy != MVT::v8f16)
642 case MVT::v8f16: return fastEmit_ARMISD_VREV64_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
964 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(Op0, Op0IsKill);
1179 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4i32_MVT_v8f16_r(Op0, Op0IsKill);
1286 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2i64_MVT_v8f16_r(Op0, Op0IsKill);
1500 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v4f32_MVT_v8f16_r(Op0, Op0IsKill);
1561 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v2f64_MVT_v8f16_r(Op0, Op0IsKill);
1581 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp2753 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2780 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2807 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2834 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2861 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2888 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2915 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2942 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2969 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
2991 VT == MVT::v8f16) { in Select()
[all …]
DAArch64CallingConvention.td33 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
76 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
84 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
98 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
114 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
165 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
174 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
193 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
DAArch64InstrInfo.td1388 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1444 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1597 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1757 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2070 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2180 def : Pat<(store (v8f16 FPR128:$Rt),
2278 def : Pat<(store (v8f16 FPR128:$Rt),
2372 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2426 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2797 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp3191 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3218 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3245 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3272 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3299 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3326 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3353 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3380 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3407 } else if (VT == MVT::v8i16 || VT == MVT::v8f16) { in Select()
3429 VT == MVT::v8f16) { in Select()
[all …]
DAArch64CallingConvention.td38 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
112 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
120 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
137 CCIfBigEndian<CCIfType<[v2i64, v2f64, v4i32, v4f32, v8i16, v8f16, v16i8],
154 CCIfType<[f128, v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
229 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
244 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
265 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
287 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64, v8f16],
DAArch64InstrInfo.td805 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot90 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
806 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 0))>;
807 def : Pat<(v8f16 (int_aarch64_neon_vcadd_rot270 (v8f16 V128:$Rn), (v8f16 V128:$Rm))),
808 (FCADDv8f16 (v8f16 V128:$Rn), (v8f16 V128:$Rm), (i32 1))>;
2096 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
2152 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
2305 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
2488 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
2815 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2838 defm : VecROStoreLane0Pat<ro16, store, v8f16, f16, hsub, STRHroW, STRHroX>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DMachineValueType.h122 v8f16 = 67, // 8 x f16 enumerator
353 SimpleTy == MVT::v8f16 || SimpleTy == MVT::v4f32 || in is128BitVector()
511 case v8f16: in getVectorElementType()
603 case v8f16: in getVectorNumElements()
764 case v8f16: in getSizeInBits()
988 if (NumElements == 8) return MVT::v8f16; in getVectorVT()
/external/clang/test/CodeGen/
Dbuiltins-mips-msa.c13 typedef __fp16 v8f16 __attribute__ ((vector_size(16))); typedef
44 v8f16 v8f16_a = (v8f16) {0.5, 1, 2, 3, 4, 5, 6, 7}; in test()
45 v8f16 v8f16_b = (v8f16) {1.5, 2, 3, 4, 5, 6, 7, 8}; in test()
46 v8f16 v8f16_r; in test()
/external/llvm/test/CodeGen/Mips/msa/
Dbitcast.ll56 ; are no operations for v8f16 to put in the way.
230 ; are no operations for v8f16 to put in the way.
354 ; are no operations for v8f16 to put in the way.
378 ; are no operations for v8f16 to put in the way.
401 ; are no operations for v8f16 to put in the way.
403 ; are no operations for v8f16 to put in the way.
423 ; are no operations for v8f16 to put in the way.
447 ; are no operations for v8f16 to put in the way.
471 ; are no operations for v8f16 to put in the way.
495 ; are no operations for v8f16 to put in the way.
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc78 LocVT == MVT::v8f16 ||
331 LocVT == MVT::v8f16) {
378 LocVT == MVT::v8f16) {
574 LocVT == MVT::v8f16) {
638 LocVT == MVT::v8f16) {
722 LocVT == MVT::v8f16) {
804 LocVT == MVT::v8f16) {
1034 LocVT == MVT::v8f16 ||
1144 LocVT == MVT::v8f16) {
DAArch64GenFastISel.inc743 case MVT::v8f16: return fastEmit_AArch64ISD_FCMEQz_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
811 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGEz_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
879 case MVT::v8f16: return fastEmit_AArch64ISD_FCMGTz_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
947 case MVT::v8f16: return fastEmit_AArch64ISD_FCMLEz_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
1015 case MVT::v8f16: return fastEmit_AArch64ISD_FCMLTz_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
1443 if (RetVT.SimpleTy != MVT::v8f16)
1455 case MVT::v8f16: return fastEmit_AArch64ISD_REV32_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
1523 if (RetVT.SimpleTy != MVT::v8f16)
1549 case MVT::v8f16: return fastEmit_AArch64ISD_REV64_MVT_v8f16_r(RetVT, Op0, Op0IsKill);
2039 case MVT::v8f16: return fastEmit_ISD_BITCAST_MVT_v16i8_MVT_v8f16_r(Op0, Op0IsKill);
[all …]
DAArch64GenGlobalISel.inc8503 …// (concat_vectors:{ *:[v8f16] } V64:{ *:[v4f16] }:$Rd, V64:{ *:[v4f16] }:$Rn) => (INSvi64lane:{…
9952 // (bitconvert:{ *:[f128] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[f128] }:$src
10048 …8:{ *:[v8f16] }:$src) => (EXTv16i8:{ *:[f128] } (REV64v8i16:{ *:[f128] } FPR128:{ *:[v8f16] }:$s…
10574 // (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2f64] }:$src
10654 …// (bitconvert:{ *:[v2f64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2f64] } FPR128:{ *:…
10770 // (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v2i64] }:$src
10844 …// (bitconvert:{ *:[v2i64] } FPR128:{ *:[v8f16] }:$src) => (REV64v8i16:{ *:[v2i64] } FPR128:{ *:…
11454 // (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4f32] }:$src
11547 …// (bitconvert:{ *:[v4f32] } FPR128:{ *:[v8f16] }:$src) => (REV32v8i16:{ *:[v4f32] } FPR128:{ *:…
11674 // (bitconvert:{ *:[v4i32] } FPR128:{ *:[v8f16] }:$src) => FPR128:{ *:[v4i32] }:$src
[all …]
/external/llvm/lib/IR/
DValueTypes.cpp188 case MVT::v8f16: return "v8f16"; in getEVTString()
264 case MVT::v8f16: return VectorType::get(Type::getHalfTy(Context), 8); in getTypeForEVT()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td3280 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3283 [(set QPR:$Vd, (v8i16 (OpNode (v8f16 QPR:$Vm))))]>,
4126 v8f16, v8f16, fadd, 1>,
4187 v8f16, v8f16, fmul, 1>,
4195 def VMULslhq : N3VQSL16<0b01, 0b1001, "vmul", "f16", v8f16,
4310 v8f16, fmul_su, fadd_mlx>,
4324 v8f16, v4f16, fmul, fadd>,
4540 v8f16, fmul, fsub>,
4554 v8f16, v4f16, fmul, fsub>,
4628 v8f16, fmul, fadd>,
[all …]

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