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Searched refs:write_domain (Results 1 – 25 of 108) sorted by relevance

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/external/libdrm/radeon/
Dradeon_cs_space.c44 uint32_t read_domains, write_domain; in radeon_cs_setup_bo() local
50 write_domain = sc->write_domain; in radeon_cs_setup_bo()
54 bo->space_accounted = sc->new_accounted = (read_domains << 16) | write_domain; in radeon_cs_setup_bo()
59 if (write_domain && (write_domain == bo->space_accounted)) { in radeon_cs_setup_bo()
69 if (write_domain) { in radeon_cs_setup_bo()
70 if (write_domain == RADEON_GEM_DOMAIN_VRAM) in radeon_cs_setup_bo()
72 else if (write_domain == RADEON_GEM_DOMAIN_GTT) in radeon_cs_setup_bo()
74 sc->new_accounted = write_domain; in radeon_cs_setup_bo()
85 if (write_domain && (old_read & write_domain)) { in radeon_cs_setup_bo()
86 sc->new_accounted = write_domain; in radeon_cs_setup_bo()
[all …]
Dradeon_cs_gem.c65 uint32_t write_domain; member
175 uint32_t write_domain, in cs_gem_write_reloc() argument
187 if ((read_domain && write_domain) || (!read_domain && !write_domain)) { in cs_gem_write_reloc()
196 if (write_domain == RADEON_GEM_DOMAIN_CPU) { in cs_gem_write_reloc()
217 if (write_domain && (reloc->read_domain & write_domain)) { in cs_gem_write_reloc()
219 reloc->write_domain = write_domain; in cs_gem_write_reloc()
220 } else if (read_domain & reloc->write_domain) { in cs_gem_write_reloc()
223 if (write_domain != reloc->write_domain) in cs_gem_write_reloc()
230 reloc->write_domain |= write_domain; in cs_gem_write_reloc()
264 reloc->write_domain = write_domain; in cs_gem_write_reloc()
Dradeon_cs.h44 uint32_t write_domain; member
86 uint32_t write_domain,
99 uint32_t write_domain);
113 uint32_t write_domain);
Dradeon_cs_int.h8 uint32_t write_domain; member
41 uint32_t write_domain,
Dradeon_cs.c15 uint32_t read_domain, uint32_t write_domain, in radeon_cs_write_reloc() argument
23 write_domain, in radeon_cs_write_reloc()
/external/mesa3d/src/gallium/winsys/i915/drm/
Di915_drm_batchbuffer.c101 unsigned write_domain = 0; in i915_drm_batchbuffer_reloc() local
108 write_domain = 0; in i915_drm_batchbuffer_reloc()
112 write_domain = I915_GEM_DOMAIN_RENDER; in i915_drm_batchbuffer_reloc()
116 write_domain = I915_GEM_DOMAIN_RENDER; in i915_drm_batchbuffer_reloc()
120 write_domain = 0; in i915_drm_batchbuffer_reloc()
124 write_domain = 0; in i915_drm_batchbuffer_reloc()
138 write_domain); in i915_drm_batchbuffer_reloc()
143 write_domain); in i915_drm_batchbuffer_reloc()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_batchbuffer.h44 uint32_t write_domain,
49 uint32_t write_domain,
139 #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \ argument
141 read_domains, write_domain, delta); \
143 #define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do { \ argument
145 read_domains, write_domain, delta); \
Dintel_batchbuffer.c197 uint32_t read_domains, uint32_t write_domain, in intel_batchbuffer_emit_reloc() argument
204 read_domains, write_domain); in intel_batchbuffer_emit_reloc()
222 uint32_t write_domain, in intel_batchbuffer_emit_reloc_fenced() argument
229 read_domains, write_domain); in intel_batchbuffer_emit_reloc_fenced()
/external/igt-gpu-tools/lib/
Dgpu_cmds.c90 uint32_t write_domain, read_domain, offset; in gen7_fill_surface_state() local
94 write_domain = read_domain = I915_GEM_DOMAIN_RENDER; in gen7_fill_surface_state()
96 write_domain = 0; in gen7_fill_surface_state()
116 read_domain, write_domain); in gen7_fill_surface_state()
392 uint32_t write_domain, read_domain, offset; in gen8_fill_surface_state() local
396 write_domain = read_domain = I915_GEM_DOMAIN_RENDER; in gen8_fill_surface_state()
398 write_domain = 0; in gen8_fill_surface_state()
420 buf->bo, 0, read_domain, write_domain); in gen8_fill_surface_state()
445 uint32_t write_domain, read_domain, offset; in gen11_fill_surface_state() local
449 write_domain = read_domain = I915_GEM_DOMAIN_RENDER; in gen11_fill_surface_state()
[all …]
Dintel_batchbuffer.h51 uint32_t write_domain,
137 #define OUT_RELOC_FENCED(buf, read_domains, write_domain, delta) do { \ argument
140 read_domains, write_domain, 1); \
155 #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \ argument
158 read_domains, write_domain, 0); \
Drendercopy_gen6.c79 uint32_t write_domain, read_domain; in gen6_bind_buf() local
87 write_domain = read_domain = I915_GEM_DOMAIN_RENDER; in gen6_bind_buf()
89 write_domain = 0; in gen6_bind_buf()
111 read_domain, write_domain); in gen6_bind_buf()
Drendercopy_gen7.c65 uint32_t write_domain, read_domain; in gen7_bind_buf() local
81 write_domain = read_domain = I915_GEM_DOMAIN_RENDER; in gen7_bind_buf()
83 write_domain = 0; in gen7_bind_buf()
109 read_domain, write_domain); in gen7_bind_buf()
/external/igt-gpu-tools/tests/i915/
Dgem_reloc_overflow.c98 single_reloc.write_domain = I915_GEM_DOMAIN_RENDER; in source_offset_tests()
112 single_reloc.write_domain = I915_GEM_DOMAIN_RENDER; in source_offset_tests()
123 single_reloc.write_domain = I915_GEM_DOMAIN_RENDER; in source_offset_tests()
135 single_reloc.write_domain = I915_GEM_DOMAIN_RENDER; in source_offset_tests()
145 single_reloc.write_domain = I915_GEM_DOMAIN_RENDER; in source_offset_tests()
155 single_reloc.write_domain = I915_GEM_DOMAIN_RENDER; in source_offset_tests()
165 single_reloc.write_domain = I915_GEM_DOMAIN_RENDER; in source_offset_tests()
421 reloc[i].write_domain = 0;
Dgem_exec_faulting_reloc.c86 reloc->write_domain = I915_GEM_DOMAIN_RENDER; in gem_linear_blt()
104 reloc->write_domain = 0; in gem_linear_blt()
130 reloc->write_domain = I915_GEM_DOMAIN_RENDER; in gem_linear_blt()
147 reloc->write_domain = 0; in gem_linear_blt()
Dgem_exec_blt.c79 reloc->write_domain = I915_GEM_DOMAIN_RENDER; in gem_linear_blt()
94 reloc->write_domain = 0; in gem_linear_blt()
117 reloc->write_domain = I915_GEM_DOMAIN_RENDER; in gem_linear_blt()
132 reloc->write_domain = 0; in gem_linear_blt()
Dgem_exec_store.c69 reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION; in store_dword()
139 reloc[n].write_domain = I915_GEM_DOMAIN_INSTRUCTION; in store_cachelines()
238 reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; in store_all()
253 reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; in store_all()
Di915_module_load.c78 reloc.write_domain = I915_GEM_DOMAIN_INSTRUCTION; in store_dword()
169 reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; in store_all()
184 reloc[j].write_domain = I915_GEM_DOMAIN_INSTRUCTION; in store_all()
Dgem_streaming_writes.c121 reloc[2*i+0].write_domain = I915_GEM_DOMAIN_RENDER; in test_streaming()
130 reloc[2*i+1].write_domain = 0; in test_streaming()
262 reloc[0].write_domain = I915_GEM_DOMAIN_RENDER; in test_batch()
271 reloc[1].write_domain = 0; in test_batch()
Dgem_close_race.c78 reloc[0].write_domain = I915_GEM_DOMAIN_RENDER; in selfcopy()
89 reloc[1].write_domain = 0; in selfcopy()
/external/libdrm/intel/
Dintel_bufmgr.c201 uint32_t read_domains, uint32_t write_domain) in drm_intel_bo_emit_reloc() argument
205 read_domains, write_domain); in drm_intel_bo_emit_reloc()
212 uint32_t read_domains, uint32_t write_domain) in drm_intel_bo_emit_reloc_fence() argument
216 read_domains, write_domain); in drm_intel_bo_emit_reloc_fence()
Dintel_bufmgr_priv.h190 uint32_t read_domains, uint32_t write_domain);
195 uint32_t write_domain);
Dintel_bufmgr_fake.c85 uint32_t write_domain; member
202 uint32_t write_domain; member
1252 uint32_t read_domains, uint32_t write_domain) in drm_intel_fake_emit_reloc() argument
1287 r->write_domain = write_domain; in drm_intel_fake_emit_reloc()
1324 target_fake->write_domain |= r->write_domain; in drm_intel_fake_calculate_domains()
1372 if (bo_fake->write_domain != 0) { in drm_intel_fake_reloc_and_validate_buffer()
1409 bo_fake->write_domain = 0; in drm_intel_bo_fake_post_submit()
/external/igt-gpu-tools/benchmarks/
Dgem_blt.c113 reloc->write_domain = I915_GEM_DOMAIN_RENDER; in gem_linear_blt()
128 reloc->write_domain = 0; in gem_linear_blt()
151 reloc->write_domain = I915_GEM_DOMAIN_RENDER; in gem_linear_blt()
166 reloc->write_domain = 0; in gem_linear_blt()
Dgem_busy.c245 reloc[0].write_domain = 0; in loop()
252 reloc[1].write_domain = 0; in loop()
254 reloc[1].write_domain = I915_GEM_DOMAIN_RENDER; in loop()
/external/igt-gpu-tools/tools/null_state_gen/
Dintel_batchbuffer.h77 #define OUT_RELOC(batch, read_domain, write_domain, d) bb_area_emit(batch->cmds, d, RELOC, #d) argument
78 #define OUT_RELOC_STATE(batch, read_domain, write_domain, d) bb_area_emit(batch->cmds, d, RELOC_STA… argument

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