Searched refs:WriteIMul (Results 1 – 13 of 13) sorted by relevance
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoM.td | 28 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
30 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
32 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
34 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
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| D | RISCVSchedRocket64.td | 58 def : WriteRes<WriteIMul, [Rocket64UnitIMul]>;
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| D | RISCVSchedule.td | 16 def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply
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| D | RISCVSchedRocket32.td | 58 def : WriteRes<WriteIMul, [Rocket32UnitIMul]> { let Latency = 4; }
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrArithmetic.td | 66 (implicit EFLAGS)], IIC_MUL8>, Sched<[WriteIMul]>;
71 [], IIC_MUL16_REG>, OpSize16, Sched<[WriteIMul]>;
77 IIC_MUL32_REG>, OpSize32, Sched<[WriteIMul]>;
83 IIC_MUL64>, Sched<[WriteIMul]>;
114 IIC_IMUL8>, Sched<[WriteIMul]>;
118 IIC_IMUL16_RR>, OpSize16, Sched<[WriteIMul]>;
122 IIC_IMUL32_RR>, OpSize32, Sched<[WriteIMul]>;
126 IIC_IMUL64_RR>, Sched<[WriteIMul]>;
154 let isCommutable = 1, SchedRW = [WriteIMul] in {
205 let SchedRW = [WriteIMul] in {
[all …]
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| D | X86ScheduleSLM.td | 82 defm : SMWriteResPair<WriteIMul, IEC_RSV1, 3>;
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| D | X86SchedSandyBridge.td | 95 defm : SBWriteResPair<WriteIMul, SBPort1, 3>;
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| D | X86ScheduleBtVer2.td | 111 defm : JWriteResIntPair<WriteIMul, JALU1, 3>;
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| D | X86Schedule.td | 44 defm WriteIMul : X86SchedWritePair; // Integer multiplication.
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| D | X86SchedHaswell.td | 107 defm : HWWriteResPair<WriteIMul, HWPort1, 3>;
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| /external/angle/src/common/spirv/ |
| D | spirv_instruction_builder_autogen.h | 353 void WriteIMul(Blob *blob,
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| D | spirv_instruction_builder_autogen.cpp | 1404 void WriteIMul(Blob *blob, in WriteIMul() function
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| /external/angle/src/compiler/translator/spirv/ |
| D | OutputSPIRV.cpp | 2414 writeBinaryOp = spirv::WriteIMul; in visitOperator()
2509 writeBinaryOp = spirv::WriteIMul; in visitOperator()
2802 writeBinaryOp = spirv::WriteIMul; in visitOperator()
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