| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 69 M(smuad) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 68 M(smuad) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 693 0x13,0xf4,0x02,0xe7 = smuad r2, r3, r4
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3201 void smuad(Condition cond, Register rd, Register rn, Register rm);
3202 void smuad(Register rd, Register rn, Register rm) { smuad(al, rd, rn, rm); } in smuad() function
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| D | disasm-aarch32.h | 1161 void smuad(Condition cond, Register rd, Register rn, Register rm);
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| D | disasm-aarch32.cc | 2754 void Disassembler::smuad(Condition cond, in smuad() function in vixl::aarch32::Disassembler
21887 smuad(CurrentCond(), in DecodeT32()
63762 smuad(condition, Register(rd), Register(rn), Register(rm)); in DecodeA32()
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| D | assembler-aarch32.cc | 10518 void Assembler::smuad(Condition cond, Register rd, Register rn, Register rm) { in smuad() function in vixl::aarch32::Assembler
10538 Delegate(kSmuad, &Assembler::smuad, cond, rd, rn, rm); in smuad()
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| D | macro-assembler-aarch32.h | 3954 smuad(cond, rd, rn, rm); in Smuad()
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2451 smuad r2, r3, r4
2457 @ CHECK: smuad r2, r3, r4 @ encoding: [0x23,0xfb,0x04,0xf2]
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| D | basic-arm-instructions.s | 2533 smuad r2, r3, r4
2538 @ CHECK: smuad r2, r3, r4 @ encoding: [0x13,0xf4,0x02,0xe7]
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 1741 # CHECK: smuad r2, r3, r4
|
| /external/capstone/arch/ARM/ |
| D | ARMMappingInsnOp.inc | 814 { /* ARM_SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */
6040 { /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */
|
| /external/capstone/arch/AArch64/ |
| D | ARMMappingInsnOp.inc | 814 { /* ARM_SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */
6040 { /* ARM_t2SMUAD, ARM_INS_SMUAD: smuad${p} $rd, $rn, $rm */
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2852 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3074 def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad", int_arm_smuad>;
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 9904 "\006smmlsr\005smmul\006smmulr\005smuad\006smuadx\006smulbb\006smulbt\005"
11156 …{ 1280 /* smuad */, ARM::t2SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsThumb2_Has…
11157 …{ 1280 /* smuad */, ARM::SMUAD, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, AMFBS_IsARM_HasV6, {…
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/ |
| D | IntrinsicImpl.inc | 1848 "llvm.arm.smuad",
11981 1, // llvm.arm.smuad
|