1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_I915_DRM_H_ 20 #define _UAPI_I915_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" 26 #define I915_ERROR_UEVENT "ERROR" 27 #define I915_RESET_UEVENT "RESET" 28 struct i915_user_extension { 29 __u64 next_extension; 30 __u32 name; 31 __u32 flags; 32 __u32 rsvd[4]; 33 }; 34 enum i915_mocs_table_index { 35 I915_MOCS_UNCACHED, 36 I915_MOCS_PTE, 37 I915_MOCS_CACHED, 38 }; 39 enum drm_i915_gem_engine_class { 40 I915_ENGINE_CLASS_RENDER = 0, 41 I915_ENGINE_CLASS_COPY = 1, 42 I915_ENGINE_CLASS_VIDEO = 2, 43 I915_ENGINE_CLASS_VIDEO_ENHANCE = 3, 44 I915_ENGINE_CLASS_COMPUTE = 4, 45 I915_ENGINE_CLASS_INVALID = - 1 46 }; 47 struct i915_engine_class_instance { 48 __u16 engine_class; 49 #define I915_ENGINE_CLASS_INVALID_NONE - 1 50 #define I915_ENGINE_CLASS_INVALID_VIRTUAL - 2 51 __u16 engine_instance; 52 }; 53 enum drm_i915_pmu_engine_sample { 54 I915_SAMPLE_BUSY = 0, 55 I915_SAMPLE_WAIT = 1, 56 I915_SAMPLE_SEMA = 2 57 }; 58 #define I915_PMU_SAMPLE_BITS (4) 59 #define I915_PMU_SAMPLE_MASK (0xf) 60 #define I915_PMU_SAMPLE_INSTANCE_BITS (8) 61 #define I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS) 62 #define __I915_PMU_ENGINE(class,instance,sample) ((class) << I915_PMU_CLASS_SHIFT | (instance) << I915_PMU_SAMPLE_BITS | (sample)) 63 #define I915_PMU_ENGINE_BUSY(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY) 64 #define I915_PMU_ENGINE_WAIT(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT) 65 #define I915_PMU_ENGINE_SEMA(class,instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) 66 #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) 67 #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0) 68 #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1) 69 #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2) 70 #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3) 71 #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4) 72 #define I915_PMU_LAST I915_PMU_RC6_RESIDENCY 73 #define I915_NR_TEX_REGIONS 255 74 #define I915_LOG_MIN_TEX_REGION_SIZE 14 75 typedef struct _drm_i915_init { 76 enum { 77 I915_INIT_DMA = 0x01, 78 I915_CLEANUP_DMA = 0x02, 79 I915_RESUME_DMA = 0x03 80 } func; 81 unsigned int mmio_offset; 82 int sarea_priv_offset; 83 unsigned int ring_start; 84 unsigned int ring_end; 85 unsigned int ring_size; 86 unsigned int front_offset; 87 unsigned int back_offset; 88 unsigned int depth_offset; 89 unsigned int w; 90 unsigned int h; 91 unsigned int pitch; 92 unsigned int pitch_bits; 93 unsigned int back_pitch; 94 unsigned int depth_pitch; 95 unsigned int cpp; 96 unsigned int chipset; 97 } drm_i915_init_t; 98 typedef struct _drm_i915_sarea { 99 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; 100 int last_upload; 101 int last_enqueue; 102 int last_dispatch; 103 int ctxOwner; 104 int texAge; 105 int pf_enabled; 106 int pf_active; 107 int pf_current_page; 108 int perf_boxes; 109 int width, height; 110 drm_handle_t front_handle; 111 int front_offset; 112 int front_size; 113 drm_handle_t back_handle; 114 int back_offset; 115 int back_size; 116 drm_handle_t depth_handle; 117 int depth_offset; 118 int depth_size; 119 drm_handle_t tex_handle; 120 int tex_offset; 121 int tex_size; 122 int log_tex_granularity; 123 int pitch; 124 int rotation; 125 int rotated_offset; 126 int rotated_size; 127 int rotated_pitch; 128 int virtualX, virtualY; 129 unsigned int front_tiled; 130 unsigned int back_tiled; 131 unsigned int depth_tiled; 132 unsigned int rotated_tiled; 133 unsigned int rotated2_tiled; 134 int pipeA_x; 135 int pipeA_y; 136 int pipeA_w; 137 int pipeA_h; 138 int pipeB_x; 139 int pipeB_y; 140 int pipeB_w; 141 int pipeB_h; 142 drm_handle_t unused_handle; 143 __u32 unused1, unused2, unused3; 144 __u32 front_bo_handle; 145 __u32 back_bo_handle; 146 __u32 unused_bo_handle; 147 __u32 depth_bo_handle; 148 } drm_i915_sarea_t; 149 #define planeA_x pipeA_x 150 #define planeA_y pipeA_y 151 #define planeA_w pipeA_w 152 #define planeA_h pipeA_h 153 #define planeB_x pipeB_x 154 #define planeB_y pipeB_y 155 #define planeB_w pipeB_w 156 #define planeB_h pipeB_h 157 #define I915_BOX_RING_EMPTY 0x1 158 #define I915_BOX_FLIP 0x2 159 #define I915_BOX_WAIT 0x4 160 #define I915_BOX_TEXTURE_LOAD 0x8 161 #define I915_BOX_LOST_CONTEXT 0x10 162 #define DRM_I915_INIT 0x00 163 #define DRM_I915_FLUSH 0x01 164 #define DRM_I915_FLIP 0x02 165 #define DRM_I915_BATCHBUFFER 0x03 166 #define DRM_I915_IRQ_EMIT 0x04 167 #define DRM_I915_IRQ_WAIT 0x05 168 #define DRM_I915_GETPARAM 0x06 169 #define DRM_I915_SETPARAM 0x07 170 #define DRM_I915_ALLOC 0x08 171 #define DRM_I915_FREE 0x09 172 #define DRM_I915_INIT_HEAP 0x0a 173 #define DRM_I915_CMDBUFFER 0x0b 174 #define DRM_I915_DESTROY_HEAP 0x0c 175 #define DRM_I915_SET_VBLANK_PIPE 0x0d 176 #define DRM_I915_GET_VBLANK_PIPE 0x0e 177 #define DRM_I915_VBLANK_SWAP 0x0f 178 #define DRM_I915_HWS_ADDR 0x11 179 #define DRM_I915_GEM_INIT 0x13 180 #define DRM_I915_GEM_EXECBUFFER 0x14 181 #define DRM_I915_GEM_PIN 0x15 182 #define DRM_I915_GEM_UNPIN 0x16 183 #define DRM_I915_GEM_BUSY 0x17 184 #define DRM_I915_GEM_THROTTLE 0x18 185 #define DRM_I915_GEM_ENTERVT 0x19 186 #define DRM_I915_GEM_LEAVEVT 0x1a 187 #define DRM_I915_GEM_CREATE 0x1b 188 #define DRM_I915_GEM_PREAD 0x1c 189 #define DRM_I915_GEM_PWRITE 0x1d 190 #define DRM_I915_GEM_MMAP 0x1e 191 #define DRM_I915_GEM_SET_DOMAIN 0x1f 192 #define DRM_I915_GEM_SW_FINISH 0x20 193 #define DRM_I915_GEM_SET_TILING 0x21 194 #define DRM_I915_GEM_GET_TILING 0x22 195 #define DRM_I915_GEM_GET_APERTURE 0x23 196 #define DRM_I915_GEM_MMAP_GTT 0x24 197 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 198 #define DRM_I915_GEM_MADVISE 0x26 199 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 200 #define DRM_I915_OVERLAY_ATTRS 0x28 201 #define DRM_I915_GEM_EXECBUFFER2 0x29 202 #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2 203 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a 204 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b 205 #define DRM_I915_GEM_WAIT 0x2c 206 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d 207 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e 208 #define DRM_I915_GEM_SET_CACHING 0x2f 209 #define DRM_I915_GEM_GET_CACHING 0x30 210 #define DRM_I915_REG_READ 0x31 211 #define DRM_I915_GET_RESET_STATS 0x32 212 #define DRM_I915_GEM_USERPTR 0x33 213 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 214 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 215 #define DRM_I915_PERF_OPEN 0x36 216 #define DRM_I915_PERF_ADD_CONFIG 0x37 217 #define DRM_I915_PERF_REMOVE_CONFIG 0x38 218 #define DRM_I915_QUERY 0x39 219 #define DRM_I915_GEM_VM_CREATE 0x3a 220 #define DRM_I915_GEM_VM_DESTROY 0x3b 221 #define DRM_I915_GEM_CREATE_EXT 0x3c 222 #define DRM_IOCTL_I915_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 223 #define DRM_IOCTL_I915_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLUSH) 224 #define DRM_IOCTL_I915_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I915_FLIP) 225 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) 226 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) 227 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) 228 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) 229 #define DRM_IOCTL_I915_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) 230 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) 231 #define DRM_IOCTL_I915_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) 232 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) 233 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) 234 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) 235 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 236 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) 237 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) 238 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) 239 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) 240 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) 241 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) 242 #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2) 243 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) 244 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) 245 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) 246 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) 247 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) 248 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) 249 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) 250 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) 251 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) 252 #define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext) 253 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) 254 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) 255 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) 256 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) 257 #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset) 258 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) 259 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) 260 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) 261 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) 262 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) 263 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) 264 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) 265 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) 266 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) 267 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 268 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) 269 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) 270 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 271 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext) 272 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 273 #define DRM_IOCTL_I915_REG_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 274 #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) 275 #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) 276 #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) 277 #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) 278 #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) 279 #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config) 280 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64) 281 #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query) 282 #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control) 283 #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control) 284 typedef struct drm_i915_batchbuffer { 285 int start; 286 int used; 287 int DR1; 288 int DR4; 289 int num_cliprects; 290 struct drm_clip_rect * cliprects; 291 } drm_i915_batchbuffer_t; 292 typedef struct _drm_i915_cmdbuffer { 293 char * buf; 294 int sz; 295 int DR1; 296 int DR4; 297 int num_cliprects; 298 struct drm_clip_rect * cliprects; 299 } drm_i915_cmdbuffer_t; 300 typedef struct drm_i915_irq_emit { 301 int * irq_seq; 302 } drm_i915_irq_emit_t; 303 typedef struct drm_i915_irq_wait { 304 int irq_seq; 305 } drm_i915_irq_wait_t; 306 #define I915_GEM_PPGTT_NONE 0 307 #define I915_GEM_PPGTT_ALIASING 1 308 #define I915_GEM_PPGTT_FULL 2 309 #define I915_PARAM_IRQ_ACTIVE 1 310 #define I915_PARAM_ALLOW_BATCHBUFFER 2 311 #define I915_PARAM_LAST_DISPATCH 3 312 #define I915_PARAM_CHIPSET_ID 4 313 #define I915_PARAM_HAS_GEM 5 314 #define I915_PARAM_NUM_FENCES_AVAIL 6 315 #define I915_PARAM_HAS_OVERLAY 7 316 #define I915_PARAM_HAS_PAGEFLIPPING 8 317 #define I915_PARAM_HAS_EXECBUF2 9 318 #define I915_PARAM_HAS_BSD 10 319 #define I915_PARAM_HAS_BLT 11 320 #define I915_PARAM_HAS_RELAXED_FENCING 12 321 #define I915_PARAM_HAS_COHERENT_RINGS 13 322 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 323 #define I915_PARAM_HAS_RELAXED_DELTA 15 324 #define I915_PARAM_HAS_GEN7_SOL_RESET 16 325 #define I915_PARAM_HAS_LLC 17 326 #define I915_PARAM_HAS_ALIASING_PPGTT 18 327 #define I915_PARAM_HAS_WAIT_TIMEOUT 19 328 #define I915_PARAM_HAS_SEMAPHORES 20 329 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 330 #define I915_PARAM_HAS_VEBOX 22 331 #define I915_PARAM_HAS_SECURE_BATCHES 23 332 #define I915_PARAM_HAS_PINNED_BATCHES 24 333 #define I915_PARAM_HAS_EXEC_NO_RELOC 25 334 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 335 #define I915_PARAM_HAS_WT 27 336 #define I915_PARAM_CMD_PARSER_VERSION 28 337 #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 338 #define I915_PARAM_MMAP_VERSION 30 339 #define I915_PARAM_HAS_BSD2 31 340 #define I915_PARAM_REVISION 32 341 #define I915_PARAM_SUBSLICE_TOTAL 33 342 #define I915_PARAM_EU_TOTAL 34 343 #define I915_PARAM_HAS_GPU_RESET 35 344 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 345 #define I915_PARAM_HAS_EXEC_SOFTPIN 37 346 #define I915_PARAM_HAS_POOLED_EU 38 347 #define I915_PARAM_MIN_EU_IN_POOL 39 348 #define I915_PARAM_MMAP_GTT_VERSION 40 349 #define I915_PARAM_HAS_SCHEDULER 41 350 #define I915_SCHEDULER_CAP_ENABLED (1ul << 0) 351 #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) 352 #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2) 353 #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3) 354 #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4) 355 #define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5) 356 #define I915_PARAM_HUC_STATUS 42 357 #define I915_PARAM_HAS_EXEC_ASYNC 43 358 #define I915_PARAM_HAS_EXEC_FENCE 44 359 #define I915_PARAM_HAS_EXEC_CAPTURE 45 360 #define I915_PARAM_SLICE_MASK 46 361 #define I915_PARAM_SUBSLICE_MASK 47 362 #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48 363 #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49 364 #define I915_PARAM_HAS_CONTEXT_ISOLATION 50 365 #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51 366 #define I915_PARAM_MMAP_GTT_COHERENT 52 367 #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53 368 #define I915_PARAM_PERF_REVISION 54 369 #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55 370 #define I915_PARAM_HAS_USERPTR_PROBE 56 371 #define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57 372 struct drm_i915_getparam { 373 __s32 param; 374 int * value; 375 }; 376 typedef struct drm_i915_getparam drm_i915_getparam_t; 377 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 378 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 379 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 380 #define I915_SETPARAM_NUM_USED_FENCES 4 381 typedef struct drm_i915_setparam { 382 int param; 383 int value; 384 } drm_i915_setparam_t; 385 #define I915_MEM_REGION_AGP 1 386 typedef struct drm_i915_mem_alloc { 387 int region; 388 int alignment; 389 int size; 390 int * region_offset; 391 } drm_i915_mem_alloc_t; 392 typedef struct drm_i915_mem_free { 393 int region; 394 int region_offset; 395 } drm_i915_mem_free_t; 396 typedef struct drm_i915_mem_init_heap { 397 int region; 398 int size; 399 int start; 400 } drm_i915_mem_init_heap_t; 401 typedef struct drm_i915_mem_destroy_heap { 402 int region; 403 } drm_i915_mem_destroy_heap_t; 404 #define DRM_I915_VBLANK_PIPE_A 1 405 #define DRM_I915_VBLANK_PIPE_B 2 406 typedef struct drm_i915_vblank_pipe { 407 int pipe; 408 } drm_i915_vblank_pipe_t; 409 typedef struct drm_i915_vblank_swap { 410 drm_drawable_t drawable; 411 enum drm_vblank_seq_type seqtype; 412 unsigned int sequence; 413 } drm_i915_vblank_swap_t; 414 typedef struct drm_i915_hws_addr { 415 __u64 addr; 416 } drm_i915_hws_addr_t; 417 struct drm_i915_gem_init { 418 __u64 gtt_start; 419 __u64 gtt_end; 420 }; 421 struct drm_i915_gem_create { 422 __u64 size; 423 __u32 handle; 424 __u32 pad; 425 }; 426 struct drm_i915_gem_pread { 427 __u32 handle; 428 __u32 pad; 429 __u64 offset; 430 __u64 size; 431 __u64 data_ptr; 432 }; 433 struct drm_i915_gem_pwrite { 434 __u32 handle; 435 __u32 pad; 436 __u64 offset; 437 __u64 size; 438 __u64 data_ptr; 439 }; 440 struct drm_i915_gem_mmap { 441 __u32 handle; 442 __u32 pad; 443 __u64 offset; 444 __u64 size; 445 __u64 addr_ptr; 446 __u64 flags; 447 #define I915_MMAP_WC 0x1 448 }; 449 struct drm_i915_gem_mmap_gtt { 450 __u32 handle; 451 __u32 pad; 452 __u64 offset; 453 }; 454 struct drm_i915_gem_mmap_offset { 455 __u32 handle; 456 __u32 pad; 457 __u64 offset; 458 __u64 flags; 459 #define I915_MMAP_OFFSET_GTT 0 460 #define I915_MMAP_OFFSET_WC 1 461 #define I915_MMAP_OFFSET_WB 2 462 #define I915_MMAP_OFFSET_UC 3 463 #define I915_MMAP_OFFSET_FIXED 4 464 __u64 extensions; 465 }; 466 struct drm_i915_gem_set_domain { 467 __u32 handle; 468 __u32 read_domains; 469 __u32 write_domain; 470 }; 471 struct drm_i915_gem_sw_finish { 472 __u32 handle; 473 }; 474 struct drm_i915_gem_relocation_entry { 475 __u32 target_handle; 476 __u32 delta; 477 __u64 offset; 478 __u64 presumed_offset; 479 __u32 read_domains; 480 __u32 write_domain; 481 }; 482 #define I915_GEM_DOMAIN_CPU 0x00000001 483 #define I915_GEM_DOMAIN_RENDER 0x00000002 484 #define I915_GEM_DOMAIN_SAMPLER 0x00000004 485 #define I915_GEM_DOMAIN_COMMAND 0x00000008 486 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 487 #define I915_GEM_DOMAIN_VERTEX 0x00000020 488 #define I915_GEM_DOMAIN_GTT 0x00000040 489 #define I915_GEM_DOMAIN_WC 0x00000080 490 struct drm_i915_gem_exec_object { 491 __u32 handle; 492 __u32 relocation_count; 493 __u64 relocs_ptr; 494 __u64 alignment; 495 __u64 offset; 496 }; 497 struct drm_i915_gem_execbuffer { 498 __u64 buffers_ptr; 499 __u32 buffer_count; 500 __u32 batch_start_offset; 501 __u32 batch_len; 502 __u32 DR1; 503 __u32 DR4; 504 __u32 num_cliprects; 505 __u64 cliprects_ptr; 506 }; 507 struct drm_i915_gem_exec_object2 { 508 __u32 handle; 509 __u32 relocation_count; 510 __u64 relocs_ptr; 511 __u64 alignment; 512 __u64 offset; 513 #define EXEC_OBJECT_NEEDS_FENCE (1 << 0) 514 #define EXEC_OBJECT_NEEDS_GTT (1 << 1) 515 #define EXEC_OBJECT_WRITE (1 << 2) 516 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1 << 3) 517 #define EXEC_OBJECT_PINNED (1 << 4) 518 #define EXEC_OBJECT_PAD_TO_SIZE (1 << 5) 519 #define EXEC_OBJECT_ASYNC (1 << 6) 520 #define EXEC_OBJECT_CAPTURE (1 << 7) 521 #define __EXEC_OBJECT_UNKNOWN_FLAGS - (EXEC_OBJECT_CAPTURE << 1) 522 __u64 flags; 523 union { 524 __u64 rsvd1; 525 __u64 pad_to_size; 526 }; 527 __u64 rsvd2; 528 }; 529 struct drm_i915_gem_exec_fence { 530 __u32 handle; 531 __u32 flags; 532 #define I915_EXEC_FENCE_WAIT (1 << 0) 533 #define I915_EXEC_FENCE_SIGNAL (1 << 1) 534 #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (- (I915_EXEC_FENCE_SIGNAL << 1)) 535 }; 536 struct drm_i915_gem_execbuffer_ext_timeline_fences { 537 #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0 538 struct i915_user_extension base; 539 __u64 fence_count; 540 __u64 handles_ptr; 541 __u64 values_ptr; 542 }; 543 struct drm_i915_gem_execbuffer2 { 544 __u64 buffers_ptr; 545 __u32 buffer_count; 546 __u32 batch_start_offset; 547 __u32 batch_len; 548 __u32 DR1; 549 __u32 DR4; 550 __u32 num_cliprects; 551 __u64 cliprects_ptr; 552 __u64 flags; 553 #define I915_EXEC_RING_MASK (0x3f) 554 #define I915_EXEC_DEFAULT (0 << 0) 555 #define I915_EXEC_RENDER (1 << 0) 556 #define I915_EXEC_BSD (2 << 0) 557 #define I915_EXEC_BLT (3 << 0) 558 #define I915_EXEC_VEBOX (4 << 0) 559 #define I915_EXEC_CONSTANTS_MASK (3 << 6) 560 #define I915_EXEC_CONSTANTS_REL_GENERAL (0 << 6) 561 #define I915_EXEC_CONSTANTS_ABSOLUTE (1 << 6) 562 #define I915_EXEC_CONSTANTS_REL_SURFACE (2 << 6) 563 #define I915_EXEC_GEN7_SOL_RESET (1 << 8) 564 #define I915_EXEC_SECURE (1 << 9) 565 #define I915_EXEC_IS_PINNED (1 << 10) 566 #define I915_EXEC_NO_RELOC (1 << 11) 567 #define I915_EXEC_HANDLE_LUT (1 << 12) 568 #define I915_EXEC_BSD_SHIFT (13) 569 #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) 570 #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) 571 #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) 572 #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) 573 #define I915_EXEC_RESOURCE_STREAMER (1 << 15) 574 #define I915_EXEC_FENCE_IN (1 << 16) 575 #define I915_EXEC_FENCE_OUT (1 << 17) 576 #define I915_EXEC_BATCH_FIRST (1 << 18) 577 #define I915_EXEC_FENCE_ARRAY (1 << 19) 578 #define I915_EXEC_FENCE_SUBMIT (1 << 20) 579 #define I915_EXEC_USE_EXTENSIONS (1 << 21) 580 #define __I915_EXEC_UNKNOWN_FLAGS (- (I915_EXEC_USE_EXTENSIONS << 1)) 581 __u64 rsvd1; 582 __u64 rsvd2; 583 }; 584 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) 585 #define i915_execbuffer2_set_context_id(eb2,context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK 586 #define i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) 587 struct drm_i915_gem_pin { 588 __u32 handle; 589 __u32 pad; 590 __u64 alignment; 591 __u64 offset; 592 }; 593 struct drm_i915_gem_unpin { 594 __u32 handle; 595 __u32 pad; 596 }; 597 struct drm_i915_gem_busy { 598 __u32 handle; 599 __u32 busy; 600 }; 601 struct drm_i915_gem_caching { 602 __u32 handle; 603 #define I915_CACHING_NONE 0 604 #define I915_CACHING_CACHED 1 605 #define I915_CACHING_DISPLAY 2 606 __u32 caching; 607 }; 608 #define I915_TILING_NONE 0 609 #define I915_TILING_X 1 610 #define I915_TILING_Y 2 611 #define I915_TILING_LAST I915_TILING_Y 612 #define I915_BIT_6_SWIZZLE_NONE 0 613 #define I915_BIT_6_SWIZZLE_9 1 614 #define I915_BIT_6_SWIZZLE_9_10 2 615 #define I915_BIT_6_SWIZZLE_9_11 3 616 #define I915_BIT_6_SWIZZLE_9_10_11 4 617 #define I915_BIT_6_SWIZZLE_UNKNOWN 5 618 #define I915_BIT_6_SWIZZLE_9_17 6 619 #define I915_BIT_6_SWIZZLE_9_10_17 7 620 struct drm_i915_gem_set_tiling { 621 __u32 handle; 622 __u32 tiling_mode; 623 __u32 stride; 624 __u32 swizzle_mode; 625 }; 626 struct drm_i915_gem_get_tiling { 627 __u32 handle; 628 __u32 tiling_mode; 629 __u32 swizzle_mode; 630 __u32 phys_swizzle_mode; 631 }; 632 struct drm_i915_gem_get_aperture { 633 __u64 aper_size; 634 __u64 aper_available_size; 635 }; 636 struct drm_i915_get_pipe_from_crtc_id { 637 __u32 crtc_id; 638 __u32 pipe; 639 }; 640 #define I915_MADV_WILLNEED 0 641 #define I915_MADV_DONTNEED 1 642 #define __I915_MADV_PURGED 2 643 struct drm_i915_gem_madvise { 644 __u32 handle; 645 __u32 madv; 646 __u32 retained; 647 }; 648 #define I915_OVERLAY_TYPE_MASK 0xff 649 #define I915_OVERLAY_YUV_PLANAR 0x01 650 #define I915_OVERLAY_YUV_PACKED 0x02 651 #define I915_OVERLAY_RGB 0x03 652 #define I915_OVERLAY_DEPTH_MASK 0xff00 653 #define I915_OVERLAY_RGB24 0x1000 654 #define I915_OVERLAY_RGB16 0x2000 655 #define I915_OVERLAY_RGB15 0x3000 656 #define I915_OVERLAY_YUV422 0x0100 657 #define I915_OVERLAY_YUV411 0x0200 658 #define I915_OVERLAY_YUV420 0x0300 659 #define I915_OVERLAY_YUV410 0x0400 660 #define I915_OVERLAY_SWAP_MASK 0xff0000 661 #define I915_OVERLAY_NO_SWAP 0x000000 662 #define I915_OVERLAY_UV_SWAP 0x010000 663 #define I915_OVERLAY_Y_SWAP 0x020000 664 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 665 #define I915_OVERLAY_FLAGS_MASK 0xff000000 666 #define I915_OVERLAY_ENABLE 0x01000000 667 struct drm_intel_overlay_put_image { 668 __u32 flags; 669 __u32 bo_handle; 670 __u16 stride_Y; 671 __u16 stride_UV; 672 __u32 offset_Y; 673 __u32 offset_U; 674 __u32 offset_V; 675 __u16 src_width; 676 __u16 src_height; 677 __u16 src_scan_width; 678 __u16 src_scan_height; 679 __u32 crtc_id; 680 __u16 dst_x; 681 __u16 dst_y; 682 __u16 dst_width; 683 __u16 dst_height; 684 }; 685 #define I915_OVERLAY_UPDATE_ATTRS (1 << 0) 686 #define I915_OVERLAY_UPDATE_GAMMA (1 << 1) 687 #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1 << 2) 688 struct drm_intel_overlay_attrs { 689 __u32 flags; 690 __u32 color_key; 691 __s32 brightness; 692 __u32 contrast; 693 __u32 saturation; 694 __u32 gamma0; 695 __u32 gamma1; 696 __u32 gamma2; 697 __u32 gamma3; 698 __u32 gamma4; 699 __u32 gamma5; 700 }; 701 #define I915_SET_COLORKEY_NONE (1 << 0) 702 #define I915_SET_COLORKEY_DESTINATION (1 << 1) 703 #define I915_SET_COLORKEY_SOURCE (1 << 2) 704 struct drm_intel_sprite_colorkey { 705 __u32 plane_id; 706 __u32 min_value; 707 __u32 channel_mask; 708 __u32 max_value; 709 __u32 flags; 710 }; 711 struct drm_i915_gem_wait { 712 __u32 bo_handle; 713 __u32 flags; 714 __s64 timeout_ns; 715 }; 716 struct drm_i915_gem_context_create { 717 __u32 ctx_id; 718 __u32 pad; 719 }; 720 struct drm_i915_gem_context_create_ext { 721 __u32 ctx_id; 722 __u32 flags; 723 #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0) 724 #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1) 725 #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (- (I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1)) 726 __u64 extensions; 727 #define I915_CONTEXT_CREATE_EXT_SETPARAM 0 728 #define I915_CONTEXT_CREATE_EXT_CLONE 1 729 }; 730 struct drm_i915_gem_context_param { 731 __u32 ctx_id; 732 __u32 size; 733 __u64 param; 734 #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 735 #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 736 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 737 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 738 #define I915_CONTEXT_PARAM_BANNABLE 0x5 739 #define I915_CONTEXT_PARAM_PRIORITY 0x6 740 #define I915_CONTEXT_MAX_USER_PRIORITY 1023 741 #define I915_CONTEXT_DEFAULT_PRIORITY 0 742 #define I915_CONTEXT_MIN_USER_PRIORITY - 1023 743 #define I915_CONTEXT_PARAM_SSEU 0x7 744 #define I915_CONTEXT_PARAM_RECOVERABLE 0x8 745 #define I915_CONTEXT_PARAM_VM 0x9 746 #define I915_CONTEXT_PARAM_ENGINES 0xa 747 #define I915_CONTEXT_PARAM_PERSISTENCE 0xb 748 #define I915_CONTEXT_PARAM_RINGSIZE 0xc 749 #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd 750 __u64 value; 751 }; 752 struct drm_i915_gem_context_param_sseu { 753 struct i915_engine_class_instance engine; 754 __u32 flags; 755 #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0) 756 __u64 slice_mask; 757 __u64 subslice_mask; 758 __u16 min_eus_per_subslice; 759 __u16 max_eus_per_subslice; 760 __u32 rsvd; 761 }; 762 struct i915_context_engines_load_balance { 763 struct i915_user_extension base; 764 __u16 engine_index; 765 __u16 num_siblings; 766 __u32 flags; 767 __u64 mbz64; 768 struct i915_engine_class_instance engines[]; 769 } __attribute__((packed)); 770 #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__,N__) struct { struct i915_user_extension base; __u16 engine_index; __u16 num_siblings; __u32 flags; __u64 mbz64; struct i915_engine_class_instance engines[N__]; \ 771 } __attribute__((packed)) name__ 772 struct i915_context_engines_bond { 773 struct i915_user_extension base; 774 struct i915_engine_class_instance master; 775 __u16 virtual_index; 776 __u16 num_bonds; 777 __u64 flags; 778 __u64 mbz64[4]; 779 struct i915_engine_class_instance engines[]; 780 } __attribute__((packed)); 781 #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__,N__) struct { struct i915_user_extension base; struct i915_engine_class_instance master; __u16 virtual_index; __u16 num_bonds; __u64 flags; __u64 mbz64[4]; struct i915_engine_class_instance engines[N__]; \ 782 } __attribute__((packed)) name__ 783 struct i915_context_engines_parallel_submit { 784 struct i915_user_extension base; 785 __u16 engine_index; 786 __u16 width; 787 __u16 num_siblings; 788 __u16 mbz16; 789 __u64 flags; 790 __u64 mbz64[3]; 791 struct i915_engine_class_instance engines[]; 792 } __attribute__((__packed__)); 793 #define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__,N__) struct { struct i915_user_extension base; __u16 engine_index; __u16 width; __u16 num_siblings; __u16 mbz16; __u64 flags; __u64 mbz64[3]; struct i915_engine_class_instance engines[N__]; \ 794 } __attribute__((packed)) name__ 795 struct i915_context_param_engines { 796 __u64 extensions; 797 #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 798 #define I915_CONTEXT_ENGINES_EXT_BOND 1 799 #define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 800 struct i915_engine_class_instance engines[0]; 801 } __attribute__((packed)); 802 #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__,N__) struct { __u64 extensions; struct i915_engine_class_instance engines[N__]; \ 803 } __attribute__((packed)) name__ 804 struct drm_i915_gem_context_create_ext_setparam { 805 struct i915_user_extension base; 806 struct drm_i915_gem_context_param param; 807 }; 808 struct drm_i915_gem_context_destroy { 809 __u32 ctx_id; 810 __u32 pad; 811 }; 812 struct drm_i915_gem_vm_control { 813 __u64 extensions; 814 __u32 flags; 815 __u32 vm_id; 816 }; 817 struct drm_i915_reg_read { 818 __u64 offset; 819 #define I915_REG_READ_8B_WA (1ul << 0) 820 __u64 val; 821 }; 822 struct drm_i915_reset_stats { 823 __u32 ctx_id; 824 __u32 flags; 825 __u32 reset_count; 826 __u32 batch_active; 827 __u32 batch_pending; 828 __u32 pad; 829 }; 830 struct drm_i915_gem_userptr { 831 __u64 user_ptr; 832 __u64 user_size; 833 __u32 flags; 834 #define I915_USERPTR_READ_ONLY 0x1 835 #define I915_USERPTR_PROBE 0x2 836 #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 837 __u32 handle; 838 }; 839 enum drm_i915_oa_format { 840 I915_OA_FORMAT_A13 = 1, 841 I915_OA_FORMAT_A29, 842 I915_OA_FORMAT_A13_B8_C8, 843 I915_OA_FORMAT_B4_C8, 844 I915_OA_FORMAT_A45_B8_C8, 845 I915_OA_FORMAT_B4_C8_A16, 846 I915_OA_FORMAT_C4_B8, 847 I915_OA_FORMAT_A12, 848 I915_OA_FORMAT_A12_B8_C8, 849 I915_OA_FORMAT_A32u40_A4u32_B8_C8, 850 I915_OAR_FORMAT_A32u40_A4u32_B8_C8, 851 I915_OA_FORMAT_A24u40_A14u32_B8_C8, 852 I915_OA_FORMAT_MAX 853 }; 854 enum drm_i915_perf_property_id { 855 DRM_I915_PERF_PROP_CTX_HANDLE = 1, 856 DRM_I915_PERF_PROP_SAMPLE_OA, 857 DRM_I915_PERF_PROP_OA_METRICS_SET, 858 DRM_I915_PERF_PROP_OA_FORMAT, 859 DRM_I915_PERF_PROP_OA_EXPONENT, 860 DRM_I915_PERF_PROP_HOLD_PREEMPTION, 861 DRM_I915_PERF_PROP_GLOBAL_SSEU, 862 DRM_I915_PERF_PROP_POLL_OA_PERIOD, 863 DRM_I915_PERF_PROP_MAX 864 }; 865 struct drm_i915_perf_open_param { 866 __u32 flags; 867 #define I915_PERF_FLAG_FD_CLOEXEC (1 << 0) 868 #define I915_PERF_FLAG_FD_NONBLOCK (1 << 1) 869 #define I915_PERF_FLAG_DISABLED (1 << 2) 870 __u32 num_properties; 871 __u64 properties_ptr; 872 }; 873 #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) 874 #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) 875 #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2) 876 struct drm_i915_perf_record_header { 877 __u32 type; 878 __u16 pad; 879 __u16 size; 880 }; 881 enum drm_i915_perf_record_type { 882 DRM_I915_PERF_RECORD_SAMPLE = 1, 883 DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, 884 DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, 885 DRM_I915_PERF_RECORD_MAX 886 }; 887 struct drm_i915_perf_oa_config { 888 char uuid[36]; 889 __u32 n_mux_regs; 890 __u32 n_boolean_regs; 891 __u32 n_flex_regs; 892 __u64 mux_regs_ptr; 893 __u64 boolean_regs_ptr; 894 __u64 flex_regs_ptr; 895 }; 896 struct drm_i915_query_item { 897 __u64 query_id; 898 #define DRM_I915_QUERY_TOPOLOGY_INFO 1 899 #define DRM_I915_QUERY_ENGINE_INFO 2 900 #define DRM_I915_QUERY_PERF_CONFIG 3 901 #define DRM_I915_QUERY_MEMORY_REGIONS 4 902 #define DRM_I915_QUERY_HWCONFIG_BLOB 5 903 #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6 904 __s32 length; 905 __u32 flags; 906 #define DRM_I915_QUERY_PERF_CONFIG_LIST 1 907 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2 908 #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3 909 __u64 data_ptr; 910 }; 911 struct drm_i915_query { 912 __u32 num_items; 913 __u32 flags; 914 __u64 items_ptr; 915 }; 916 struct drm_i915_query_topology_info { 917 __u16 flags; 918 __u16 max_slices; 919 __u16 max_subslices; 920 __u16 max_eus_per_subslice; 921 __u16 subslice_offset; 922 __u16 subslice_stride; 923 __u16 eu_offset; 924 __u16 eu_stride; 925 __u8 data[]; 926 }; 927 struct drm_i915_engine_info { 928 struct i915_engine_class_instance engine; 929 __u32 rsvd0; 930 __u64 flags; 931 #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0) 932 __u64 capabilities; 933 #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0) 934 #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1) 935 __u16 logical_instance; 936 __u16 rsvd1[3]; 937 __u64 rsvd2[3]; 938 }; 939 struct drm_i915_query_engine_info { 940 __u32 num_engines; 941 __u32 rsvd[3]; 942 struct drm_i915_engine_info engines[]; 943 }; 944 struct drm_i915_query_perf_config { 945 union { 946 __u64 n_configs; 947 __u64 config; 948 char uuid[36]; 949 }; 950 __u32 flags; 951 __u8 data[]; 952 }; 953 enum drm_i915_gem_memory_class { 954 I915_MEMORY_CLASS_SYSTEM = 0, 955 I915_MEMORY_CLASS_DEVICE, 956 }; 957 struct drm_i915_gem_memory_class_instance { 958 __u16 memory_class; 959 __u16 memory_instance; 960 }; 961 struct drm_i915_memory_region_info { 962 struct drm_i915_gem_memory_class_instance region; 963 __u32 rsvd0; 964 __u64 probed_size; 965 __u64 unallocated_size; 966 union { 967 __u64 rsvd1[8]; 968 struct { 969 __u64 probed_cpu_visible_size; 970 __u64 unallocated_cpu_visible_size; 971 }; 972 }; 973 }; 974 struct drm_i915_query_memory_regions { 975 __u32 num_regions; 976 __u32 rsvd[3]; 977 struct drm_i915_memory_region_info regions[]; 978 }; 979 struct drm_i915_gem_create_ext { 980 __u64 size; 981 __u32 handle; 982 #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0) 983 __u32 flags; 984 #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 985 #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 986 __u64 extensions; 987 }; 988 struct drm_i915_gem_create_ext_memory_regions { 989 struct i915_user_extension base; 990 __u32 pad; 991 __u32 num_regions; 992 __u64 regions; 993 }; 994 struct drm_i915_gem_create_ext_protected_content { 995 struct i915_user_extension base; 996 __u32 flags; 997 }; 998 #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf 999 #ifdef __cplusplus 1000 } 1001 #endif 1002 #endif 1003