1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_TEGRA_DRM_H_ 20 #define _UAPI_TEGRA_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) 26 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) 27 struct drm_tegra_gem_create { 28 __u64 size; 29 __u32 flags; 30 __u32 handle; 31 }; 32 struct drm_tegra_gem_mmap { 33 __u32 handle; 34 __u32 pad; 35 __u64 offset; 36 }; 37 struct drm_tegra_syncpt_read { 38 __u32 id; 39 __u32 value; 40 }; 41 struct drm_tegra_syncpt_incr { 42 __u32 id; 43 __u32 pad; 44 }; 45 struct drm_tegra_syncpt_wait { 46 __u32 id; 47 __u32 thresh; 48 __u32 timeout; 49 __u32 value; 50 }; 51 #define DRM_TEGRA_NO_TIMEOUT (0xffffffff) 52 struct drm_tegra_open_channel { 53 __u32 client; 54 __u32 pad; 55 __u64 context; 56 }; 57 struct drm_tegra_close_channel { 58 __u64 context; 59 }; 60 struct drm_tegra_get_syncpt { 61 __u64 context; 62 __u32 index; 63 __u32 id; 64 }; 65 struct drm_tegra_get_syncpt_base { 66 __u64 context; 67 __u32 syncpt; 68 __u32 id; 69 }; 70 struct drm_tegra_syncpt { 71 __u32 id; 72 __u32 incrs; 73 }; 74 struct drm_tegra_cmdbuf { 75 __u32 handle; 76 __u32 offset; 77 __u32 words; 78 __u32 pad; 79 }; 80 struct drm_tegra_reloc { 81 struct { 82 __u32 handle; 83 __u32 offset; 84 } cmdbuf; 85 struct { 86 __u32 handle; 87 __u32 offset; 88 } target; 89 __u32 shift; 90 __u32 pad; 91 }; 92 struct drm_tegra_waitchk { 93 __u32 handle; 94 __u32 offset; 95 __u32 syncpt; 96 __u32 thresh; 97 }; 98 struct drm_tegra_submit { 99 __u64 context; 100 __u32 num_syncpts; 101 __u32 num_cmdbufs; 102 __u32 num_relocs; 103 __u32 num_waitchks; 104 __u32 waitchk_mask; 105 __u32 timeout; 106 __u64 syncpts; 107 __u64 cmdbufs; 108 __u64 relocs; 109 __u64 waitchks; 110 __u32 fence; 111 __u32 reserved[5]; 112 }; 113 #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 114 #define DRM_TEGRA_GEM_TILING_MODE_TILED 1 115 #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 116 struct drm_tegra_gem_set_tiling { 117 __u32 handle; 118 __u32 mode; 119 __u32 value; 120 __u32 pad; 121 }; 122 struct drm_tegra_gem_get_tiling { 123 __u32 handle; 124 __u32 mode; 125 __u32 value; 126 __u32 pad; 127 }; 128 #define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) 129 #define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) 130 struct drm_tegra_gem_set_flags { 131 __u32 handle; 132 __u32 flags; 133 }; 134 struct drm_tegra_gem_get_flags { 135 __u32 handle; 136 __u32 flags; 137 }; 138 #define DRM_TEGRA_GEM_CREATE 0x00 139 #define DRM_TEGRA_GEM_MMAP 0x01 140 #define DRM_TEGRA_SYNCPT_READ 0x02 141 #define DRM_TEGRA_SYNCPT_INCR 0x03 142 #define DRM_TEGRA_SYNCPT_WAIT 0x04 143 #define DRM_TEGRA_OPEN_CHANNEL 0x05 144 #define DRM_TEGRA_CLOSE_CHANNEL 0x06 145 #define DRM_TEGRA_GET_SYNCPT 0x07 146 #define DRM_TEGRA_SUBMIT 0x08 147 #define DRM_TEGRA_GET_SYNCPT_BASE 0x09 148 #define DRM_TEGRA_GEM_SET_TILING 0x0a 149 #define DRM_TEGRA_GEM_GET_TILING 0x0b 150 #define DRM_TEGRA_GEM_SET_FLAGS 0x0c 151 #define DRM_TEGRA_GEM_GET_FLAGS 0x0d 152 #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) 153 #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) 154 #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) 155 #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) 156 #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) 157 #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) 158 #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel) 159 #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) 160 #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) 161 #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) 162 #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) 163 #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) 164 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) 165 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) 166 #define DRM_TEGRA_CHANNEL_CAP_CACHE_COHERENT (1 << 0) 167 struct drm_tegra_channel_open { 168 __u32 host1x_class; 169 __u32 flags; 170 __u32 context; 171 __u32 version; 172 __u32 capabilities; 173 __u32 padding; 174 }; 175 struct drm_tegra_channel_close { 176 __u32 context; 177 __u32 padding; 178 }; 179 #define DRM_TEGRA_CHANNEL_MAP_READ (1 << 0) 180 #define DRM_TEGRA_CHANNEL_MAP_WRITE (1 << 1) 181 #define DRM_TEGRA_CHANNEL_MAP_READ_WRITE (DRM_TEGRA_CHANNEL_MAP_READ | DRM_TEGRA_CHANNEL_MAP_WRITE) 182 struct drm_tegra_channel_map { 183 __u32 context; 184 __u32 handle; 185 __u32 flags; 186 __u32 mapping; 187 }; 188 struct drm_tegra_channel_unmap { 189 __u32 context; 190 __u32 mapping; 191 }; 192 #define DRM_TEGRA_SUBMIT_RELOC_SECTOR_LAYOUT (1 << 0) 193 struct drm_tegra_submit_buf { 194 __u32 mapping; 195 __u32 flags; 196 struct { 197 __u64 target_offset; 198 __u32 gather_offset_words; 199 __u32 shift; 200 } reloc; 201 }; 202 #define DRM_TEGRA_SUBMIT_CMD_GATHER_UPTR 0 203 #define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT 1 204 #define DRM_TEGRA_SUBMIT_CMD_WAIT_SYNCPT_RELATIVE 2 205 struct drm_tegra_submit_cmd_gather_uptr { 206 __u32 words; 207 __u32 reserved[3]; 208 }; 209 struct drm_tegra_submit_cmd_wait_syncpt { 210 __u32 id; 211 __u32 value; 212 __u32 reserved[2]; 213 }; 214 struct drm_tegra_submit_cmd { 215 __u32 type; 216 __u32 flags; 217 union { 218 struct drm_tegra_submit_cmd_gather_uptr gather_uptr; 219 struct drm_tegra_submit_cmd_wait_syncpt wait_syncpt; 220 __u32 reserved[4]; 221 }; 222 }; 223 struct drm_tegra_submit_syncpt { 224 __u32 id; 225 __u32 flags; 226 __u32 increments; 227 __u32 value; 228 }; 229 struct drm_tegra_channel_submit { 230 __u32 context; 231 __u32 num_bufs; 232 __u32 num_cmds; 233 __u32 gather_data_words; 234 __u64 bufs_ptr; 235 __u64 cmds_ptr; 236 __u64 gather_data_ptr; 237 __u32 syncobj_in; 238 __u32 syncobj_out; 239 struct drm_tegra_submit_syncpt syncpt; 240 }; 241 struct drm_tegra_syncpoint_allocate { 242 __u32 id; 243 __u32 padding; 244 }; 245 struct drm_tegra_syncpoint_free { 246 __u32 id; 247 __u32 padding; 248 }; 249 struct drm_tegra_syncpoint_wait { 250 __s64 timeout_ns; 251 __u32 id; 252 __u32 threshold; 253 __u32 value; 254 __u32 padding; 255 }; 256 #define DRM_IOCTL_TEGRA_CHANNEL_OPEN DRM_IOWR(DRM_COMMAND_BASE + 0x10, struct drm_tegra_channel_open) 257 #define DRM_IOCTL_TEGRA_CHANNEL_CLOSE DRM_IOWR(DRM_COMMAND_BASE + 0x11, struct drm_tegra_channel_close) 258 #define DRM_IOCTL_TEGRA_CHANNEL_MAP DRM_IOWR(DRM_COMMAND_BASE + 0x12, struct drm_tegra_channel_map) 259 #define DRM_IOCTL_TEGRA_CHANNEL_UNMAP DRM_IOWR(DRM_COMMAND_BASE + 0x13, struct drm_tegra_channel_unmap) 260 #define DRM_IOCTL_TEGRA_CHANNEL_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + 0x14, struct drm_tegra_channel_submit) 261 #define DRM_IOCTL_TEGRA_SYNCPOINT_ALLOCATE DRM_IOWR(DRM_COMMAND_BASE + 0x20, struct drm_tegra_syncpoint_allocate) 262 #define DRM_IOCTL_TEGRA_SYNCPOINT_FREE DRM_IOWR(DRM_COMMAND_BASE + 0x21, struct drm_tegra_syncpoint_free) 263 #define DRM_IOCTL_TEGRA_SYNCPOINT_WAIT DRM_IOWR(DRM_COMMAND_BASE + 0x22, struct drm_tegra_syncpoint_wait) 264 #ifdef __cplusplus 265 } 266 #endif 267 #endif 268