1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _USR_IDXD_H_ 20 #define _USR_IDXD_H_ 21 #include <stdint.h> 22 enum idxd_scmd_stat { 23 IDXD_SCMD_DEV_ENABLED = 0x80000010, 24 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020, 25 IDXD_SCMD_WQ_ENABLED = 0x80000021, 26 IDXD_SCMD_DEV_DMA_ERR = 0x80020000, 27 IDXD_SCMD_WQ_NO_GRP = 0x80030000, 28 IDXD_SCMD_WQ_NO_NAME = 0x80040000, 29 IDXD_SCMD_WQ_NO_SVM = 0x80050000, 30 IDXD_SCMD_WQ_NO_THRESH = 0x80060000, 31 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000, 32 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000, 33 IDXD_SCMD_PERCPU_ERR = 0x80090000, 34 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000, 35 IDXD_SCMD_CDEV_ERR = 0x800b0000, 36 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000, 37 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000, 38 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000, 39 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000, 40 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000, 41 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000, 42 }; 43 #define IDXD_SCMD_SOFTERR_MASK 0x80000000 44 #define IDXD_SCMD_SOFTERR_SHIFT 16 45 #define IDXD_OP_FLAG_FENCE 0x0001 46 #define IDXD_OP_FLAG_BOF 0x0002 47 #define IDXD_OP_FLAG_CRAV 0x0004 48 #define IDXD_OP_FLAG_RCR 0x0008 49 #define IDXD_OP_FLAG_RCI 0x0010 50 #define IDXD_OP_FLAG_CRSTS 0x0020 51 #define IDXD_OP_FLAG_CR 0x0080 52 #define IDXD_OP_FLAG_CC 0x0100 53 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200 54 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400 55 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800 56 #define IDXD_OP_FLAG_CR_TCS 0x1000 57 #define IDXD_OP_FLAG_STORD 0x2000 58 #define IDXD_OP_FLAG_DRDBK 0x4000 59 #define IDXD_OP_FLAG_DSTS 0x8000 60 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000 61 #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000 62 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000 63 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000 64 #define IDXD_OP_FLAG_SRC2_STS 0x100000 65 #define IDXD_OP_FLAG_CRC_RFC3720 0x200000 66 enum dsa_opcode { 67 DSA_OPCODE_NOOP = 0, 68 DSA_OPCODE_BATCH, 69 DSA_OPCODE_DRAIN, 70 DSA_OPCODE_MEMMOVE, 71 DSA_OPCODE_MEMFILL, 72 DSA_OPCODE_COMPARE, 73 DSA_OPCODE_COMPVAL, 74 DSA_OPCODE_CR_DELTA, 75 DSA_OPCODE_AP_DELTA, 76 DSA_OPCODE_DUALCAST, 77 DSA_OPCODE_CRCGEN = 0x10, 78 DSA_OPCODE_COPY_CRC, 79 DSA_OPCODE_DIF_CHECK, 80 DSA_OPCODE_DIF_INS, 81 DSA_OPCODE_DIF_STRP, 82 DSA_OPCODE_DIF_UPDT, 83 DSA_OPCODE_CFLUSH = 0x20, 84 }; 85 enum iax_opcode { 86 IAX_OPCODE_NOOP = 0, 87 IAX_OPCODE_DRAIN = 2, 88 IAX_OPCODE_MEMMOVE, 89 IAX_OPCODE_DECOMPRESS = 0x42, 90 IAX_OPCODE_COMPRESS, 91 IAX_OPCODE_CRC64, 92 IAX_OPCODE_ZERO_DECOMP_32 = 0x48, 93 IAX_OPCODE_ZERO_DECOMP_16, 94 IAX_OPCODE_ZERO_COMP_32 = 0x4c, 95 IAX_OPCODE_ZERO_COMP_16, 96 IAX_OPCODE_SCAN = 0x50, 97 IAX_OPCODE_SET_MEMBER, 98 IAX_OPCODE_EXTRACT, 99 IAX_OPCODE_SELECT, 100 IAX_OPCODE_RLE_BURST, 101 IAX_OPCODE_FIND_UNIQUE, 102 IAX_OPCODE_EXPAND, 103 }; 104 enum dsa_completion_status { 105 DSA_COMP_NONE = 0, 106 DSA_COMP_SUCCESS, 107 DSA_COMP_SUCCESS_PRED, 108 DSA_COMP_PAGE_FAULT_NOBOF, 109 DSA_COMP_PAGE_FAULT_IR, 110 DSA_COMP_BATCH_FAIL, 111 DSA_COMP_BATCH_PAGE_FAULT, 112 DSA_COMP_DR_OFFSET_NOINC, 113 DSA_COMP_DR_OFFSET_ERANGE, 114 DSA_COMP_DIF_ERR, 115 DSA_COMP_BAD_OPCODE = 0x10, 116 DSA_COMP_INVALID_FLAGS, 117 DSA_COMP_NOZERO_RESERVE, 118 DSA_COMP_XFER_ERANGE, 119 DSA_COMP_DESC_CNT_ERANGE, 120 DSA_COMP_DR_ERANGE, 121 DSA_COMP_OVERLAP_BUFFERS, 122 DSA_COMP_DCAST_ERR, 123 DSA_COMP_DESCLIST_ALIGN, 124 DSA_COMP_INT_HANDLE_INVAL, 125 DSA_COMP_CRA_XLAT, 126 DSA_COMP_CRA_ALIGN, 127 DSA_COMP_ADDR_ALIGN, 128 DSA_COMP_PRIV_BAD, 129 DSA_COMP_TRAFFIC_CLASS_CONF, 130 DSA_COMP_PFAULT_RDBA, 131 DSA_COMP_HW_ERR1, 132 DSA_COMP_HW_ERR_DRB, 133 DSA_COMP_TRANSLATION_FAIL, 134 }; 135 enum iax_completion_status { 136 IAX_COMP_NONE = 0, 137 IAX_COMP_SUCCESS, 138 IAX_COMP_PAGE_FAULT_IR = 0x04, 139 IAX_COMP_ANALYTICS_ERROR = 0x0a, 140 IAX_COMP_OUTBUF_OVERFLOW, 141 IAX_COMP_BAD_OPCODE = 0x10, 142 IAX_COMP_INVALID_FLAGS, 143 IAX_COMP_NOZERO_RESERVE, 144 IAX_COMP_INVALID_SIZE, 145 IAX_COMP_OVERLAP_BUFFERS = 0x16, 146 IAX_COMP_INT_HANDLE_INVAL = 0x19, 147 IAX_COMP_CRA_XLAT, 148 IAX_COMP_CRA_ALIGN, 149 IAX_COMP_ADDR_ALIGN, 150 IAX_COMP_PRIV_BAD, 151 IAX_COMP_TRAFFIC_CLASS_CONF, 152 IAX_COMP_PFAULT_RDBA, 153 IAX_COMP_HW_ERR1, 154 IAX_COMP_HW_ERR_DRB, 155 IAX_COMP_TRANSLATION_FAIL, 156 IAX_COMP_PRS_TIMEOUT, 157 IAX_COMP_WATCHDOG, 158 IAX_COMP_INVALID_COMP_FLAG = 0x30, 159 IAX_COMP_INVALID_FILTER_FLAG, 160 IAX_COMP_INVALID_INPUT_SIZE, 161 IAX_COMP_INVALID_NUM_ELEMS, 162 IAX_COMP_INVALID_SRC1_WIDTH, 163 IAX_COMP_INVALID_INVERT_OUT, 164 }; 165 #define DSA_COMP_STATUS_MASK 0x7f 166 #define DSA_COMP_STATUS_WRITE 0x80 167 struct dsa_hw_desc { 168 uint32_t pasid : 20; 169 uint32_t rsvd : 11; 170 uint32_t priv : 1; 171 uint32_t flags : 24; 172 uint32_t opcode : 8; 173 uint64_t completion_addr; 174 union { 175 uint64_t src_addr; 176 uint64_t rdback_addr; 177 uint64_t pattern; 178 uint64_t desc_list_addr; 179 }; 180 union { 181 uint64_t dst_addr; 182 uint64_t rdback_addr2; 183 uint64_t src2_addr; 184 uint64_t comp_pattern; 185 }; 186 union { 187 uint32_t xfer_size; 188 uint32_t desc_count; 189 }; 190 uint16_t int_handle; 191 uint16_t rsvd1; 192 union { 193 uint8_t expected_res; 194 struct { 195 uint64_t delta_addr; 196 uint32_t max_delta_size; 197 uint32_t delt_rsvd; 198 uint8_t expected_res_mask; 199 }; 200 uint32_t delta_rec_size; 201 uint64_t dest2; 202 struct { 203 uint32_t crc_seed; 204 uint32_t crc_rsvd; 205 uint64_t seed_addr; 206 }; 207 struct { 208 uint8_t src_dif_flags; 209 uint8_t dif_chk_res; 210 uint8_t dif_chk_flags; 211 uint8_t dif_chk_res2[5]; 212 uint32_t chk_ref_tag_seed; 213 uint16_t chk_app_tag_mask; 214 uint16_t chk_app_tag_seed; 215 }; 216 struct { 217 uint8_t dif_ins_res; 218 uint8_t dest_dif_flag; 219 uint8_t dif_ins_flags; 220 uint8_t dif_ins_res2[13]; 221 uint32_t ins_ref_tag_seed; 222 uint16_t ins_app_tag_mask; 223 uint16_t ins_app_tag_seed; 224 }; 225 struct { 226 uint8_t src_upd_flags; 227 uint8_t upd_dest_flags; 228 uint8_t dif_upd_flags; 229 uint8_t dif_upd_res[5]; 230 uint32_t src_ref_tag_seed; 231 uint16_t src_app_tag_mask; 232 uint16_t src_app_tag_seed; 233 uint32_t dest_ref_tag_seed; 234 uint16_t dest_app_tag_mask; 235 uint16_t dest_app_tag_seed; 236 }; 237 uint8_t op_specific[24]; 238 }; 239 } __attribute__((packed)); 240 struct iax_hw_desc { 241 uint32_t pasid : 20; 242 uint32_t rsvd : 11; 243 uint32_t priv : 1; 244 uint32_t flags : 24; 245 uint32_t opcode : 8; 246 uint64_t completion_addr; 247 uint64_t src1_addr; 248 uint64_t dst_addr; 249 uint32_t src1_size; 250 uint16_t int_handle; 251 union { 252 uint16_t compr_flags; 253 uint16_t decompr_flags; 254 }; 255 uint64_t src2_addr; 256 uint32_t max_dst_size; 257 uint32_t src2_size; 258 uint32_t filter_flags; 259 uint32_t num_inputs; 260 } __attribute__((packed)); 261 struct dsa_raw_desc { 262 uint64_t field[8]; 263 } __attribute__((packed)); 264 struct dsa_completion_record { 265 volatile uint8_t status; 266 union { 267 uint8_t result; 268 uint8_t dif_status; 269 }; 270 uint16_t rsvd; 271 uint32_t bytes_completed; 272 uint64_t fault_addr; 273 union { 274 struct { 275 uint32_t invalid_flags : 24; 276 uint32_t rsvd2 : 8; 277 }; 278 uint32_t delta_rec_size; 279 uint64_t crc_val; 280 struct { 281 uint32_t dif_chk_ref_tag; 282 uint16_t dif_chk_app_tag_mask; 283 uint16_t dif_chk_app_tag; 284 }; 285 struct { 286 uint64_t dif_ins_res; 287 uint32_t dif_ins_ref_tag; 288 uint16_t dif_ins_app_tag_mask; 289 uint16_t dif_ins_app_tag; 290 }; 291 struct { 292 uint32_t dif_upd_src_ref_tag; 293 uint16_t dif_upd_src_app_tag_mask; 294 uint16_t dif_upd_src_app_tag; 295 uint32_t dif_upd_dest_ref_tag; 296 uint16_t dif_upd_dest_app_tag_mask; 297 uint16_t dif_upd_dest_app_tag; 298 }; 299 uint8_t op_specific[16]; 300 }; 301 } __attribute__((packed)); 302 struct dsa_raw_completion_record { 303 uint64_t field[4]; 304 } __attribute__((packed)); 305 struct iax_completion_record { 306 volatile uint8_t status; 307 uint8_t error_code; 308 uint16_t rsvd; 309 uint32_t bytes_completed; 310 uint64_t fault_addr; 311 uint32_t invalid_flags; 312 uint32_t rsvd2; 313 uint32_t output_size; 314 uint8_t output_bits; 315 uint8_t rsvd3; 316 uint16_t xor_csum; 317 uint32_t crc; 318 uint32_t min; 319 uint32_t max; 320 uint32_t sum; 321 uint64_t rsvd4[2]; 322 } __attribute__((packed)); 323 struct iax_raw_completion_record { 324 uint64_t field[8]; 325 } __attribute__((packed)); 326 #endif 327