1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef MLX5_ABI_USER_H 20 #define MLX5_ABI_USER_H 21 #include <linux/types.h> 22 #include <linux/if_ether.h> 23 #include <rdma/ib_user_ioctl_verbs.h> 24 enum { 25 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 26 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 27 MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2, 28 MLX5_QP_FLAG_BFREG_INDEX = 1 << 3, 29 MLX5_QP_FLAG_TYPE_DCT = 1 << 4, 30 MLX5_QP_FLAG_TYPE_DCI = 1 << 5, 31 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_UC = 1 << 6, 32 MLX5_QP_FLAG_TIR_ALLOW_SELF_LB_MC = 1 << 7, 33 MLX5_QP_FLAG_ALLOW_SCATTER_CQE = 1 << 8, 34 MLX5_QP_FLAG_PACKET_BASED_CREDIT_MODE = 1 << 9, 35 MLX5_QP_FLAG_UAR_PAGE_INDEX = 1 << 10, 36 MLX5_QP_FLAG_DCI_STREAM = 1 << 11, 37 }; 38 enum { 39 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 40 }; 41 enum { 42 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 43 }; 44 #define MLX5_IB_UVERBS_ABI_VERSION 1 45 struct mlx5_ib_alloc_ucontext_req { 46 __u32 total_num_bfregs; 47 __u32 num_low_latency_bfregs; 48 }; 49 enum mlx5_lib_caps { 50 MLX5_LIB_CAP_4K_UAR = (__u64) 1 << 0, 51 MLX5_LIB_CAP_DYN_UAR = (__u64) 1 << 1, 52 }; 53 enum mlx5_ib_alloc_uctx_v2_flags { 54 MLX5_IB_ALLOC_UCTX_DEVX = 1 << 0, 55 }; 56 struct mlx5_ib_alloc_ucontext_req_v2 { 57 __u32 total_num_bfregs; 58 __u32 num_low_latency_bfregs; 59 __u32 flags; 60 __u32 comp_mask; 61 __u8 max_cqe_version; 62 __u8 reserved0; 63 __u16 reserved1; 64 __u32 reserved2; 65 __aligned_u64 lib_caps; 66 }; 67 enum mlx5_ib_alloc_ucontext_resp_mask { 68 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 69 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY = 1UL << 1, 70 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE = 1UL << 2, 71 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS = 1UL << 3, 72 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS = 1UL << 4, 73 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG = 1UL << 5, 74 }; 75 enum mlx5_user_cmds_supp_uhw { 76 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 77 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 78 }; 79 enum mlx5_user_inline_mode { 80 MLX5_USER_INLINE_MODE_NA, 81 MLX5_USER_INLINE_MODE_NONE, 82 MLX5_USER_INLINE_MODE_L2, 83 MLX5_USER_INLINE_MODE_IP, 84 MLX5_USER_INLINE_MODE_TCP_UDP, 85 }; 86 enum { 87 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM = 1 << 0, 88 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA = 1 << 1, 89 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING = 1 << 2, 90 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD = 1 << 3, 91 MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN = 1 << 4, 92 }; 93 struct mlx5_ib_alloc_ucontext_resp { 94 __u32 qp_tab_size; 95 __u32 bf_reg_size; 96 __u32 tot_bfregs; 97 __u32 cache_line_size; 98 __u16 max_sq_desc_sz; 99 __u16 max_rq_desc_sz; 100 __u32 max_send_wqebb; 101 __u32 max_recv_wr; 102 __u32 max_srq_recv_wr; 103 __u16 num_ports; 104 __u16 flow_action_flags; 105 __u32 comp_mask; 106 __u32 response_length; 107 __u8 cqe_version; 108 __u8 cmds_supp_uhw; 109 __u8 eth_min_inline; 110 __u8 clock_info_versions; 111 __aligned_u64 hca_core_clock_offset; 112 __u32 log_uar_size; 113 __u32 num_uars_per_page; 114 __u32 num_dyn_bfregs; 115 __u32 dump_fill_mkey; 116 }; 117 struct mlx5_ib_alloc_pd_resp { 118 __u32 pdn; 119 }; 120 struct mlx5_ib_tso_caps { 121 __u32 max_tso; 122 __u32 supported_qpts; 123 }; 124 struct mlx5_ib_rss_caps { 125 __aligned_u64 rx_hash_fields_mask; 126 __u8 rx_hash_function; 127 __u8 reserved[7]; 128 }; 129 enum mlx5_ib_cqe_comp_res_format { 130 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 131 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 132 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX = 1 << 2, 133 }; 134 struct mlx5_ib_cqe_comp_caps { 135 __u32 max_num; 136 __u32 supported_format; 137 }; 138 enum mlx5_ib_packet_pacing_cap_flags { 139 MLX5_IB_PP_SUPPORT_BURST = 1 << 0, 140 }; 141 struct mlx5_packet_pacing_caps { 142 __u32 qp_rate_limit_min; 143 __u32 qp_rate_limit_max; 144 __u32 supported_qpts; 145 __u8 cap_flags; 146 __u8 reserved[3]; 147 }; 148 enum mlx5_ib_mpw_caps { 149 MPW_RESERVED = 1 << 0, 150 MLX5_IB_ALLOW_MPW = 1 << 1, 151 MLX5_IB_SUPPORT_EMPW = 1 << 2, 152 }; 153 enum mlx5_ib_sw_parsing_offloads { 154 MLX5_IB_SW_PARSING = 1 << 0, 155 MLX5_IB_SW_PARSING_CSUM = 1 << 1, 156 MLX5_IB_SW_PARSING_LSO = 1 << 2, 157 }; 158 struct mlx5_ib_sw_parsing_caps { 159 __u32 sw_parsing_offloads; 160 __u32 supported_qpts; 161 }; 162 struct mlx5_ib_striding_rq_caps { 163 __u32 min_single_stride_log_num_of_bytes; 164 __u32 max_single_stride_log_num_of_bytes; 165 __u32 min_single_wqe_log_num_of_strides; 166 __u32 max_single_wqe_log_num_of_strides; 167 __u32 supported_qpts; 168 __u32 reserved; 169 }; 170 struct mlx5_ib_dci_streams_caps { 171 __u8 max_log_num_concurent; 172 __u8 max_log_num_errored; 173 }; 174 enum mlx5_ib_query_dev_resp_flags { 175 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0, 176 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1, 177 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE = 1 << 2, 178 MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT = 1 << 3, 179 }; 180 enum mlx5_ib_tunnel_offloads { 181 MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0, 182 MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1, 183 MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2, 184 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE = 1 << 3, 185 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP = 1 << 4, 186 }; 187 struct mlx5_ib_query_device_resp { 188 __u32 comp_mask; 189 __u32 response_length; 190 struct mlx5_ib_tso_caps tso_caps; 191 struct mlx5_ib_rss_caps rss_caps; 192 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 193 struct mlx5_packet_pacing_caps packet_pacing_caps; 194 __u32 mlx5_ib_support_multi_pkt_send_wqes; 195 __u32 flags; 196 struct mlx5_ib_sw_parsing_caps sw_parsing_caps; 197 struct mlx5_ib_striding_rq_caps striding_rq_caps; 198 __u32 tunnel_offloads_caps; 199 struct mlx5_ib_dci_streams_caps dci_streams_caps; 200 __u16 reserved; 201 }; 202 enum mlx5_ib_create_cq_flags { 203 MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0, 204 MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX = 1 << 1, 205 MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS = 1 << 2, 206 }; 207 struct mlx5_ib_create_cq { 208 __aligned_u64 buf_addr; 209 __aligned_u64 db_addr; 210 __u32 cqe_size; 211 __u8 cqe_comp_en; 212 __u8 cqe_comp_res_format; 213 __u16 flags; 214 __u16 uar_page_index; 215 __u16 reserved0; 216 __u32 reserved1; 217 }; 218 struct mlx5_ib_create_cq_resp { 219 __u32 cqn; 220 __u32 reserved; 221 }; 222 struct mlx5_ib_resize_cq { 223 __aligned_u64 buf_addr; 224 __u16 cqe_size; 225 __u16 reserved0; 226 __u32 reserved1; 227 }; 228 struct mlx5_ib_create_srq { 229 __aligned_u64 buf_addr; 230 __aligned_u64 db_addr; 231 __u32 flags; 232 __u32 reserved0; 233 __u32 uidx; 234 __u32 reserved1; 235 }; 236 struct mlx5_ib_create_srq_resp { 237 __u32 srqn; 238 __u32 reserved; 239 }; 240 struct mlx5_ib_create_qp_dci_streams { 241 __u8 log_num_concurent; 242 __u8 log_num_errored; 243 }; 244 struct mlx5_ib_create_qp { 245 __aligned_u64 buf_addr; 246 __aligned_u64 db_addr; 247 __u32 sq_wqe_count; 248 __u32 rq_wqe_count; 249 __u32 rq_wqe_shift; 250 __u32 flags; 251 __u32 uidx; 252 __u32 bfreg_index; 253 union { 254 __aligned_u64 sq_buf_addr; 255 __aligned_u64 access_key; 256 }; 257 __u32 ece_options; 258 struct mlx5_ib_create_qp_dci_streams dci_streams; 259 __u16 reserved; 260 }; 261 enum mlx5_rx_hash_function_flags { 262 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 263 }; 264 enum mlx5_rx_hash_fields { 265 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 266 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 267 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 268 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 269 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 270 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 271 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 272 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7, 273 MLX5_RX_HASH_IPSEC_SPI = 1 << 8, 274 MLX5_RX_HASH_INNER = (1UL << 31), 275 }; 276 struct mlx5_ib_create_qp_rss { 277 __aligned_u64 rx_hash_fields_mask; 278 __u8 rx_hash_function; 279 __u8 rx_key_len; 280 __u8 reserved[6]; 281 __u8 rx_hash_key[128]; 282 __u32 comp_mask; 283 __u32 flags; 284 }; 285 enum mlx5_ib_create_qp_resp_mask { 286 MLX5_IB_CREATE_QP_RESP_MASK_TIRN = 1UL << 0, 287 MLX5_IB_CREATE_QP_RESP_MASK_TISN = 1UL << 1, 288 MLX5_IB_CREATE_QP_RESP_MASK_RQN = 1UL << 2, 289 MLX5_IB_CREATE_QP_RESP_MASK_SQN = 1UL << 3, 290 MLX5_IB_CREATE_QP_RESP_MASK_TIR_ICM_ADDR = 1UL << 4, 291 }; 292 struct mlx5_ib_create_qp_resp { 293 __u32 bfreg_index; 294 __u32 ece_options; 295 __u32 comp_mask; 296 __u32 tirn; 297 __u32 tisn; 298 __u32 rqn; 299 __u32 sqn; 300 __u32 reserved1; 301 __u64 tir_icm_addr; 302 }; 303 struct mlx5_ib_alloc_mw { 304 __u32 comp_mask; 305 __u8 num_klms; 306 __u8 reserved1; 307 __u16 reserved2; 308 }; 309 enum mlx5_ib_create_wq_mask { 310 MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0), 311 }; 312 struct mlx5_ib_create_wq { 313 __aligned_u64 buf_addr; 314 __aligned_u64 db_addr; 315 __u32 rq_wqe_count; 316 __u32 rq_wqe_shift; 317 __u32 user_index; 318 __u32 flags; 319 __u32 comp_mask; 320 __u32 single_stride_log_num_of_bytes; 321 __u32 single_wqe_log_num_of_strides; 322 __u32 two_byte_shift_en; 323 }; 324 struct mlx5_ib_create_ah_resp { 325 __u32 response_length; 326 __u8 dmac[ETH_ALEN]; 327 __u8 reserved[6]; 328 }; 329 struct mlx5_ib_burst_info { 330 __u32 max_burst_sz; 331 __u16 typical_pkt_sz; 332 __u16 reserved; 333 }; 334 struct mlx5_ib_modify_qp { 335 __u32 comp_mask; 336 struct mlx5_ib_burst_info burst_info; 337 __u32 ece_options; 338 }; 339 struct mlx5_ib_modify_qp_resp { 340 __u32 response_length; 341 __u32 dctn; 342 __u32 ece_options; 343 __u32 reserved; 344 }; 345 struct mlx5_ib_create_wq_resp { 346 __u32 response_length; 347 __u32 reserved; 348 }; 349 struct mlx5_ib_create_rwq_ind_tbl_resp { 350 __u32 response_length; 351 __u32 reserved; 352 }; 353 struct mlx5_ib_modify_wq { 354 __u32 comp_mask; 355 __u32 reserved; 356 }; 357 struct mlx5_ib_clock_info { 358 __u32 sign; 359 __u32 resv; 360 __aligned_u64 nsec; 361 __aligned_u64 cycles; 362 __aligned_u64 frac; 363 __u32 mult; 364 __u32 shift; 365 __aligned_u64 mask; 366 __aligned_u64 overflow_period; 367 }; 368 enum mlx5_ib_mmap_cmd { 369 MLX5_IB_MMAP_REGULAR_PAGE = 0, 370 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES = 1, 371 MLX5_IB_MMAP_WC_PAGE = 2, 372 MLX5_IB_MMAP_NC_PAGE = 3, 373 MLX5_IB_MMAP_CORE_CLOCK = 5, 374 MLX5_IB_MMAP_ALLOC_WC = 6, 375 MLX5_IB_MMAP_CLOCK_INFO = 7, 376 MLX5_IB_MMAP_DEVICE_MEM = 8, 377 }; 378 enum { 379 MLX5_IB_CLOCK_INFO_KERNEL_UPDATING = 1, 380 }; 381 enum { 382 MLX5_IB_CLOCK_INFO_V1 = 0, 383 }; 384 struct mlx5_ib_flow_counters_desc { 385 __u32 description; 386 __u32 index; 387 }; 388 struct mlx5_ib_flow_counters_data { 389 RDMA_UAPI_PTR(struct mlx5_ib_flow_counters_desc *, counters_data); 390 __u32 ncounters; 391 __u32 reserved; 392 }; 393 struct mlx5_ib_create_flow { 394 __u32 ncounters_data; 395 __u32 reserved; 396 struct mlx5_ib_flow_counters_data data[]; 397 }; 398 #endif 399