1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __QEDR_USER_H__ 20 #define __QEDR_USER_H__ 21 #include <linux/types.h> 22 #define QEDR_ABI_VERSION (8) 23 enum qedr_alloc_ucontext_flags { 24 QEDR_ALLOC_UCTX_EDPM_MODE = 1 << 0, 25 QEDR_ALLOC_UCTX_DB_REC = 1 << 1, 26 QEDR_SUPPORT_DPM_SIZES = 1 << 2, 27 }; 28 struct qedr_alloc_ucontext_req { 29 __u32 context_flags; 30 __u32 reserved; 31 }; 32 #define QEDR_LDPM_MAX_SIZE (8192) 33 #define QEDR_EDPM_TRANS_SIZE (64) 34 #define QEDR_EDPM_MAX_SIZE (ROCE_REQ_MAX_INLINE_DATA_SIZE) 35 enum qedr_rdma_dpm_type { 36 QEDR_DPM_TYPE_NONE = 0, 37 QEDR_DPM_TYPE_ROCE_ENHANCED = 1 << 0, 38 QEDR_DPM_TYPE_ROCE_LEGACY = 1 << 1, 39 QEDR_DPM_TYPE_IWARP_LEGACY = 1 << 2, 40 QEDR_DPM_TYPE_ROCE_EDPM_MODE = 1 << 3, 41 QEDR_DPM_SIZES_SET = 1 << 4, 42 }; 43 struct qedr_alloc_ucontext_resp { 44 __aligned_u64 db_pa; 45 __u32 db_size; 46 __u32 max_send_wr; 47 __u32 max_recv_wr; 48 __u32 max_srq_wr; 49 __u32 sges_per_send_wr; 50 __u32 sges_per_recv_wr; 51 __u32 sges_per_srq_wr; 52 __u32 max_cqes; 53 __u8 dpm_flags; 54 __u8 wids_enabled; 55 __u16 wid_count; 56 __u16 ldpm_limit_size; 57 __u8 edpm_trans_size; 58 __u8 reserved; 59 __u16 edpm_limit_size; 60 __u8 padding[6]; 61 }; 62 struct qedr_alloc_pd_ureq { 63 __aligned_u64 rsvd1; 64 }; 65 struct qedr_alloc_pd_uresp { 66 __u32 pd_id; 67 __u32 reserved; 68 }; 69 struct qedr_create_cq_ureq { 70 __aligned_u64 addr; 71 __aligned_u64 len; 72 }; 73 struct qedr_create_cq_uresp { 74 __u32 db_offset; 75 __u16 icid; 76 __u16 reserved; 77 __aligned_u64 db_rec_addr; 78 }; 79 struct qedr_create_qp_ureq { 80 __u32 qp_handle_hi; 81 __u32 qp_handle_lo; 82 __aligned_u64 sq_addr; 83 __aligned_u64 sq_len; 84 __aligned_u64 rq_addr; 85 __aligned_u64 rq_len; 86 }; 87 struct qedr_create_qp_uresp { 88 __u32 qp_id; 89 __u32 atomic_supported; 90 __u32 sq_db_offset; 91 __u16 sq_icid; 92 __u32 rq_db_offset; 93 __u16 rq_icid; 94 __u32 rq_db2_offset; 95 __u32 reserved; 96 __aligned_u64 sq_db_rec_addr; 97 __aligned_u64 rq_db_rec_addr; 98 }; 99 struct qedr_create_srq_ureq { 100 __aligned_u64 prod_pair_addr; 101 __aligned_u64 srq_addr; 102 __aligned_u64 srq_len; 103 }; 104 struct qedr_create_srq_uresp { 105 __u16 srq_id; 106 __u16 reserved0; 107 __u32 reserved1; 108 }; 109 struct qedr_user_db_rec { 110 __aligned_u64 db_data; 111 }; 112 #endif 113