1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __VMW_PVRDMA_ABI_H__ 20 #define __VMW_PVRDMA_ABI_H__ 21 #include <linux/types.h> 22 #define PVRDMA_UVERBS_ABI_VERSION 3 23 #define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF 24 #define PVRDMA_UAR_QP_OFFSET 0 25 #define PVRDMA_UAR_QP_SEND (1 << 30) 26 #define PVRDMA_UAR_QP_RECV (1 << 31) 27 #define PVRDMA_UAR_CQ_OFFSET 4 28 #define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) 29 #define PVRDMA_UAR_CQ_ARM (1 << 30) 30 #define PVRDMA_UAR_CQ_POLL (1 << 31) 31 #define PVRDMA_UAR_SRQ_OFFSET 8 32 #define PVRDMA_UAR_SRQ_RECV (1 << 30) 33 enum pvrdma_wr_opcode { 34 PVRDMA_WR_RDMA_WRITE, 35 PVRDMA_WR_RDMA_WRITE_WITH_IMM, 36 PVRDMA_WR_SEND, 37 PVRDMA_WR_SEND_WITH_IMM, 38 PVRDMA_WR_RDMA_READ, 39 PVRDMA_WR_ATOMIC_CMP_AND_SWP, 40 PVRDMA_WR_ATOMIC_FETCH_AND_ADD, 41 PVRDMA_WR_LSO, 42 PVRDMA_WR_SEND_WITH_INV, 43 PVRDMA_WR_RDMA_READ_WITH_INV, 44 PVRDMA_WR_LOCAL_INV, 45 PVRDMA_WR_FAST_REG_MR, 46 PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP, 47 PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD, 48 PVRDMA_WR_BIND_MW, 49 PVRDMA_WR_REG_SIG_MR, 50 PVRDMA_WR_ERROR, 51 }; 52 enum pvrdma_wc_status { 53 PVRDMA_WC_SUCCESS, 54 PVRDMA_WC_LOC_LEN_ERR, 55 PVRDMA_WC_LOC_QP_OP_ERR, 56 PVRDMA_WC_LOC_EEC_OP_ERR, 57 PVRDMA_WC_LOC_PROT_ERR, 58 PVRDMA_WC_WR_FLUSH_ERR, 59 PVRDMA_WC_MW_BIND_ERR, 60 PVRDMA_WC_BAD_RESP_ERR, 61 PVRDMA_WC_LOC_ACCESS_ERR, 62 PVRDMA_WC_REM_INV_REQ_ERR, 63 PVRDMA_WC_REM_ACCESS_ERR, 64 PVRDMA_WC_REM_OP_ERR, 65 PVRDMA_WC_RETRY_EXC_ERR, 66 PVRDMA_WC_RNR_RETRY_EXC_ERR, 67 PVRDMA_WC_LOC_RDD_VIOL_ERR, 68 PVRDMA_WC_REM_INV_RD_REQ_ERR, 69 PVRDMA_WC_REM_ABORT_ERR, 70 PVRDMA_WC_INV_EECN_ERR, 71 PVRDMA_WC_INV_EEC_STATE_ERR, 72 PVRDMA_WC_FATAL_ERR, 73 PVRDMA_WC_RESP_TIMEOUT_ERR, 74 PVRDMA_WC_GENERAL_ERR, 75 }; 76 enum pvrdma_wc_opcode { 77 PVRDMA_WC_SEND, 78 PVRDMA_WC_RDMA_WRITE, 79 PVRDMA_WC_RDMA_READ, 80 PVRDMA_WC_COMP_SWAP, 81 PVRDMA_WC_FETCH_ADD, 82 PVRDMA_WC_BIND_MW, 83 PVRDMA_WC_LSO, 84 PVRDMA_WC_LOCAL_INV, 85 PVRDMA_WC_FAST_REG_MR, 86 PVRDMA_WC_MASKED_COMP_SWAP, 87 PVRDMA_WC_MASKED_FETCH_ADD, 88 PVRDMA_WC_RECV = 1 << 7, 89 PVRDMA_WC_RECV_RDMA_WITH_IMM, 90 }; 91 enum pvrdma_wc_flags { 92 PVRDMA_WC_GRH = 1 << 0, 93 PVRDMA_WC_WITH_IMM = 1 << 1, 94 PVRDMA_WC_WITH_INVALIDATE = 1 << 2, 95 PVRDMA_WC_IP_CSUM_OK = 1 << 3, 96 PVRDMA_WC_WITH_SMAC = 1 << 4, 97 PVRDMA_WC_WITH_VLAN = 1 << 5, 98 PVRDMA_WC_WITH_NETWORK_HDR_TYPE = 1 << 6, 99 PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_NETWORK_HDR_TYPE, 100 }; 101 enum pvrdma_network_type { 102 PVRDMA_NETWORK_IB, 103 PVRDMA_NETWORK_ROCE_V1 = PVRDMA_NETWORK_IB, 104 PVRDMA_NETWORK_IPV4, 105 PVRDMA_NETWORK_IPV6 106 }; 107 struct pvrdma_alloc_ucontext_resp { 108 __u32 qp_tab_size; 109 __u32 reserved; 110 }; 111 struct pvrdma_alloc_pd_resp { 112 __u32 pdn; 113 __u32 reserved; 114 }; 115 struct pvrdma_create_cq { 116 __aligned_u64 buf_addr; 117 __u32 buf_size; 118 __u32 reserved; 119 }; 120 struct pvrdma_create_cq_resp { 121 __u32 cqn; 122 __u32 reserved; 123 }; 124 struct pvrdma_resize_cq { 125 __aligned_u64 buf_addr; 126 __u32 buf_size; 127 __u32 reserved; 128 }; 129 struct pvrdma_create_srq { 130 __aligned_u64 buf_addr; 131 __u32 buf_size; 132 __u32 reserved; 133 }; 134 struct pvrdma_create_srq_resp { 135 __u32 srqn; 136 __u32 reserved; 137 }; 138 struct pvrdma_create_qp { 139 __aligned_u64 rbuf_addr; 140 __aligned_u64 sbuf_addr; 141 __u32 rbuf_size; 142 __u32 sbuf_size; 143 __aligned_u64 qp_addr; 144 }; 145 struct pvrdma_create_qp_resp { 146 __u32 qpn; 147 __u32 qp_handle; 148 }; 149 struct pvrdma_ex_cmp_swap { 150 __aligned_u64 swap_val; 151 __aligned_u64 compare_val; 152 __aligned_u64 swap_mask; 153 __aligned_u64 compare_mask; 154 }; 155 struct pvrdma_ex_fetch_add { 156 __aligned_u64 add_val; 157 __aligned_u64 field_boundary; 158 }; 159 struct pvrdma_av { 160 __u32 port_pd; 161 __u32 sl_tclass_flowlabel; 162 __u8 dgid[16]; 163 __u8 src_path_bits; 164 __u8 gid_index; 165 __u8 stat_rate; 166 __u8 hop_limit; 167 __u8 dmac[6]; 168 __u8 reserved[6]; 169 }; 170 struct pvrdma_sge { 171 __aligned_u64 addr; 172 __u32 length; 173 __u32 lkey; 174 }; 175 struct pvrdma_rq_wqe_hdr { 176 __aligned_u64 wr_id; 177 __u32 num_sge; 178 __u32 total_len; 179 }; 180 struct pvrdma_sq_wqe_hdr { 181 __aligned_u64 wr_id; 182 __u32 num_sge; 183 __u32 total_len; 184 __u32 opcode; 185 __u32 send_flags; 186 union { 187 __be32 imm_data; 188 __u32 invalidate_rkey; 189 } ex; 190 __u32 reserved; 191 union { 192 struct { 193 __aligned_u64 remote_addr; 194 __u32 rkey; 195 __u8 reserved[4]; 196 } rdma; 197 struct { 198 __aligned_u64 remote_addr; 199 __aligned_u64 compare_add; 200 __aligned_u64 swap; 201 __u32 rkey; 202 __u32 reserved; 203 } atomic; 204 struct { 205 __aligned_u64 remote_addr; 206 __u32 log_arg_sz; 207 __u32 rkey; 208 union { 209 struct pvrdma_ex_cmp_swap cmp_swap; 210 struct pvrdma_ex_fetch_add fetch_add; 211 } wr_data; 212 } masked_atomics; 213 struct { 214 __aligned_u64 iova_start; 215 __aligned_u64 pl_pdir_dma; 216 __u32 page_shift; 217 __u32 page_list_len; 218 __u32 length; 219 __u32 access_flags; 220 __u32 rkey; 221 __u32 reserved; 222 } fast_reg; 223 struct { 224 __u32 remote_qpn; 225 __u32 remote_qkey; 226 struct pvrdma_av av; 227 } ud; 228 } wr; 229 }; 230 struct pvrdma_cqe { 231 __aligned_u64 wr_id; 232 __aligned_u64 qp; 233 __u32 opcode; 234 __u32 status; 235 __u32 byte_len; 236 __be32 imm_data; 237 __u32 src_qp; 238 __u32 wc_flags; 239 __u32 vendor_err; 240 __u16 pkey_index; 241 __u16 slid; 242 __u8 sl; 243 __u8 dlid_path_bits; 244 __u8 port_num; 245 __u8 smac[6]; 246 __u8 network_hdr_type; 247 __u8 reserved2[6]; 248 }; 249 #endif 250